Programmable Interrupt Processing Patents (Class 710/266)
  • Patent number: 10776177
    Abstract: Event data for an application execution is accessed from a table of logged events, the event data comprising a sequence, a hierarchy, and a start time and duration for each event. Dependency data for each event is also accessed to determine whether the start time for an event is dependent on the prior completion of at least one other event. A waterfall representation is then generated, the representation including an entry for each event in the sequence, with a start time and duration represented for each event. Based on the dependencies and hierarchy, it is determined, for each event with a start time that is later than the start time of an event which precedes it in the sequence, whether the event's start time is dependent on the prior completion of at least one preceding event. The start time for each event may then be advanced based on the determination.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: September 15, 2020
    Assignee: eBay Inc.
    Inventor: Dmytro Semenov
  • Patent number: 10699269
    Abstract: A Turing incomplete smart contracting source code for use in a blockchain network is disclosed that allows for static analysis of a smart contract at the time of publishing.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: June 30, 2020
    Assignee: Blockstack PBC
    Inventors: Aaron Blankstein, Jude Nelson
  • Patent number: 10579502
    Abstract: Aspects include receiving, at a pass-through server executing in a replay mode, a request directed to a backend resource. The request is received from an application that is connected to the pass-through server. The pass-through server executing in the replay mode identifies a response that corresponds to the request by: forming a key that includes an identifier of the current execution phase of the application and at least a subset of the request; accessing trace data that includes a plurality of keys and corresponding responses that were previously recorded in the trace data by the pass-through server executing in a recording mode; and using the key to locate, in the trace data, the response corresponding to the request. The identified response is relayed, by the pass-through server executing in the replay mode, to the application.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joshua H. Armitage, Michael P. Clarke, John A. Kaputin, King-Yan Kwan, Andrew Wright
  • Patent number: 10466903
    Abstract: Systems and methods for dynamic and adaptive interrupt coalescing are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device notifies the host device, via an interrupt, of entries on the completion queue. However, excessive interrupts become a burden to the host device. In that regard, the memory device includes a dynamic and adaptive interrupt coalescing methodology according to one or more parameters including: the completion queue; the commands; the queue depth; latency; and memory device firmware settings. In this way, the memory device may reduce the number of interrupts while still notifying the host device in a timely manner.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: November 5, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Eran Erez
  • Patent number: 10318456
    Abstract: In an approach to validation of correctness of interrupt triggers and delivery a computer allocates one or more flags of a gang of flags. The computer allocates one or more interrupt source numbers, wherein each interrupt source number of the one or more interrupt source numbers corresponds to a flag of the gang of flags. The computer allocates one or more virtual processors to process the one or more interrupt source numbers. The computer schedules the one or more virtual processors. The computer receives one or more interrupt triggers corresponding to the one or more interrupt source numbers. The computer updates the one or more flags corresponding to the one or more received interrupt triggers. The computer determines whether all of the one or more flags in the gang of flags is updated. The computer determines a lost interrupt source number.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Shakti Kapoor, Brenton Yiu, Siva Sundar A
  • Patent number: 10225287
    Abstract: Methods, devices, and systems are described to modify the life cycle of a Google Android® application, in its application manifest file and byte code, such that the execution of the application can be controlled via policies and security governed by a workspace application installed on an Android-based device. Dummy wrapper classes are inserted into the byte code for network and I/O system calls that call security code before calling the original classes.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: March 5, 2019
    Assignee: Oracle International Corporation
    Inventors: Mohammad Aamir, Atta Ur Rehman
  • Patent number: 10216532
    Abstract: Systems and techniques for memory and resource management in a virtual computing environment are disclosed herein. For example, in some embodiments, an apparatus for memory management in a virtual computing environment may include: a storage device; memory page comparison logic, coupled to the storage device, to determine that a first memory page of instructions, stored in the storage device, for a guest machine in the virtual computing environment is identical to a second memory page of instructions, stored in the storage device, for a host machine in the virtual computing environment, wherein the guest machine is hosted by the host machine; and merge logic, coupled to the memory page comparison logic, to, in response to a determination that the first memory page is identical to the second memory page, map the first memory page to the second memory page. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Yao Zu Dong, Kun Tian
  • Patent number: 10191878
    Abstract: A method is implemented by a network device to configure the operation of a Peripheral Component Interconnect Express (PCIe) switch to enable an efficient transition from a first active processor in a first root complex to a backup processor in a second root complex. The method involves determining the first active processor in the first root complex and a set of backup processors and a set of root complexes, and configuring each root complex for independent PCIe switch communication. The method further includes detecting a failure of the active processor in the first root complex, selecting and notifying the backup processor and the second root complex to transition to be a second active processor and second root complex, and starting communication with PCIe devices using previously configured independent PCIe switch communication for the second processor of the second root complex.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: January 29, 2019
    Assignee: Tolefonaktiebolaget LM Ericsson (Publ)
    Inventors: Gaurav Garg, Tong Ho
  • Patent number: 10151796
    Abstract: A semiconductor apparatus includes a storage circuit, a processing circuit that performs processing using data stored in the storage circuit and writes data into the storage circuit as the processing is performed, a scan test circuit that executes a scan test on the processing circuit when the processing circuit does not perform processing, and an inhibit circuit that inhibits writing of data from the processing circuit to the storage circuit when the scan test on the processing circuit is executed.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: December 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Shibahara, Daisuke Kawakami, Yutaka Igaku
  • Patent number: 10055263
    Abstract: Event data for an application execution is accessed from a table of logged events, the event data comprising a sequence, a hierarchy, and a start time and duration for each event. Dependency data for each event is also accessed to determine whether the start time for an event is dependent on the prior completion of at least one other event. A waterfall representation is then generated, the representation including an entry for each event in the sequence, with a start time and duration represented for each event. Based on the dependencies and hierarchy, it is determined, for each event with a start time that is later than the start time of an event which precedes it in the sequence, whether the event's start time is dependent on the prior completion of at least one preceding event. The start time for each event may then be advanced based on the determination.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 21, 2018
    Assignee: eBay Inc.
    Inventor: Dmytro Semenov
  • Patent number: 9971605
    Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate multiple of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate a single processing core of the plurality of processing cores to be the bootstrap processor.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: May 15, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: G. Glenn Henry, Stephan Gaskins
  • Patent number: 9959225
    Abstract: At start-up of a computer apparatus, a CPU executes a first initialization procedure included in a RAS module to initialize resources to be used by the RAS module. After execution of the first initialization procedure, the CPU executes an initialization procedure included in an OS to initialize resources to be used by the OS. After execution of the initialization procedure, the CPU executes a second initialization procedure included in the RAS module to copy an interrupt determining part included in the OS to the RAS module, and to set the interrupt detection unit such that upon detecting an interrupt the interrupt detection unit calls an interrupt determining part copied to the RAS module, instead of the interrupt determining part in the OS.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: May 1, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Toshiro Tokunaga, Atsushi Settsu
  • Patent number: 9917827
    Abstract: This invention relates to methods for controlling and monitoring access to network servers. In particular, the process described in the invention includes client-server sessions over the Internet. In this environment, when the user attempts to access an access-controlled file, the server subjects the request to a secondary server which determines whether the client has an authorization or valid account. Upon such verification, the user is provided with a session identification which allows the user to access to the requested file as well as any other files within the present protection domain.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: March 13, 2018
    Assignee: Soverain IP, LLC
    Inventors: Thomas Mark Levergood, Lawrence C. Stewart, Stephen Jeffrey Morris, Andrew C. Payne, George Winfield Treese
  • Patent number: 9880842
    Abstract: A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 30, 2018
    Assignee: Intel Corporation
    Inventors: Jayaram Bobba, Ruchira Sasanka, Jeffrey J. Cook, Abhinav Das, Arvind Krishnaswamy, David J. Sager, Jason M. Agron
  • Patent number: 9836371
    Abstract: A method, system, and computer program product for performing user-initiated logging and auto-correction in hardware/software systems. Embodiments commence upon identifying a set of test points and respective instrumentation components, then determining logging capabilities of the instrumentation components. The nature and extent of the capabilities and configuration of the components aid in generating labels to describe the various logging capabilities. The labels are then used in a user interface so as to obtain user-configurable settings which are also used in determining auto-correction actions. A measurement taken at a testpoint may result in detection of an occurrence of a certain condition, and auto-correction steps can be taken by retrieving a rulebase comprising a set of conditions corresponding to one or more measurements, and corrective actions corresponding to the one or more conditions.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: December 5, 2017
    Assignee: Oracle International Corporation
    Inventors: Chae Hun Jeong, Christopher Bartlett Papineau, Pradip Kumar Pandey, Gurbinder Singh Bali
  • Patent number: 9824034
    Abstract: Embodiments include method, systems and computer program products for a parallel ordering queue using an encoded command type. In some embodiments, a command may be receive from a receiver of a first bus, wherein the command is to be sent to a second bus. The command may be decoded. The command may be associated with an encoded command type. The command may be placed in an ordering queue. A first entry of a second queue may be popped based on the encoded command type of the first entry of the ordering queue. The first entry of the ordering queue may be removed from the ordering queue.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: November 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jie Zheng
  • Patent number: 9684613
    Abstract: A storage controller of a data storage system maintains, for each interrupt vector, (1) a pending status that indicates whether one or more completions are pending in the completion queue (CQ) associated with the interrupt vector, and (2) an in-progress status that indicates whether or not the storage controller is currently in the process of composing an interrupt. The storage controller utilizes these two statuses to reduce or eliminate spurious interrupts by preventing an interrupt from being composed if there are no completions in the CQ, by preventing an interrupt from being composed if the corresponding interrupt mask has been set before composition of the interrupt begins, and by preventing an interrupt from being sent to the host system in cases where the interrupt mask was set after composition of the interrupt began, but before the interrupt has been sent to the host system.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: June 20, 2017
    Assignee: Seagate Technology LLC
    Inventors: Nital Patwa, Timothy Canepa, Yimin Chen
  • Patent number: 9465681
    Abstract: Embodiments are directed to systems and methodologies for allowing a computer program code to efficiently respond to and process events. For events having a multiple stage completion sequence, and wherein several of the events occur within relatively close time proximity to each other, portions of the multiple stages may be coalesced without adding latency, thereby maintaining responsiveness of the computer program. The disclosed coalescing systems and methodologies include state machines and counters that in effect “replace” certain stages of the event sequence when the frequency of events increases.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 11, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas A. Gregg, Kulwant M. Pandey
  • Patent number: 9450935
    Abstract: A shell device with minimal software and/or hardware resources can download from a server configuration information and/or user data in order to allow the shell device to communicate with other computing devices (whether cell phones, personal digital assistants, laptops, and the like). Various security features can also be used herein, including a shell device password and a server network access password. In another aspect, any time code and/or data is downloaded from the server to the shell device, such code and/or data resides on the shell device during the time of a communication between the server and the shell device; thereafter, it can be deleted, thereby returning the shell device to its minimalistic resource state. When the shell device contacts the server again and attempts to establish another communication, such code and/or data can be downloaded anew, and after the communication it can be deleted again.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: September 20, 2016
    Assignee: UNITED SERVICES AUTOMOBILES ASSOCIATION (USAA)
    Inventors: Charles L. Oakes, III, Reynaldo Medina, III, Bradly J. Billman
  • Patent number: 9442808
    Abstract: A ticket request is transmitted from an execution engine to an authentication engine. In response, a ticket comprising privileges is received from the authentication engine. The ticket is transmitted to a client, and a service request including the ticket is received back from the client. A service is executed in response to the ticket received from the client and results are transmitted to the client.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 13, 2016
    Assignee: EMC CORPORATION
    Inventors: Michal J Drozd, Michael G Roche, Aliaksandr Shtop
  • Patent number: 9442869
    Abstract: A multiprocessor device is provided that includes a plurality of processors in which each processor of the plurality of processors includes an interrupt controller, and a symmetric interrupt crossbar having a plurality of interrupt inputs in which each interrupt input that is not reserved is coupled to a respective interrupt output of an interrupt source of a plurality of interrupt sources, and a plurality of interrupt outputs in which each interrupt output is coupled to a respective interrupt input of an interrupt controller of one of the plurality of processors, in which the symmetric interrupt crossbar is programmable to map an interrupt signal from any interrupt source of the plurality of interrupt sources coupled to the symmetric interrupt crossbar to any interrupt input of any interrupt controller coupled to the symmetric interrupt crossbar.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: September 13, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Vasant Easwaran
  • Patent number: 9389979
    Abstract: A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: July 12, 2016
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS S.R.L.
    Inventors: Daniele Mangano, Ignazio Antonino Urzi
  • Patent number: 9367376
    Abstract: A drive control device includes: an embedded microcontroller including a program for outputting a drive control signal to a driving unit; a first timer circuit for outputting a cyclic signal to the embedded microcontroller, wherein the embedded microcontroller reads the cyclic signal outputted from the first timer circuit and transmits the cyclic signal to output a transmission signal as part of operation of the program; and a second timer circuit provided externally to the embedded microcontroller, wherein the transmission signal is inputted to the second timer circuit, the second timer circuit obtains temporal change of the transmission signal for a time set in advance, and the second timer circuit outputs, based on the obtained result, a signal indicating one of different operation states of the embedded microcontroller depending on whether or not there is continuous temporal change of the transmission signal.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: June 14, 2016
    Assignee: Riso Kagaku Corporation
    Inventor: Masao Suzuki
  • Patent number: 9344422
    Abstract: Methods, devices, and systems are described to modify the life cycle of a Google Android® application, in its application manifest file and byte code, such that the execution of the application can be controlled via policies and security governed by a workspace application installed on an Android-based device. Dummy wrapper classes are inserted into the byte code for network and I/O system calls that call security code before calling the original classes.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: May 17, 2016
    Assignee: Oracle International Corporation
    Inventors: Mohammad Aamir, Atta Ur Rehman
  • Patent number: 9304802
    Abstract: With N_Port ID Virtualization (NPIV), a managed system can be configured so that multiple logical partitions (LPARs) can access independent physical storage through the same physical fiber channel adapter. An NPIV client recovery component of a virtualization management component, such as a Power Hypervisor (pHYP), provides the emulation mapping between server and client virtual fiber channel adapters. The pHYP also provides a mechanism that prevents client partition crashes when the NPIV server (e.g., a VIOS logical partition) goes down. When the NPIV server is rebooted or powers down, the pHYP handles the client LPARs to avoid a crash by removing processing resources from the client logical partition. Thereby, the client logical partition is prevented from attempting to access a root volume group in physical storage via the NPIV server. The pHYP allocates processor resources to the client LPAR when the NPIV server is again available for I/O processing.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: April 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael Paul Cyr, James A. Pafumi, Veena Ganti, Vasu Vallabhaneni
  • Patent number: 9235542
    Abstract: A signal switching circuit allows a PCIe card access to additional data channels when installation of the PCIe cards on first and second PCIe connectors are detected. First and second PCIe connectors output a first detection signal when each of the first and second PCIe connectors receives a PCIe card. The first and second PCIe connectors output a second detection signal when each of the first and second PCIe connectors does not receive a PCIe card. A first multiplexer receives the first or second detection signal and connects an input terminal to first or second output terminal of the first multiplexer, to transmit PCIe signals to the first or second PCIe connector. A second multiplexer receives the first or second detection signal and connects an input terminal to first or second output terminal of the second multiplexer, to transmit PCIe signals to the first or second PCIe connectors.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: January 12, 2016
    Assignee: Zhongshan Innocloud Intellectual Property Services Co., Ltd.
    Inventors: Lei Liu, Guo-Yi Chen
  • Patent number: 9178757
    Abstract: One embodiment describes a fault tolerant transmission system that includes a programmable logic device. The programmable logic device includes a first serial port communicatively coupled to a first serial link, in which the first serial port receives a first transmission signal from the first serial link, and a second serial port communicatively coupled to a second serial link, in which the second serial port receives a second transmission signal from the second serial link. The first serial link and the second serial link are disposed in parallel with each other and communicate over a first single conduit, and the first communication signal and the second communication signal are representative of identical information.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: November 3, 2015
    Assignee: General Electric Company
    Inventors: Richard Joseph Glosser, Jr., Michael Glynn Wise, Steven James Schmitt
  • Patent number: 9116869
    Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: August 25, 2015
    Assignee: Intel Corporation
    Inventors: Rajesh Sankaran Madukkarumukumana, Gilbert Neiger, Ohad Falik, Sridhar Muthrasanallur, Gideon Gerzon
  • Patent number: 9098431
    Abstract: Methods and systems for conducting a transaction between a virtual USB device driver and a USB device client are provided. A hypervisor of a computer system receives one or more data packets from the client. The hypervisor stores the one or more data packets in a buffer. The hypervisor dequeues a data packet from the buffer. The hypervisor transmits the data packet to the virtual USB device driver.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: August 4, 2015
    Assignee: Red Hat, Inc.
    Inventor: Hans de Goede
  • Patent number: 9054885
    Abstract: A method and system for distributing audio, visual, data, annunciator and other information within an educational facility utilizes a bit-wise addressing scheme to route UDP message packets to individual classrooms. The audio/video network system includes a central processor that controls a plurality of audio/video sources (e.g., DVD players, cable TV receivers, etc.). Output from audio/video sources is encoded by audio/video encoders for transmission via a local area network. Classroom control hubs within each classroom recognize data packets addressed with the bit-wise addressing scheme and in combination with a video decoder, recover the encoded audio/video signal for presentation within the classroom, such as by a video projector and classroom speakers. Transmitting audio/video information in UDP packets addressed with the bit-wise addressing scheme enables near simultaneous presentation of audio and video programs throughout the educational facility.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: June 9, 2015
    Assignee: AMX, LLC
    Inventor: Sheldon M. Samuels
  • Patent number: 9026705
    Abstract: Techniques are disclosed relating to systems that allow sending and receiving of interrupts between processing elements. In various embodiments, a system includes an interrupt processing unit that in turn includes various indicators corresponding to processing elements. In some embodiments, the interrupt processing unit may be configured to receive an interrupt and determine whether a first processing element associated with the interrupt is available to receive interrupts. The system may initiate a corrective action if the first processing element is not available to receive interrupts. In some embodiments, the corrective action may include redirecting the interrupt to a second processing element. In some embodiments, the interrupt processing unit may include a dropped interrupt management register to store information corresponding to the second processing element.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: May 5, 2015
    Assignee: Oracle International Corporation
    Inventors: John R. Feehrer, Fred Han-Ching Tsai, Ali Vahidsafa, Sumti Jairath
  • Patent number: 9003094
    Abstract: A computing apparatus determines that a virtual processor of a guest has been moved from a first physical processor of a host to a second physical processor of the host. The computing apparatus identifies a device that is controlled by the virtual processor, wherein device interrupts for the device are forwarded to the virtual processor. The computing apparatus updates at least one of the device or an interrupt controller to cause at least one of the device or the interrupt controller to send the device interrupts to the second physical processor of the host, wherein the second physical processor of the host forwards the device interrupts to the virtual processor running on the second physical processor without generating an inter-processor interrupt.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 7, 2015
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael S. Tsirkin, Avi Kivity
  • Patent number: 8971537
    Abstract: The client requests from the authentication and authorization server a capability for accessing the target server. The authentication and authorization server sends client a capability (capC,S) comprising the public key (pubC) of the client, said capability being signed with a private key (privAA) of the authentication and authorization server. The client sends the capability (capC,S) to the target server. If the capability is valid, the target server grants the client access and a data exchange session can be initiated. The disclosed protocol is scalable, as it does not require individual configuration of each target server device, allows revocation of user access within reasonable time, stores no compromisable secret data on any target server device, enables individual access permission per user, and accountability of each user.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: March 3, 2015
    Assignee: ABB Research Ltd
    Inventor: Martin Naedele
  • Patent number: 8966149
    Abstract: Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Bruce Fleming, Arvind Mandhani
  • Patent number: 8938737
    Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: January 20, 2015
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A. Uhlig, Udo Steinberg, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M. Bennett, Andrew V. Anderson, Erik C. Cota-Robles
  • Publication number: 20150019780
    Abstract: An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.
    Type: Application
    Filed: September 10, 2014
    Publication date: January 15, 2015
    Inventors: Ronald K. Kreuzenstein, Elizabeth A. Moore, Alberto Poggesi
  • Patent number: 8924615
    Abstract: A global interrupt number space 38 is provided for use in message signalled interrupts. Interrupt destinations 10, 12, 14, 16 are provided with pending interrupt caches 24 with either backing storage provided by global pending status memory 34 shared by all the caches or separate individual pending status memories 56. The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 30, 2014
    Assignee: ARM Limited
    Inventors: Richard Roy Grisenthwaite, Anthony Jebson, Andrew Christopher Rose, Matthew Lucien Evans
  • Patent number: 8914566
    Abstract: A process for managing interrupts, which may be performed using electronic circuitry, includes: receiving interrupts bound for a processing device, where the interrupts are received from hardware devices that are configured to communicate with the processing device; generating data containing information corresponding to the interrupts; and sending the data to the processing device.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: December 16, 2014
    Assignee: Teradyne, Inc.
    Inventors: David Vandervalk, Lloyd K. Frick
  • Patent number: 8909836
    Abstract: An interrupt controller coupled to a plurality of processors is provided to rout at least one interrupt request event to at least one of the processors. The interrupt controller includes a receiving circuit and a controlling circuit. The receiving circuit receives at least one interrupt input, and the controlling circuit, generates the at least one interrupt request event based on the received at least one interrupt input and routes the at least one interrupt request event generated to the at least one of the processors. The plurality of processors including at least a first processor and a second processor, the first and second processors arranged to process interrupt request event(s), and the controlling circuit is arranged to withdraw/cancel assertion of an interrupt request event that has been transmitted to the first processor.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: December 9, 2014
    Assignee: Andes Technology Corporation
    Inventors: Hsin-Ming Chen, Chi-Chang Lai
  • Patent number: 8909835
    Abstract: CPU architecture is modified so that content of the interrupt mask register can be changed directly based on a decoding result of an instruction decoder of a CPU. Such modification does not require a great deal of labor in changing a CPU design. In addition, an extended CALL instruction and an extended software interrupt instruction are added to the CPU, and each of the extended CALL instruction and the extended software interrupt instruction additionally has a function of changing the value of the interrupt mask register. Atomicity is achieved by: allowing such a single instruction to concurrently execute a call of a process and a value change of the interrupt mask register; and disabling other interrupts during execution of the single instruction.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Masaki Kataoka, Hideaki Komatsu
  • Patent number: 8898361
    Abstract: Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt priorities of the memory based upon the interrupt processing criteria without losing incoming processing requests for the system. Additionally, the processor is operable to process the incoming interrupts according to the modified interrupt priorities responsive to modifying the interrupt priorities.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: November 25, 2014
    Assignee: LSI Corporation
    Inventor: Sourin Sarkar
  • Patent number: 8880764
    Abstract: A computing apparatus identifies that a first physical processor of a host has forwarded information regarding a device interrupt for a device to a second physical processor executing at least one of a virtual processor that controls the device or an application thread that controls the device. After identifying that the first physical processor has forwarded the information regarding the device interrupt to the second physical processor and in response to determining that one or more update criteria have been satisfied, the computing apparatus updates at least one of the device or an interrupt controller to cause at least one of the device or the interrupt controller to send future device interrupts for the device to the second physical processor.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: November 4, 2014
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael S. Tsirkin, Avi Kivity
  • Patent number: 8856416
    Abstract: Numerous embodiments of a method and apparatus for processing latency sensitive electronic data with interrupt moderation are disclosed.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: October 7, 2014
    Assignee: Intel Corporation
    Inventors: Linden Minnick, Patrick L. Connor
  • Patent number: 8838852
    Abstract: A method and apparatus to operate programmable routing logic comprise receiving, from a fixed function block, a first request, responsive to the first request, forwarding the first request to a first resource of one or more controllers, the first resource allocated to the fixed function block. The method and apparatus further comprise receiving, from a programmable function block, a second request, and responsive to the second request, forwarding the second request to a second resource of the one or more controllers, the second resource allocated to the programmable function block.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: September 16, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Bert Sullam, Haneef Mohammed
  • Publication number: 20140250250
    Abstract: An apparatus, method, system, and computer-readable medium are disclosed. In one embodiment the apparatus is a processor. The processor includes thread remapping logic that is capable of tracking hardware thread interrupt equivalence information for a first hardware thread and a second hardware thread. The processor also includes logic to receive an interrupt issued from a device, wherein the interrupt has an affinity tied to the first hardware thread. The processor also includes logic to redirect the interrupt to the second hardware thread when the hardware thread interrupt equivalence information validates the second hardware thread is capable of handling the interrupt.
    Type: Application
    Filed: May 15, 2014
    Publication date: September 4, 2014
    Inventor: Ramakrishna Saripalli
  • Patent number: 8811417
    Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: August 19, 2014
    Assignee: Mellanox Technologies Ltd.
    Inventors: Noam Bloch, Gil Bloch, Ariel Shachar, Hillel Chapman, Ishai Rabinovitz, Pavel Shamis, Gilad Shainer
  • Publication number: 20140189184
    Abstract: One particular example implementation of an apparatus that includes logic, the logic at least partially comprising hardware logic to: trigger a particular interrupt based, at least in part, on input/output (I/O) activity when a predetermined state is activated on a platform; generate a system control interrupt based, at least in part, on a source associated with the particular interrupt; and route the system control interrupt to a custom system control interrupt handler.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Nicholas Adams, Robert Gough, Gary Lee
  • Patent number: 8719589
    Abstract: A microprocessor includes a storage element having a plurality of locations each storing decryption key data associated with an encrypted program. A control register field (may be x86 EFLAGS register reserved field) specifies a storage element location associated with a currently executing encrypted program. The microprocessor restores from memory to the control register a previously saved value of the field in response to executing a return from interrupt instruction. A fetch unit fetches encrypted instructions of the currently executing encrypted program and decrypts them using the decryption key data stored the storage element location specified by the restored field value. A kill bit associated with each storage element location may be employed if the location is clobbered because more encrypted programs are multitasked than available locations in the storage element, in which case an exception is generated to re-load the clobbered decryption key data in response to the return from interrupt instruction.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: May 6, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: G. Glenn Henry, Terry Parks, Brent Bean, Thomas A. Crispin
  • Patent number: 8694688
    Abstract: A hardware support system for implementing accelerated disk I/O for a computer system. The system includes a bus interface for interfacing with a processor and a system memory of the computer system, a disk I/O engine coupled to the bus interface, and a device interface coupled to the disk I/O engine for interfacing the disk I/O engine with a disk drive. The disk I/O engine is configured to cause a start up of the disk drive upon receiving a disk start up command from the processor. The disk I/O engine is further configured to execute a disk transaction by processing the disk transaction information from a bypass register coupled to the disk I/O engine.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: April 8, 2014
    Assignee: NVIDIA Corporation
    Inventors: Radoslav Danilak, Krishnaraj S. Rao
  • Patent number: 8656079
    Abstract: A method and apparatus are provided for controlling system management interrupts is disclosed. The method comprises: receiving an interrupt signal; determining a type associated with the interrupt signal; using the determined type to access control information indicating an action to be applied to the determined type of interrupt; and blocking, passing or remapping the interrupt signal in response to the control information. The apparatus comprises a memory, an interrupt unit and a logic circuit. The memory is adapted to store control information regarding a plurality of types of interrupt signals. The interrupt unit is adapted to receive the interrupt signal, and use the interrupt type contained in the interrupt signal to access the control information stored in the memory. The logic circuit is adapted to block, pass or remap said interrupt signal in response to the control information.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: February 18, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andrew G. Kegel, Michael D. Vance