Abstract: A port of a computing device is to communicate with another device over a link, the port including physical layer logic of a first protocol, link layer logic of each of a plurality of different protocols, and protocol negotiation logic to determine which of the plurality of different protocols to apply on the link. The protocol negotiation logic is to send and receive ordered sets in a configuration state of a link training state machine of the first protocol, where the ordered sets include an identifier of a particular one of the plurality of different protocols. The protocol negotiation logic is to determine from the ordered sets that a link layer of the particular protocol is to be applied on the link.

Abstract: A method for providing varying amounts of simulated latencies for a mainframe is disclosed. The method includes modifying routing to pass through a simulated latency injector system; setting an initial latency amount for the target mainframe; when the mainframe application is determined to be unstable, modifying the OSA routing to bypass the simulated latency injector system; when the mainframe application is determined to be stable in the first monitoring, initiating a planned latency injection schedule for injecting latencies in differing amounts until a target latency amount is reached; performing monitoring for the stability of the mainframe application; modifying an injected latency amount back to the initial latency amount when the mainframe application is determined to be unstable in the monitoring; and applying another latency amount specified in the planned latency injection schedule when the mainframe application is determined to be stable.

Abstract: Aspects of the embodiments are directed to a port comprising hardware to support the multi-lane link, the link comprising a lane that comprises a first differential signal pair and a second differential signal pair. Link configuration logic, implemented at least in part in hardware circuitry, can determine that the port comprises hardware to support one or both of receiving data on the first differential signal pair or transmitting data on the second differential signal pair, and reconfigure the first differential signal pair to receive data with the second differential signal pair or reconfigure the second differential signal pair to transmit data with the first differential signal pair; and wherein the port is to transmit data or receive data based on reconfiguration of one or both the first differential signal pair and the second differential signal pair.

Abstract: A system includes a first integrated circuit package including a first group of one or more artificial intelligence processing units and a first chip-to-chip interconnect communication unit and a second integrated circuit package including a second group of one or more artificial intelligence processing units and a second chip-to-chip interconnect communication unit. The system also includes an interconnect between the first integrated circuit package and the second integrated circuit package, wherein the first chip-to-chip interconnect communication unit and the second chip-to-chip interconnect communication unit manage ethernet-based communication via the interconnect using a layered communication architecture supporting a credit-based data flow control and a retransmission data flow control.

Abstract: Aspects relate to link speed for a peripheral component interconnect. In one aspect, an apparatus includes an interface circuit configured to provide an interface with a multiple lane data link, the data link having a first set of lanes in an active state and a second set of lanes in an idle state and a controller. The controller is configured to receive a request at the controller to change a data rate of the data link to a requested data rate, change the second set of lanes from an idle state to an active state, train the second set of lanes to the requested data rate, transfer data traffic from the first set of lanes to the second set of lanes after the training, and transmit the data traffic on the second set of lanes.

Abstract: The present technology relates to an information processing system, information processing method, and information processing device capable of reducing load on an information processing unit in a case where data is shared among a plurality of information processing devices.

Abstract: Aspects relate to power management for a peripheral component interconnect. Transmit traffic activity may be monitored for a peripheral component interconnect express (PCIe) link. Receive traffic activity may also be monitored for the link A first power of transmit lines of the link is managed as a transmit group in accordance with the transmit traffic activity. A second power of the receive lines of the link are managed as a receive group in accordance with the receive traffic activity. The first power of the transmit lines is managed independently of the second power of the receive lines.

Abstract: An electronic device connectable to a network interface device having a plurality of signal lanes may include a first computing device, a second computing device, and an interface to connect the first computing device to a first subset of signal lanes of the plurality of data lanes of the network interface device and connect the second computing device to a second subset of data lanes of the plurality of data lanes of the network computing device.

Abstract: In embodiments, an apparatus for serial communication includes a transceiver, to receive a precoding request from a downlink receiver across a serial communication link, and to transmit data bits to the downlink receiver over the serial communication link. In embodiments, the apparatus further includes a precoder, coupled to the transceiver, to: receive scrambled data bits of a subset of the data bits to be transmitted, from a coupled scrambler, and, in response to the request from the downlink receiver, precode the scrambled data bits, and output the precoded scrambled data bits to the transceiver, for transmission to the downlink receiver across the serial communication link together with other unscrambled data bits.

Abstract: A collection device includes a deciding unit that, on the basis of data obtained in advance for each area, decides a collection interval and a collection time for each of the areas, a communication unit that acquires a current position from each of measurement terminals, and an allocating unit that, in a case where there is an area corresponding to the current position acquired regarding each of the measurement terminals, calculates a slot count of slots regarding which the collection interval and the collection time are cyclically allocated, on the basis of the collection interval and the collection time of this area, and allocates slot Nos. of an amount equivalent to the slot count, to any of the measurement terminals present in this area, by a predetermined method. The communication unit transmits, to each of the measurement terminals to which slot Nos.

Abstract: A memory controller selects from among a plurality of memory access commands including volatile memory reads, volatile memory writes, non-volatile memory reads, and non-volatile memory writes. The selected memory access commands are transmitted to a heterogenous memory channel coupled to a non-volatile memory and a volatile memory. The non-volatile read commands that are transmitted are stored in a non-volatile command queue (NV queue). A ready response is received from the non-volatile memory indicating that responsive data is available for an associated one of the non-volatile read commands. In response to receiving the ready response, a send command is transmitted for commanding the non-volatile memory to send the responsive data.

Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.

Abstract: Disclosed is a system, central control device, an application device for the Internet of things and communication methods applied to the Internet of Things system. The Internet of Things includes the center control and a plurality of application devices, wherein the central control device includes: a central control unit configured to perform a central control function of the central control device under control of a first clock signal; an asynchronous communication unit configured to perform data communication between the central control device and a plurality of application devices in the Internet of Things by using an asynchronous circuit; a synchronous-asynchronous interface configured to perform data transmission between the central control unit and the asynchronous communication unit.

Abstract: Enabling a protocol for efficiently and reliably using the NVME protocol over a network, referred to as NVME over Network, or NVMEoN, may include an NVMEoN exchange layer for handling exchanges between initiating and target nodes on a network, a burst transmission protocol that provides guaranteed delivery without duplicate retransmission, and an exchange status block approach to manage state information about exchanges.

Abstract: A network device decrypts a record, received from a client device, that is associated with an encrypted session between the client device and an application platform. The network device incorporates decrypted record data, from the decrypted record, into a payload field of a transmission control protocol (TCP) packet to be transmitted to another device, identifies a record header in the record, and determines, based on the record header, a record type associated with the decrypted record. Based on the record type, the network device marks the one or more TCP packets as including urgent data by setting a TCP urgent control bit in a header of the one or more TCP packets, and sets a second field, in the header of the TCP packet, to a second value that identifies an end of the urgent data, which corresponds to an end of the decrypted record data in the payload field.

Abstract: An apparatus is provided to manage memory utilization by a topic in a publish-subscribe environment, wherein the topic is a logical container for the messages. The apparatus includes a primary memory device configured to store messages published to a topic, and a secondary storage device. A processor operationally coupled to the primary and secondary memory devices is configured to monitor utilization of a portion of the primary memory device assigned to the topic. In response to detecting that the utilization of the portion of the primary memory device has equaled or exceeded a threshold for memory utilization, the processor performs at least one of throttling the rate of publishing to the topic and transferring a portion of the messages from the topic to the secondary memory device. Each of the throttling and the transferring keeps the portion of the primary memory device assigned to the topic from overloading.

Abstract: A workflow engine tool is disclosed that enables scientists and engineers to programmatically author workflows (e.g., a directed acyclic graph, “DAG”) with nearly no overhead, using a simpler script that needs almost no modifications for portability among multiple different workflow engines. This permits users to focus on the business logic of the project, avoiding the distracting tedious overhead related to workflow management (such as uploading modules, drawing edges, setting parameters, and other tasks). The workflow engine tool provides an abstraction layer on top of workflow engines, introducing a binding function that converts a programming language function (e.g., a normal python function) into a workflow module definition. The workflow engine tool infers module instances and induces edge dependencies automatically by inferring from a programming language script to build a DAG.

Abstract: Techniques for automatically scheduling builds of derived datasets in a distributed database system that supports pipelined data transformations are described herein.

Abstract: An address identification method, apparatus, system, storage medium, a processor and a terminal are disclosed. In an embodiment, the method includes: defining a screening library including at least one expected attribute value describing an expected state value of a device parameter to be addressed in an operating mode of an industrial device; acquiring a data group including an actual state value generated in the operating mode and an address where the actual state value is stored; for each address, extracting an actual attribute value, stored in the address, of the actual state value; comparing the actual attribute value with the expected attribute value, determining the actual state value corresponding to the actual attribute value which complies with the expected attribute value, and determining, from the data group, an address corresponding to the selected actual state value; and taking the selected address as a final address and outputting same.

Abstract: An encoded representation of a picture of a video stream is decoded by retrieving buffer description from the encoded representation. The buffer description information is used to determine at least one picture identifier identifying a respective reference picture as decoding reference for the picture. A decoded picture buffer is updated based on the determined picture identifier. The encoded representation of the picture itself comprises the information needed by a decoder to identify the reference pictures required to decode the encoded representation.

Abstract: Described herein are systems and techniques for determining when excessive I/O response times are not the fault of a storage port, but rather are caused by other factors or components on a storage network, for example, over-utilization of a host port. For one or more host ports and/or storage ports, a payload idle time (PIT) may be determined for each I/O operation, the PIT being the amount of time during which a storage port is waiting for a host port to be ready to send or receive data of the respective I/O operation. It may be determined whether one or more of the PITs includes an excessive idle time (EIT), where the EIT may be an amount of the PIT that is more than a predefined acceptable amount of time. The cause of the EIT may be determined.

Abstract: A receiver-directed congestion control system which provides receiver-directed apportioning by adding a bandwidth share indicator value to the acknowledgement messages sent by the receiver to the senders. In certain embodiments, bandwidth share indicator value comprises the number of senders seen by the receiver. In other embodiments, the bandwidth share indicator value may comprise a percentage bandwidth share allocated to the sender computer to allow for varying priorities between senders. In the acknowledgement message, each sender may also include the incast degree, which is programmed in the application, to the receiver. This strategy enables the receiver to send back the sender count to all the senders as soon the first sender's packets arrive, even before the rest of the senders' packets arrive. Thus, the sender count and the incast degree look-ahead enable the receiver-directed system to achieve accurate and faster convergence of sending rates, without any repeated adjustments.

Abstract: The techniques described herein limit client utilization of a parallel-access storage device. Specifically, client utilization of a particular storage device is estimated using I/O cost metrics to estimate the costs of I/O requests from the client to the particular storage device. The I/O cost metrics are determined based on calibration-based system performance data, which represents a system-wide measure of storage device performance for a system in which the particular storage device resides. The calibration-based system performance data includes one or both of composite throughput data and composite IOPS data for multiple parallel-access devices in the system. The cost estimates for I/O requests issued from a client to a parallel-access device are tracked in a total cost estimate for the client. Client utilization of the storage device, as tracked by the total cost estimate for the client, is limited to a percentage of the total estimated bandwidth of the storage device.

Abstract: By extending a Basic-CAN controller and/or a Full-CAN controller with a RX filter device, it is possible to compare the CAN identifiers intended for transmission for the CAN controller with those of the received CAN frames. In the case of a match, an interrupt is generated. When no hardware expansion is intended, the RX-FIFO or TX-FIFO of a Full-CAN controller is used for detecting an intrusion.

Abstract: A method, computer system, and a computer program product for managing asset placement with respect to a distributed computing environment having a set of hosts is provided. The present invention may include detecting a set of host computing resource requirement data for an asset, wherein the distributed computing environment includes a stream computing environment and the asset includes a rookie asset in the stream computing environment. The present invention may include identifying a set of computing resource profile data for a set of hosts in the distributed computing environment. The present invention may include determining, by comparing the set of host computing resource requirement data for the asset and the set of computing resource profile data for the set of hosts, an asset placement arrangement. The present invention may include establishing, based on the asset placement arrangement, the asset in the distributed computing environment.

Abstract: Techniques for accessing data, comprising receiving a first memory request associated with a first clock domain, converting a first memory address of the first memory request from a first memory address format associated with the first clock domain to a second memory address format associated with the second clock domain, transitioning the first memory request to a second clock domain, creating a first scoreboard entry associated with the first memory request, transmitting the first memory request to a memory based on the converted first memory address, receiving a first response to the first memory request, transitioning the first response to the second clock domain and clearing the first scoreboard entry based on the received response.

Abstract: Launch configurations of a hardware acceleration device are determined, which minimize hardware thread management overhead in running a program code. Based on received hardware behaviors, the architectural features, the thread resources and the constraints associated with the hardware acceleration device, possible launch configurations and impossible launch configurations are generated. A ranking of at least some of the possible launch configurations may be generated and output, based on how well each of said at least some of the possible launch configurations satisfies at least some of the constraints. Parametric values of said at least some of the possible launch configurations, an explanation why the impossible launch configurations have been determined as being impossible, and one or more strategies for scheduling, latencies and efficiencies associated with the hardware acceleration device, are output.

Abstract: A method of detecting cyber attacks on a cyber physical system is disclosed, and the system includes at least one computing device coupled to at least one sensor and/or actuator for controlling a physical process. The method comprises: deriving at least one invariant for the computing device, based on a system design of the system or computer code configured to control the system in relation to the physical process or data collected from the system during testing or operation of the system, the invariant defining a set of conditions that enable determination from the sensor and/or actuator regarding process anomalies of the physical process being controlled; configuring the invariant as corresponding computer code; and executing the invariant as the computer code on the computing device to monitor the physical process via the sensor and/or actuator and detect the process anomalies for detecting the cyber attacks.

Abstract: A non-volatile memory system accepts Secure Digital (SD) Commands and manages a data buffer that buffers data for the SD commands. The SD Commands may be accepted over an SD bus of the non-volatile memory system. The SD Commands may be accepted over a PCIe bus of the non-volatile memory system. The memory system may generate one or more NVMe commands for each SD command, and submit the NVMe command(s) to an NVMe submission queue. Upon completion all of the NVMe commands that were generated for an SD command, the memory system may report completion status of the SD command to an SD host. The memory system ensures that the timing requirements for SD commands are met even though a conversion from SD commands to NVMe commands may be performed. The memory system makes efficient use of the depth of the NVMe submission queue.

Abstract: A method for selecting content to send to labelers for prevalence estimation may include (1) selecting a prevalence estimator, (2) sampling content items from an online system, (3) using, for each of the content items, a model to generate a score for the content item that indicates a likelihood that the content item is of a class of content, (4) generating buckets that each (a) is assigned a range of scores from the model and (b) contains a subset of the content items whose scores fall within the range of scores, (5) determining a sampling rate for each of the buckets that minimizes a variance metric of the estimator, (6) selecting, from each of the buckets, a portion of content items according to the sampling rate of the bucket, and (7) sending the portions to labelers for labeling. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Techniques for dynamic throttling in batched bulk processing are described. In one embodiment, an apparatus may comprise an execution management component operative to retrieve a plurality of batch-operation instructions from a batch-operation instruction store; initiate performance of the plurality of batch-operation instructions, wherein performance of the plurality of batch-operation instructions modifies data stored on a data storage shard of a data storage system; and throttle performance of the plurality of batch-operation instructions where one or more data operation performance signals indicate that the data storage shard is overloaded; and a storage monitoring component operative to monitor the one or more data operation performance signals for the data storage shard. Other embodiments are described and claimed.

Abstract: A shared database platform can interface with a cluster computing platform over a network through a connector. The data transferred over the network can include metadata result packages that can be distributed to worker nodes of the duster computing platform, which receive the metadata objects and access the result data for further processing on a staging platform, such as a scalable storage platform.

Abstract: In order to be able to better and more flexibly utilize the available isochronous bandwidth of a realtime capable Ethernet network protocol, it is provided that a number (k) of transmission cycles (Z1, . . . , Zk) are combined to create a slow transmission cycle (ZL) and two network nodes (M, S1, . . . , Sn) communicate with one another in this slow transmission cycle (ZL) in that data communication of these two network nodes (M, S1, . . . , Sn) is provided in each kth transmission cycle (Z), and/or a transmission cycle (Z) is divided into a plurality (j) of rapid transmission cycles (ZS) and two network nodes (M, S1, . . . , Sn) communicate with one another in this rapid transmission cycle (ZS) in that data communication of these two network nodes (M, S1, . . . , Sn) is provided j times in each transmission cycle (ZS).

Abstract: A media stream receiver is provided for scalable physical layer flow of packetized media streams. The media stream receiver replicates the processing block in time, rather than in hardware, through the use of a single shared memory and pointer alignment calculations, which combines multiple buffering stages as the single, shared memory buffer to offer redundancy and alignment, while acting as a receiver buffer to account for packet delay variations. By doing so the media stream receiver can perform a vertical interval switch between received media streams.

Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation; a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform a second operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements.

Abstract: A method includes receiving, by a hardware controller of a storage device and from a host device, a command to read data from or write data to a non-volatile memory device of the storage device. The method includes, responsive to receiving the command: initializing, by firmware executing at a processor of the hardware controller, a command to retrieve data from or write data to the non-volatile memory device; determining, by circuit logic of the hardware controller, a time indicative of when the firmware initialized the command; determining, by the circuit logic, a time indicative of when the command terminated; and storing, by the circuit logic and at a latency monitoring cache of the storage device, a timestamp associated with the time indicative of when the command was initialized and a timestamp associated with the time indicative of when the command terminated.

Abstract: The present invention provides a method and apparatus for restricting batch requests for a service, facilitating restriction on requesting the service in batch and contributing to overcome some deficiencies in the prior art. The method comprises: receiving, by a server, service request information sent by a terminal (S11); sending, by the server, a calculation problem to the terminal, the question requiring a larger amount of computing recourses of the terminal than that of the server (S12); receiving, by the server, a calculation result of the calculation question from the terminal (S13), and verifying the calculation result (S14), and if the calculation result is correct, providing the service to the terminal (S15), otherwise, rejecting to provide the service to the terminal (S16).

Abstract: Techniques are described for eliminating backpressure in a distributed system by changing the rate data flows through a processing element. Backpressure occurs when data throughput in a processing element begins to decrease, for example, if new processing elements are added to the operating chart or if the distributed system is required to process more data. Indicators of backpressure (current or future) may be monitored. Once current backpressure or potential backpressure is identified, the operator graph or data rates may be altered to alleviate the backpressure. For example, a processing element may reduce the data rates it sends to processing elements that are downstream in the operator graph, or processing elements and/or data paths may be eliminated. In one embodiment, processing elements and associate data paths may be prioritized so that more important execution paths are maintained.

Abstract: Data flow node validation and provisioning techniques are described. In one or more implementations, a system is described that supports visual design and deployment of data flow pipelines to process streaming data flows. The system may be configured to include nodes and connections between the nodes to represent an arbitrary execution graph of data science algorithms (as algorithm action components) that are used to process the streaming data flows. The system may also support validation techniques to verify that the data flow pipeline may operate as intended. Further, the system may also support implementation and provisioning techniques that involve estimation and adjustment of runtime resource provisioning of a deployed data flow pipeline without preemption or starvation occurring for nodes within the pipeline.

Abstract: A computer-executable method, computer program product, and system for managing I/Os from a legacy compliant Application on a host, wherein the host is in communication with a data storage system including a burst buffer node, the computer-executable method comprising receiving a POSIX compliant message from the Application, wherein the message is associated with data on the data storage system and processing the POSIX message on the data storage system.

Abstract: First and second apparatuses are connected with each other through a communication path provided with a plurality of lanes used for data transfer that is performed between the first and second apparatuses. Prior to data transfer, transfer-control information is exchanged between the first and second apparatuses according to a predetermined communication protocol. Upon detecting transfer-control information, the first apparatus notifies the second apparatus of a lane-control instruction to increase a second lane-counter indicating a number of lanes used by the second apparatus, and increases a first lane-counter indicating a number of lanes used by the first apparatus so that the first lane-counter is greater than a number of lanes that have been used when detecting the transfer-control information.

Abstract: Systems and methods for limiting the rate of packet transmission from a NIC to a host CPU are provided. According to one embodiment, data packets are received from a network by the NIC. The NIC is coupled to a host central processing unit (CPU) of a network security device through a bus. A status of the host CPU is monitored by the NIC. A rate limiting mode indicator is set by the NIC based on the status. When the rate limiting mode indicator indicates rate limiting is inactive, then the received data packets are delivered or made available to the host CPU for processing. When the rate limiting mode indicator indicates rate limiting is active, then rate limiting is performing by temporarily stopping or slowing the delivery or making available of the received data packets to the host CPU for processing.

Abstract: A method begins by a dispersed storage (DS) processing module determining that partial task processing resources of a first DST execution unit are projected to be available. The method continues with the DS processing module ascertaining that partial task processing resources of a second DST execution unit are projected to be overburdened. The method continues with the DS processing module receiving, from the second DST execution unit, a partial task assigned to the second DST execution unit in accordance with a partial task allocation transfer policy to produce an allocated partial task and executing the allocated partial task.

Abstract: A data transmission method includes: determining a sum of first service proportions and a sum of second service proportions according to a first transmission rate of at least one first device, a second transmission rate of at least one second device, and a maximum bandwidth of a host transmission interface; determining at least one first service proportion of the first device according to the sum of the first service proportions, and determining at least one second service proportion of the second device according to the sum of the second service proportions; and transmitting at least one package of first transmission data of the first device and at least one package of second transmission data of the second device to a host via the host transmission interface according to the first service proportion and the second service proportion.

Abstract: Display systems that use contactless connectors for transmitting data are provided. The contactless connectors are electromagnetic connectors that form an electromagnetic communications link. The electromagnetic communications link can be established within different locations of the same device, or between two different devices. The communications link can be established using at least two transceivers. The transceivers can be incorporated in different enclosures that are hinged together, or the transceivers can be incorporated within a hinge that enables two enclosures to move with respect to each other. A transceiver can be incorporated into a display device that can receive data from an active surface that has a transceiver. When the display device is placed on the active surface, the display device may serve as an access point to content contained within the active surface.

Abstract: The present disclosure relates to methods and systems for implementing a high-speed serial bus with inhomogeneous lane bundles and encodings. A system for transmitting information can include a bus with a plurality of lanes and a host in communication with a target. The host can run an application that writes data to and reads data from storage. The host can assign a first plurality of lanes and a first encoding to a first bundle and assign a second plurality of lanes and a second encoding to a second bundle. The host can also evaluate a bandwidth requirement for the read and write instructions and evaluate a bus performance. The host can also regroup the first bundle or the second bundle based on bandwidth requirements and bus performance and can assign a third plurality of lanes and a third encoding to the at least one of the first bundle and the second bundle.

Abstract: A device may receive, via a first optical supervisory channel, a first timing signal from a first network node. The first timing signal may be generated by a first clock, of the first network node, and may be used to synchronize the first clock, of the first network node, and a second clock of a second network node. The device may determine a parameter value based on the first timing signal, and may determine whether the parameter value satisfies a threshold value. The device may selectively transmit, via a second optical supervisory channel, a second timing signal to the second network node based on determining whether the parameter value satisfies the threshold value. The second timing signal may be used to synchronize the second clock, of the second network node, with the first clock of the first network node.

Abstract: Systems, processors and methods are disclosed for organizing processing datapaths to perform operations in parallel while executing a single program. Each datapath executes the same sequence of instructions, using a novel instruction sequencing method. Each datapath is implemented through a processor having a data memory partitioned into identical regions. A master processor fetches instructions and conveys them to the datapath processors. All processors are connected serially by an instruction pipeline, such that instructions are executed in parallel datapaths, with execution in each datapath offset in time by one clock cycle from execution in adjacent datapaths. The system includes an interconnection network that enables full sharing of data in both horizontal and vertical dimensions, with the effect of coupling any datapath to the memory of any other datapath without adding processing cycles in common usage.

Abstract: An image processing apparatus having a storage device includes a switching unit configured to switch a bus width of a data bus of the storage device between at a time of activation of the image processing apparatus, and after the image processing apparatus is activated, and a shared terminal switching unit configured to switch a shared terminal shared between an I/O port and the data bus of the storage device, to an I/O side after the activation.

Abstract: A method of displaying information when an electronic apparatus is booted is provided. The method includes storing specific information, the specific information being monitored and collected from data created when the electronic apparatus operates, in an information file, and executing the information file storing the specific information during booting of the electronic apparatus and displaying the specific information.