Flow Controlling Patents (Class 710/29)
  • Patent number: 11132131
    Abstract: The techniques described herein limit client utilization of a parallel-access storage device. Specifically, client utilization of a particular storage device is estimated using I/O cost metrics to estimate the costs of I/O requests from the client to the particular storage device. The I/O cost metrics are determined based on calibration-based system performance data, which represents a system-wide measure of storage device performance for a system in which the particular storage device resides. The calibration-based system performance data includes one or both of composite throughput data and composite IOPS data for multiple parallel-access devices in the system. The cost estimates for I/O requests issued from a client to a parallel-access device are tracked in a total cost estimate for the client. Client utilization of the storage device, as tracked by the total cost estimate for the client, is limited to a percentage of the total estimated bandwidth of the storage device.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: September 28, 2021
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Kishy Kumar, Akshay Shah, Kothanda Umamageswaran
  • Patent number: 11128650
    Abstract: By extending a Basic-CAN controller and/or a Full-CAN controller with a RX filter device, it is possible to compare the CAN identifiers intended for transmission for the CAN controller with those of the received CAN frames. In the case of a match, an interrupt is generated. When no hardware expansion is intended, the RX-FIFO or TX-FIFO of a Full-CAN controller is used for detecting an intrusion.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: September 21, 2021
    Inventors: Oliver Hartkopp, André Oberschachtsiek
  • Patent number: 10992742
    Abstract: A method, computer system, and a computer program product for managing asset placement with respect to a distributed computing environment having a set of hosts is provided. The present invention may include detecting a set of host computing resource requirement data for an asset, wherein the distributed computing environment includes a stream computing environment and the asset includes a rookie asset in the stream computing environment. The present invention may include identifying a set of computing resource profile data for a set of hosts in the distributed computing environment. The present invention may include determining, by comparing the set of host computing resource requirement data for the asset and the set of computing resource profile data for the set of hosts, an asset placement arrangement. The present invention may include establishing, based on the asset placement arrangement, the asset in the distributed computing environment.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: April 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bradley W. Fawcett, Jason A. Nikolai
  • Patent number: 10990529
    Abstract: Techniques for accessing data, comprising receiving a first memory request associated with a first clock domain, converting a first memory address of the first memory request from a first memory address format associated with the first clock domain to a second memory address format associated with the second clock domain, transitioning the first memory request to a second clock domain, creating a first scoreboard entry associated with the first memory request, transmitting the first memory request to a memory based on the converted first memory address, receiving a first response to the first memory request, transitioning the first response to the second clock domain and clearing the first scoreboard entry based on the received response.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: April 27, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Daniel Wu, Kai Chirca, Matthew David Pierson
  • Patent number: 10936370
    Abstract: Launch configurations of a hardware acceleration device are determined, which minimize hardware thread management overhead in running a program code. Based on received hardware behaviors, the architectural features, the thread resources and the constraints associated with the hardware acceleration device, possible launch configurations and impossible launch configurations are generated. A ranking of at least some of the possible launch configurations may be generated and output, based on how well each of said at least some of the possible launch configurations satisfies at least some of the constraints. Parametric values of said at least some of the possible launch configurations, an explanation why the impossible launch configurations have been determined as being impossible, and one or more strategies for scheduling, latencies and efficiencies associated with the hardware acceleration device, are output.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventor: Fausto Artico
  • Patent number: 10911482
    Abstract: A method of detecting cyber attacks on a cyber physical system is disclosed, and the system includes at least one computing device coupled to at least one sensor and/or actuator for controlling a physical process. The method comprises: deriving at least one invariant for the computing device, based on a system design of the system or computer code configured to control the system in relation to the physical process or data collected from the system during testing or operation of the system, the invariant defining a set of conditions that enable determination from the sensor and/or actuator regarding process anomalies of the physical process being controlled; configuring the invariant as corresponding computer code; and executing the invariant as the computer code on the computing device to monitor the physical process via the sensor and/or actuator and detect the process anomalies for detecting the cyber attacks.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: February 2, 2021
    Inventors: Aditya Mathur, Sridhar Adepu
  • Patent number: 10846017
    Abstract: A non-volatile memory system accepts Secure Digital (SD) Commands and manages a data buffer that buffers data for the SD commands. The SD Commands may be accepted over an SD bus of the non-volatile memory system. The SD Commands may be accepted over a PCIe bus of the non-volatile memory system. The memory system may generate one or more NVMe commands for each SD command, and submit the NVMe command(s) to an NVMe submission queue. Upon completion all of the NVMe commands that were generated for an SD command, the memory system may report completion status of the SD command to an SD host. The memory system ensures that the timing requirements for SD commands are met even though a conversion from SD commands to NVMe commands may be performed. The memory system makes efficient use of the depth of the NVMe submission queue.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: November 24, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Dinesh Agarwal
  • Patent number: 10796245
    Abstract: A method for selecting content to send to labelers for prevalence estimation may include (1) selecting a prevalence estimator, (2) sampling content items from an online system, (3) using, for each of the content items, a model to generate a score for the content item that indicates a likelihood that the content item is of a class of content, (4) generating buckets that each (a) is assigned a range of scores from the model and (b) contains a subset of the content items whose scores fall within the range of scores, (5) determining a sampling rate for each of the buckets that minimizes a variance metric of the estimator, (6) selecting, from each of the buckets, a portion of content items according to the sampling rate of the bucket, and (7) sending the portions to labelers for labeling. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: October 6, 2020
    Assignee: Facebook, Inc.
    Inventors: Yevgeniy Grechka, David James Radburn-Smith
  • Patent number: 10747607
    Abstract: Techniques for dynamic throttling in batched bulk processing are described. In one embodiment, an apparatus may comprise an execution management component operative to retrieve a plurality of batch-operation instructions from a batch-operation instruction store; initiate performance of the plurality of batch-operation instructions, wherein performance of the plurality of batch-operation instructions modifies data stored on a data storage shard of a data storage system; and throttle performance of the plurality of batch-operation instructions where one or more data operation performance signals indicate that the data storage shard is overloaded; and a storage monitoring component operative to monitor the one or more data operation performance signals for the data storage shard. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 18, 2020
    Assignee: FACEBOOK, INC.
    Inventors: Gyujin Hwang, Jonathan Edward Sailor, Hugo Leonardo Wolff de Souza, Carson Tang
  • Patent number: 10719517
    Abstract: A shared database platform can interface with a cluster computing platform over a network through a connector. The data transferred over the network can include metadata result packages that can be distributed to worker nodes of the duster computing platform, which receive the metadata objects and access the result data for further processing on a staging platform, such as a scalable storage platform.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 21, 2020
    Assignee: Snowflake Inc.
    Inventors: Bing Li, Edward Ma, Mingli Rui, Haowei Yu, Andong Zhan
  • Patent number: 10630604
    Abstract: In order to be able to better and more flexibly utilize the available isochronous bandwidth of a realtime capable Ethernet network protocol, it is provided that a number (k) of transmission cycles (Z1, . . . , Zk) are combined to create a slow transmission cycle (ZL) and two network nodes (M, S1, . . . , Sn) communicate with one another in this slow transmission cycle (ZL) in that data communication of these two network nodes (M, S1, . . . , Sn) is provided in each kth transmission cycle (Z), and/or a transmission cycle (Z) is divided into a plurality (j) of rapid transmission cycles (ZS) and two network nodes (M, S1, . . . , Sn) communicate with one another in this rapid transmission cycle (ZS) in that data communication of these two network nodes (M, S1, . . . , Sn) is provided j times in each transmission cycle (ZS).
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 21, 2020
    Assignee: B&R INDUSTRIAL AUTOMATION GMBH
    Inventor: Dietmar Bruckner
  • Patent number: 10416999
    Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation; a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform a second operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Kermin Fleming, Kent D. Glossop, Simon C. Steely, Jr.
  • Patent number: 10419808
    Abstract: A media stream receiver is provided for scalable physical layer flow of packetized media streams. The media stream receiver replicates the processing block in time, rather than in hardware, through the use of a single shared memory and pointer alignment calculations, which combines multiple buffering stages as the single, shared memory buffer to offer redundancy and alignment, while acting as a receiver buffer to account for packet delay variations. By doing so the media stream receiver can perform a vertical interval switch between received media streams.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: September 17, 2019
    Assignee: GVBB HOLDINGS S.A.R.L.
    Inventors: Stephane Martel, Charles S. Meyer
  • Patent number: 10379747
    Abstract: A method includes receiving, by a hardware controller of a storage device and from a host device, a command to read data from or write data to a non-volatile memory device of the storage device. The method includes, responsive to receiving the command: initializing, by firmware executing at a processor of the hardware controller, a command to retrieve data from or write data to the non-volatile memory device; determining, by circuit logic of the hardware controller, a time indicative of when the firmware initialized the command; determining, by the circuit logic, a time indicative of when the command terminated; and storing, by the circuit logic and at a latency monitoring cache of the storage device, a timestamp associated with the time indicative of when the command was initialized and a timestamp associated with the time indicative of when the command terminated.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 13, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Mark David Erickson, Adam Christopher Geml, Darin Edward Gerhart, Nicholas Edward Ortmeier
  • Patent number: 10366223
    Abstract: The present invention provides a method and apparatus for restricting batch requests for a service, facilitating restriction on requesting the service in batch and contributing to overcome some deficiencies in the prior art. The method comprises: receiving, by a server, service request information sent by a terminal (S11); sending, by the server, a calculation problem to the terminal, the question requiring a larger amount of computing recourses of the terminal than that of the server (S12); receiving, by the server, a calculation result of the calculation question from the terminal (S13), and verifying the calculation result (S14), and if the calculation result is correct, providing the service to the terminal (S15), otherwise, rejecting to provide the service to the terminal (S16).
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: July 30, 2019
    Assignees: BEIJING JINGDONG SHANGKE INFORMATION TECHNOLOGY CO., LTD., BEIJING JINGDONG CENTURY TRADING CO., LTD.
    Inventor: Weiqi Li
  • Patent number: 10324756
    Abstract: Techniques are described for eliminating backpressure in a distributed system by changing the rate data flows through a processing element. Backpressure occurs when data throughput in a processing element begins to decrease, for example, if new processing elements are added to the operating chart or if the distributed system is required to process more data. Indicators of backpressure (current or future) may be monitored. Once current backpressure or potential backpressure is identified, the operator graph or data rates may be altered to alleviate the backpressure. For example, a processing element may reduce the data rates it sends to processing elements that are downstream in the operator graph, or processing elements and/or data paths may be eliminated. In one embodiment, processing elements and associate data paths may be prioritized so that more important execution paths are maintained.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Branson, Ryan K. Cradick, John M. Santosuosso
  • Patent number: 10313248
    Abstract: Data flow node validation and provisioning techniques are described. In one or more implementations, a system is described that supports visual design and deployment of data flow pipelines to process streaming data flows. The system may be configured to include nodes and connections between the nodes to represent an arbitrary execution graph of data science algorithms (as algorithm action components) that are used to process the streaming data flows. The system may also support validation techniques to verify that the data flow pipeline may operate as intended. Further, the system may also support implementation and provisioning techniques that involve estimation and adjustment of runtime resource provisioning of a deployed data flow pipeline without preemption or starvation occurring for nodes within the pipeline.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: June 4, 2019
    Assignee: Adobe Inc.
    Inventor: David M. Tompkins
  • Patent number: 10261723
    Abstract: A computer-executable method, computer program product, and system for managing I/Os from a legacy compliant Application on a host, wherein the host is in communication with a data storage system including a burst buffer node, the computer-executable method comprising receiving a POSIX compliant message from the Application, wherein the message is associated with data on the data storage system and processing the POSIX message on the data storage system.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: April 16, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Sorin Faibish, Dominique P. Cote, Dennis Pei Jean Ting, John M. Bent, James M. Pedone, Jr.
  • Patent number: 10223323
    Abstract: First and second apparatuses are connected with each other through a communication path provided with a plurality of lanes used for data transfer that is performed between the first and second apparatuses. Prior to data transfer, transfer-control information is exchanged between the first and second apparatuses according to a predetermined communication protocol. Upon detecting transfer-control information, the first apparatus notifies the second apparatus of a lane-control instruction to increase a second lane-counter indicating a number of lanes used by the second apparatus, and increases a first lane-counter indicating a number of lanes used by the first apparatus so that the first lane-counter is greater than a number of lanes that have been used when detecting the transfer-control information.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: March 5, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Atsuyuki Nikami, Toshiyuki Shimizu, Tomohiro Inoue
  • Patent number: 10212129
    Abstract: Systems and methods for limiting the rate of packet transmission from a NIC to a host CPU are provided. According to one embodiment, data packets are received from a network by the NIC. The NIC is coupled to a host central processing unit (CPU) of a network security device through a bus. A status of the host CPU is monitored by the NIC. A rate limiting mode indicator is set by the NIC based on the status. When the rate limiting mode indicator indicates rate limiting is inactive, then the received data packets are delivered or made available to the host CPU for processing. When the rate limiting mode indicator indicates rate limiting is active, then rate limiting is performing by temporarily stopping or slowing the delivery or making available of the received data packets to the host CPU for processing.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: February 19, 2019
    Assignee: Fortinet, Inc.
    Inventors: Zhiwei Dai, Xu Zhou
  • Patent number: 10140177
    Abstract: A method begins by a dispersed storage (DS) processing module determining that partial task processing resources of a first DST execution unit are projected to be available. The method continues with the DS processing module ascertaining that partial task processing resources of a second DST execution unit are projected to be overburdened. The method continues with the DS processing module receiving, from the second DST execution unit, a partial task assigned to the second DST execution unit in accordance with a partial task allocation transfer policy to produce an allocated partial task and executing the allocated partial task.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 10108571
    Abstract: A data transmission method includes: determining a sum of first service proportions and a sum of second service proportions according to a first transmission rate of at least one first device, a second transmission rate of at least one second device, and a maximum bandwidth of a host transmission interface; determining at least one first service proportion of the first device according to the sum of the first service proportions, and determining at least one second service proportion of the second device according to the sum of the second service proportions; and transmitting at least one package of first transmission data of the first device and at least one package of second transmission data of the second device to a host via the host transmission interface according to the first service proportion and the second service proportion.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: October 23, 2018
    Assignee: ASMEDIA TECHNOLOGY INC.
    Inventors: Hsin-Chih Huang, Wei-Yun Chang
  • Patent number: 10082995
    Abstract: Display systems that use contactless connectors for transmitting data are provided. The contactless connectors are electromagnetic connectors that form an electromagnetic communications link. The electromagnetic communications link can be established within different locations of the same device, or between two different devices. The communications link can be established using at least two transceivers. The transceivers can be incorporated in different enclosures that are hinged together, or the transceivers can be incorporated within a hinge that enables two enclosures to move with respect to each other. A transceiver can be incorporated into a display device that can receive data from an active surface that has a transceiver. When the display device is placed on the active surface, the display device may serve as an access point to content contained within the active surface.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: September 25, 2018
    Assignee: KEYSSA, INC.
    Inventors: Gary D. McCormack, Roger D. Isaac
  • Patent number: 10049076
    Abstract: The present disclosure relates to methods and systems for implementing a high-speed serial bus with inhomogeneous lane bundles and encodings. A system for transmitting information can include a bus with a plurality of lanes and a host in communication with a target. The host can run an application that writes data to and reads data from storage. The host can assign a first plurality of lanes and a first encoding to a first bundle and assign a second plurality of lanes and a second encoding to a second bundle. The host can also evaluate a bandwidth requirement for the read and write instructions and evaluate a bus performance. The host can also regroup the first bundle or the second bundle based on bandwidth requirements and bus performance and can assign a third plurality of lanes and a third encoding to the at least one of the first bundle and the second bundle.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: August 14, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dejan Vucinic, Zvonimir Z. Bandic
  • Patent number: 10014937
    Abstract: A device may receive, via a first optical supervisory channel, a first timing signal from a first network node. The first timing signal may be generated by a first clock, of the first network node, and may be used to synchronize the first clock, of the first network node, and a second clock of a second network node. The device may determine a parameter value based on the first timing signal, and may determine whether the parameter value satisfies a threshold value. The device may selectively transmit, via a second optical supervisory channel, a second timing signal to the second network node based on determining whether the parameter value satisfies the threshold value. The second timing signal may be used to synchronize the second clock, of the second network node, with the first clock of the first network node.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: July 3, 2018
    Assignee: Juniper Networks, Inc.
    Inventors: Domenico Di Mola, Gert Grammel
  • Patent number: 10013733
    Abstract: Systems, processors and methods are disclosed for organizing processing datapaths to perform operations in parallel while executing a single program. Each datapath executes the same sequence of instructions, using a novel instruction sequencing method. Each datapath is implemented through a processor having a data memory partitioned into identical regions. A master processor fetches instructions and conveys them to the datapath processors. All processors are connected serially by an instruction pipeline, such that instructions are executed in parallel datapaths, with execution in each datapath offset in time by one clock cycle from execution in adjacent datapaths. The system includes an interconnection network that enables full sharing of data in both horizontal and vertical dimensions, with the effect of coupling any datapath to the memory of any other datapath without adding processing cycles in common usage.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: July 3, 2018
    Assignee: Mireplica Technology, LLC
    Inventor: William M. Johnson
  • Patent number: 9940560
    Abstract: An image processing apparatus having a storage device includes a switching unit configured to switch a bus width of a data bus of the storage device between at a time of activation of the image processing apparatus, and after the image processing apparatus is activated, and a shared terminal switching unit configured to switch a shared terminal shared between an I/O port and the data bus of the storage device, to an I/O side after the activation.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: April 10, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Kazuhiro Oyoshi
  • Patent number: 9928078
    Abstract: A method of displaying information when an electronic apparatus is booted is provided. The method includes storing specific information, the specific information being monitored and collected from data created when the electronic apparatus operates, in an information file, and executing the information file storing the specific information during booting of the electronic apparatus and displaying the specific information.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: March 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-su Jung, Young-ah Seong, Say Jang
  • Patent number: 9904653
    Abstract: The disclosure provides a PCI Express Scaled Port, a computing device and a method of communicating between PCI Express components. In one embodiment, the PCI Express Scaled Port includes: (1) an interface configured to communicate flow control negotiating packets with another PCI Express Port and (2) a FCC Controller configured to generate the flow control negotiating packets, wherein the flow control negotiating packets include a flow control credit for PCI Express packets and a scaling factor for the flow control credit.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: February 27, 2018
    Assignee: Nvidia Corporation
    Inventors: Steve Glaser, Chris Runhaar
  • Patent number: 9904490
    Abstract: A mass storage device and method for storing data originally written to a volatile memory with byte level I/O protocol commands to a non-volatile memory using block level I/O protocol commands. The mass storage device includes a host interface for communicating with the host computer system, at least one non-volatile memory, at least one volatile memory, a memory controller configured to accept block level I/O protocol commands from the host computer system to read data from and write data to the non-volatile memory, and additionally accept byte level memory I/O commands from the host computer system for reading data from and writing data to the at least one volatile memory, and means for retrieving the data written by the host computer system using the byte level memory I/O commands from the volatile memory and writing the data retrieved from the volatile memory to the at least one non-volatile memory.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: February 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Nigel David Horspool, Jeremy Omar Moore, Julien Margetts
  • Patent number: 9900272
    Abstract: A method and server for transmitting application test data are provided, the method including: obtaining data to be transmitted by an application; dividing the data into a plurality of data sections, wherein each data section is less than a maximum transmission capacity that the application can transmit one time; and controlling the application to transmit the plurality of data sections sequentially, wherein upon the completion of the transmission of a data section, the application is reinitiated to automatically transmit a next data section. The method and server for transmitting application test data saves testing costs and enhances operational efficiency.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: February 20, 2018
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventor: Jian Zhu
  • Patent number: 9843436
    Abstract: A port is provided to facilitate a link between a first device and a second device. The port can include a driver circuit to support half duplex communication between the first device and the second device and further include switching logic to receive a value and cause the driver circuit to function in one of a plurality of half duplex modes based on the value. The value is based on a configuration register value corresponding to the port.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: December 12, 2017
    Assignee: Intel Corporation
    Inventors: Chia How Low, Su Sin Florence Phun
  • Patent number: 9798620
    Abstract: Techniques are disclosed relating to writing data across multiple storage blocks in a storage device. In one embodiment, physical erase blocks in a bank of a storage device are erasable. Ones of the physical erase blocks may be associated with different respective communication channels. In such an embodiment, a data stripe may be written across a set of physical erase blocks such that the set of physical erase blocks includes physical erase blocks of different banks and includes physical erase blocks associated with different communication channels. In some embodiments, a request to read a portion of the data stripe may be received. In response to the request, a determination may be made that one of the set of physical erase blocks is unavailable to service the request. The request may then be serviced by reassembling data of the unavailable physical erase block.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: October 24, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Robert Wood, Jeremy Fillingim, Pankaj Mehra
  • Patent number: 9729459
    Abstract: A system and method for credit-based link level flow control. In one embodiment, a byte-based flow control mechanism is based on a sender effectively maintaining a buffer state at the receiver. In maintaining a buffer state at the receiver, the sender is provided with information regarding byte expansion at the receiver. This byte-expansion information can be used by the sender to identify the amount of additional storage needed by the receiver when storing a packet transmitted by the sender in the receiver's packet buffer.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: August 8, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Ariel Hendel, K. R. Kishore
  • Patent number: 9674249
    Abstract: Software for a distributed streaming platform receives a specification for a streaming application and converts the specification into a logical plan that includes a directed acyclic graph (DAG) with operators as nodes and streams as edges. The software translates the logical plan into a physical plan using any stream modes as specified and with one or more instances of the operators per any static partitioning. Then the software obtains a plurality of containers running on a networked cluster of servers. One slave executes in each container. The software assigns the instances to the slaves for execution according to an execution plan that depends at least in part on the physical plan and number of containers obtained. Each slave monitors throughput of the streaming windows through the instances in the container and other statistics related to service level and reports the results of the monitoring, which are used for dynamic adjustment.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: June 6, 2017
    Assignee: DataTorrent, Inc.
    Inventors: Amol J. Kekre, Phu D. Hoang, Chetan Narsude, Thomas Weise
  • Patent number: 9639272
    Abstract: A sequence of storage devices of a data store may include one or more stripesets for storing data stripes of different lengths and of different types. Each data stripe may be stored in a prefix or other portion of a stripeset. Each data stripe may be identified by an array of addresses that identify each page of the data stripe on each included storage device. When a first storage device of a stripeset becomes full, the stripeset may be shifted by removing the full storage device from the stripeset, and adding a next storage device of the data store to the stripeset. A class variable may be associated with storage devices of a stripeset to identify the type of data that the stripeset can store. The class variable may be increased (or otherwise modified) when a computer stores data of a different class in the stripeset.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: May 2, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Colin Reid, Philip A. Bernstein
  • Patent number: 9631286
    Abstract: The present invention relates to a reversible electrochemical cell, such as an electrolysis cell for water splitting or for conversion of carbon dioxide and water into fuel. The present invention relates also to an electrochemical cell that when operated in reverse performs as a fuel cell. The electrochemical cell comprises gas5 diffusion electrodes and a porous layer made of materials and having a structure adapted to allow for a temperature range of operation between 100-374° C. and in a pressure range between 3-200 bars.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: April 25, 2017
    Assignee: Danmarks Tekniske Universitet
    Inventors: Frank Allebrod, Christodoulos Chatzichristodoulou, Pia Lolk Mollerup, Mogens Bjerg Mogensen
  • Patent number: 9621143
    Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: April 11, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael J. Osborn, Michael J. Tresidder, Aaron J. Grenat, Joseph Kidd, Priyank Parakh, Steven J. Kommrusch
  • Patent number: 9563486
    Abstract: Software for a distributed streaming platform receives an application that runs on a streaming platform. The application is structured as a directed acyclic graph (DAG) with instances of operators as nodes and streams as edges between nodes. The application is associated with a pre-defined hint that is a key-value pair. The software launches the application by assigning the instances of operators to containers provided by the streaming platform and initiating the streams. Then the software reads a value for the pre-defined hint and transmits the value to the application through an application programming interface (API) exposed by the streaming platform. The software receives a request from the application through the API to make a dynamic adjustment. And the software makes the dynamic adjustment and re-launches the application using a recovery policy.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: February 7, 2017
    Assignee: DataTorrent, Inc.
    Inventors: Chetan Narsude, Thomas Weise, Pramod Immaneni, David Yan, Amol Kekre
  • Patent number: 9558139
    Abstract: A communications technique using spare bit-lanes to communicate changes in interface physical link layer bandwidth and/or active width provides for dynamic adjustment of power consumption of interface links without requiring a separate control path for exchanging the change information. One or more spare bit-lanes are used to communicate an indication of the operating frequency/active width change to the physical link layer of the remote side of the interface and an acknowledgement is sent back to provide complete handshaking of the operating characteristic change. The method can determine whether or not a spare bit-lane is available and prevent making the change if a spare bit-lane is not available until the interface is repaired and a spare bit-lane can then be used for communicating operating changes in operating frequency/active width.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: January 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel Mark Dreps, Frank D. Ferraiolo, Anand Haridass, Prasanna Jayaraman
  • Patent number: 9552319
    Abstract: A communications technique using spare bit-lanes to communicate changes in interface physical link layer bandwidth and/or active width provides for dynamic adjustment of power consumption of interface links without requiring a separate control path for exchanging the change information. One or more spare bit-lanes are used to communicate an indication of the operating frequency/active width change to the physical link layer of the remote side of the interface and an acknowledgement is sent back to provide complete handshaking of the operating characteristic change. The method can determine whether or not a spare bit-lane is available and prevent making the change if a spare bit-lane is not available until the interface is repaired and a spare bit-lane can then be used for communicating operating changes in operating frequency/active width.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel Mark Dreps, Frank D. Ferraiolo, Anand Haridass, Prasanna Jayaraman
  • Patent number: 9538956
    Abstract: A medical apparatus (300, 400, 500, 600) comprising a magnetic resonance imaging system (302). The medical apparatus further comprises a heating system (320, 502, 601) operable for heating a target zone (321) and a processor (326). Execution of machine readable instructions causes the processor to receive (100, 200, 700, 800) a treatment plan (340). Execution of the instructions further cause the processor to repeatedly: control (102, 204, 704, 804, 900, 1002) the heating system, using the treatment plan, to heat the target zone during alternating heating periods and cooling periods; acquire (104, 208, 702, 706, 802, 806, 902, 906, 1000, 1004) magnetic resonance data using the magnetic resonance imaging system, and modify (110, 214, 712, 812, 1008) the treatment plan using the magnetic resonance data. The instructions cause the processor to acquire the magnetic resonance data during a cooling period selected from at least one of the cooling periods.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: January 10, 2017
    Assignee: Koninklijke Philips N.V.
    Inventors: Max Oskar Köhler, Erkki Tapani Vahala, Jukka Ilmari Tanttu, Jaakko Juhani Tölö
  • Patent number: 9519586
    Abstract: Efficient techniques are described for reducing cache pollution by use of a prefetch logic that recognizes exits from software loops or function returns to cancel any pending prefetch request operations. The prefetch logic includes a loop data address monitor to determine a data access stride based on repeated execution of a memory access instruction in a program loop. Data prefetch logic then speculatively issues prefetch requests according to the data access stride. A stop prefetch circuit is used to cancel pending prefetch requests in response to an identified loop exit. The prefetch logic may also recognize a return from a called function and cancel any pending prefetch request operations associated with the called function. When prefetch requests are canceled, demand requests, such as based on load instructions, are not canceled. This approach to reduce cache pollution uses program flow information to throttle data cache prefetching.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: December 13, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Matthew M. Gilbert
  • Patent number: 9430434
    Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a DRAM memory system and a system on chip (SoC). The SoC is coupled to the DRAM memory system via a memory bus. The SoC comprises one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system. The one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a bus width of the memory bus.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: August 30, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Haw-Jing Lo, Dexter Chun
  • Patent number: 9420498
    Abstract: A method and apparatus are described for supporting dynamic and distributed mobility management (DMM). A wireless transmit/receive unit (WTRU) may attach to a first distributed gateway (D-GW), and configure a first Internet protocol (IP) address based on a prefix locally provided by the first D-GW. The WTRU may move and attach to a second D-GW while carrying out an on-going communication session with a correspondent node (CN). The WTRU may configure a second IP address based on a prefix provided by the second D-GW. The WTRU may use the first IP address for carrying out the on-going session and use the second IP address for a new communication session.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: August 16, 2016
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Juan Carlos Zuniga, Carlos Jesus Bernardos, Alexander Reznik
  • Patent number: 9354922
    Abstract: Systems, methods and computer program products configured to provide and perform metadata-based workflow management are disclosed. The inventive subject matter includes a computer readable storage medium having computer readable program instructions embodied therewith. The computer readable program instructions are configured to: initiate a workflow configured to process data; associate the data with metadata; and drive at least a portion of the workflow based on at least some of the metadata. The metadata include anchoring metadata; common metadata; and custom metadata. Inventive subject matter also encompasses a method for managing genomic data processing workflows using metadata includes: initiating a workflow; receiving a request to manage the workflow using metadata comprising: anchoring metadata, common metadata, and custom metadata, associating the metadata with the data; and driving at least a portion of the workflow based on the metadata. The workflow involves genomic analyzes.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: May 31, 2016
    Assignee: International Business Machines Corporation
    Inventor: Frank N. Lee
  • Patent number: 9307057
    Abstract: Methods and systems are provided for operating a SIMD packet parsing cluster, wherein the cluster includes a plurality of M packet parsing engines 1 to M, and the cluster further includes a shared memory and an instruction memory storing a plurality of instructions to be performed by each of the engines, and wherein the instructions include one or more memory accessing instructions that require accessing the shared memory. The method comprises transmitting the instructions to the engines for instructions to be executed by the engines; for each of the engines 2 to M, delaying execution of each of the memory accessing instructions by a delay time compared to a previous engine; and each one of the engines performing one of the memory accessing instructions at a time that the other engines are not performing one of the memory accessing instructions.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: April 5, 2016
    Assignee: Cavium, Inc.
    Inventors: Wilson Parkhurst Snyder, II, Daniel Adam Katz
  • Patent number: 9246748
    Abstract: An optical channel data unit (ODU) switch includes a set of two or more client cards, a set of two or more line cards, and a set of two or more switch cards. Each switch card is connected to all client cards, all line cards, and all other switch cards, and each client card, line card and switch card includes control logic for managing an operation of the ODU switch in a distributed manner.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: January 26, 2016
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Chunjie Duan, Ghulam Bhatti, Kieran Parsons, Kazuumi Koguchi, Soichiro Kametani
  • Patent number: 9240951
    Abstract: Some demonstrative embodiments include apparatuses, systems and/or methods of controlling data flow over a communication network. For example, an apparatus may include a communication unit to control the transfer of a stream of data from a first device to a second device over a communication link, the stream of data including data to be delivered to a plurality of endpoints. For example, the controlling may include communicating between the first and second devices at least one message including at least one endpoint-specific credit consumption unit (CCU) defined with respect to at least one endpoint of the plurality of endpoints.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 19, 2016
    Assignee: INTEL CORPORATION
    Inventors: Bahareh Sadeghi, Elad Levy, Rafal Wielicki, Marek Dabek, Oren Kedem
  • Patent number: 9219934
    Abstract: A method of controlling data transfer in a data transmission system which includes a plurality of video and/or audio data sources, a single transmitter operable to transmit data from the data sources over at least one transmission channel, a plurality of client receivers operable to receive transmitted data, the method comprising estimating available channel capacity for each client receiver, using parameters relating to the at least one transmission channel, and using information from the transmitter and receiver, and using information relating to queuing of data between the data sources and the transmitter; determining a target bit transmit rate for each client receiver in dependence upon the estimated channel capacity, a quality parameter, and an activity parameter for the client receiver concerned; and controlling the data sources and transmitter in dependence upon the determined bit transmit rate.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: December 22, 2015
    Assignee: Global Invacom Limited
    Inventors: David Bull, James Chung How, Andrew Nix, Jon Pledge