Abstract: A data stream flow-controller controls a transfer of data between a data processing device and an interconnection network. The flow controller includes interfaces for interfacing the controller on the network side and on the processing device side, a configurable storage for buffering queues of data in the controller before transfer to destination, and a programmable controller to control the storage to define queue parameters.

Abstract: Source circuits (10) produce messages that may each be processed by any one of a plurality of processing circuits (14). A network of distributor circuits is provided between the source circuits and the processing circuits (14). Local decisions by the distributor circuits in the network decide for each message to which one of the processing circuits the message will be routed. Messages are supplied to at least two parallel distributor circuits. These distributor circuits (12a) select from further distributor circuits (12b) in the network on the basis of current availability of individual ones of the further distributor circuits (12b). The respective messages are in turn forwarded from the selected further distributor circuits (12b) to data processing circuits (14) along routes selected by the selected further distributor circuits (12b) on the basis of current availability of the data processing circuits (14) and/or subsequent distributor circuits (12c) in the network.

Abstract: Disclosed are a method and a computer program storage product for dynamically stabilizing a stream processing system. The method includes receiving at least one computing resource allocation target. A plurality of downstream processing elements and an upstream processing element are associated with at least one input buffer. Each of the downstream processing elements consumes data packets produced by the upstream processing element received on an output stream associated with the upstream processing element. A fastest input rate among each downstream processing element in the plurality of downstream processing elements is identified. An output rate of the upstream processing element is set to the fastest input rate that has been determined for the plurality of downstream processing elements.

Abstract: A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.

Abstract: The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side.

Abstract: An apparatus, a computer program product and a computer-implemented method performed by a computerized device, comprising: receiving a description of a workflow, the workflow comprising a plurality of blocks, wherein each block comprises one or more instructions, the plurality of blocks comprising at least a first block and a second block, wherein the first block is adapted to output information, and the second block is adapted to receive the information wherein at least one of the plurality of blocks is associated with a ratio between a number of records input into the block and a number of records output by the block; and validating that the workflow can operate properly, using the ratio, wherein during execution, each of the first block and the second block can keep an internal state and request to receive again data previously received as input.

Abstract: A device controller, a peripheral device, and a power control method that enable buffers to be used efficiently and that enable power control to be performed on the basis of data amounts accumulated in the buffers are provided. A novel device controller includes an input buffer for accumulating data output from a host device, an output buffer for accumulating data output to the host device, a data communication section for transferring data between the input and output buffers and the host device, and a data buffer control section for modifying buffer allocation amounts to the input and output buffers on the basis of the data amount accumulated in at least one of the input and output buffers. The data buffer control section causes the data communication section to transition from a normal power consumption mode to a low power consumption mode when the data amount reaches a predetermined value.

Abstract: In one embodiment, the present invention includes a method for determining whether a packet received in an input/output (I/O) circuit of a node is destined for the node and if so, providing the packet to an egress queue of the I/O circuit and determining whether one or more packets are present in an ingress queue of the I/O circuit and if so, providing a selected packet to a first or second output register according to a global schedule that is independent of traffic flow. Other embodiments are described and claimed.

Abstract: The method includes the following steps: monitoring an actual value of a relevant parameter of a display bandwidth of data to be output by the memory; comparing the actual value of the relevant parameter with a threshold to determine whether the actual display bandwidth meets predetermined requirements; and selecting an access arbitration mode for the memory according to whether the predetermined requirements are met. The access controller includes: a monitoring and comparing unit, adapted to monitor an actual value of a relevant parameter of a display bandwidth of data to be output by the memory and compare the actual value of the relevant parameter with a threshold to determine whether the actual display bandwidth meets predetermined requirements; and an arbitration adjusting unit, adapted to select an access arbitration mode for the memory according to whether the predetermined requirements are met.

Abstract: One embodiment provides a system that processes an input/output (I/O) operation associated with a portable storage device. During operation, the system loads a virtual computing environment stored on the portable storage device into a host computer system coupled to the portable storage device. Next, the system intercepts the I/O operation from the virtual computing environment to the portable storage device. Finally, the system decouples the I/O operation from the virtual computing environment by processing the I/O operation independently of a representation of the I/O operation in the virtual computing environment.

Abstract: A physical coding sublayer includes a first channel configured to receive a first encoded data stream from a physical media attachment layer and to provide a first decoded data stream to a media access layer. The first channel includes a first circuit configured to detect synchronization headers in the first encoded data stream received from the physical media attachment layer, a decoding circuit configured to decode the encoded data stream and to adjust a width of the received data from a first width to a second width based on a signal identifying the synchronization headers received from the first circuit, and a first single configured to compensate for clock differences between the physical media attachment layer and the media access layer to which the first buffer provides the first decoded data stream.

Abstract: The present invention concerns a control device (1) provided for smart card readers (SCR), a smart card reading activation device (2) and associated products including a set-top box and a daisy chain. The control device comprises means for communicating (11) with at least two smart card reading devices (SCR3, SCR4, SCR5), means for processing (12) information received from those reading devices and means for activating (13) at least one of those reading devices for a current communication. The activating means are intended to send selection data (SD) towards all those reading devices, those selection data enabling each of the reading devices to determine if it is selected or not for the current communication.

Abstract: A data processing system 100 comprising a monitor 120 is provided and corresponding system-on-chip, method for monitoring and computer program product. The data processing system comprises multiple processing devices 104, 106, 116, 116 and a monitor 120. The monitor is configured to monitor characteristics of the data streams 102, 112, occurring among the plurality of data processing devices. The monitor comprises a means to determine whether a system characteristic substantially deviates from an expected system characteristic and to raise an anomaly signal if so. The system characteristic depends on the first characteristic and the second characteristic. In this way the monitor increases robustness by monitoring for problems related to deviations in the relation between multiple data streams.

Abstract: A data writing apparatus includes a tape drive, a buffer and non-volatile memory. When a synchronization request is received from a device sending data to be written to a tape, the apparatus is operable to copy data corresponding to the synchronization request from the buffer to the non-volatile memory. The data may be stored in the non-volatile memory until at least the time when the data which it is a copy of is written to the tape from the buffer.

Abstract: A method and structure for detecting whether the packets received by the switch are low latency packets or high bandwidth packets and routing detected low latency packets to a first one of a pair of switching structures and for high bandwidth packets to a second one of the pair of switching structures. The switch includes an output section for detecting whether a low latency packet is being received during transmission of a high bandwidth packet and, under such detected condition interrupting the transmission of the high bandwidth packet, transmitting the low latency packet, and then transmitting a remaining portion of the high bandwidth packet. The switch inserts delimiters at the start of transmission of the low latency packet and an end of transmission of the low latency packet. The transmission of the low latency packet commences immediately upon detection of such low latency packet.

Abstract: A stream data control server includes: a processable flow rate managing unit which manages a processable flow rate corresponding to an amount of data per unit time, which can be processed in each of storage units serving as storing destinations; a classified data flow rate managing unit which manages a data flow rate corresponding to an amount of data processed per unit time for each class of data to which a data priority is attached; and a storing destination control unit which controls the storing destinations of respective data based upon the processable flow rate of each of the storage units and the data flow rate for each class in such a manner that the data having higher data priorities are stored in the storage units having higher priorities within a range of the processable flow rate of each of the storage units.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: A circuit arrangement and method facilitate the direct streaming of data between producer and consumer circuits (12P, 12C) that are otherwise configured to communicate over an address-based network (18). Sync signals (46, 56) are generated for each of producer and consumer circuits (12P, 12C) from the address information encoded into requests that communicate the data streams output by the producer circuit (12P) and expected by the consumer circuit (12C). The sync signals (46, 56) for the producer and consumer circuits (12C) are then used to selectively modify the data stream output by the producer circuit (12P) to a format expected by the consumer circuit (12C). Typically, such modification takes the form of inserting data into the data stream when the consumer circuit (12C) expects more data than output by the producer circuit (12P), and discarding data communicated by the producer circuit (12P) when the consumer expects less data than that output by the producer circuit (12P).

Abstract: A method of processing a frame received at a networked device having a port switch and a general-purpose processor. The method can include receiving frame information at the port switch, determining at least one port for the frame, and directing the received frame information based on the determined port(s).

Abstract: Once data stagnation occurs in a query group which groups queries, a scheduler of a server apparatus calculates an estimated load value of each query forming the query group based on at least one of input flow rate information and latency information of the query. The scheduler divides the queries of the query group into a plurality query groups so that the sum of estimated load values of queries belonging to one query group becomes substantially equal to the sum of estimated load values of queries belonging to another query group. The divided query groups are reallocated to different processors respectively. Throughput in query processing of stream data in a stream data processing system can be improved.

Abstract: A control method of flow control scheme and a control module thereof are provided. The provided control method includes setting a value of the transaction packets and outputting data to an external device according to the value of the transaction packets. When a not-ready transaction packet is received, the value of the transaction packets is reduced and the data is transmitted according to the value of the transaction packets.

Abstract: An information processing apparatus includes an execution determination unit and a control unit. The execution determination unit determines whether a series of processes including multiple processes is executable at an execution time of the series of processes. The control unit selectively provides at least one recovery device for substituting for the series of processes when it is determined that the series of processes is not executable.

Abstract: A circuit including a first memory and a processor. The processor is configured to receive data from a host device and transfer the data from the circuit to a storage drive. The processor is configured to receive the data back from the storage drive when a second memory in the storage drive does not have available space for the data, and prior to the data being transferred from the second memory to a third memory in the storage drive. The processor is configured to: store the data received from the storage drive in the first memory or transfer the data received from the storage drive back to the host device; and based on a request received from the storage drive, transfer the data from the first memory or the host device back to the storage drive. The request indicates that space is available in the second memory for the data.

Abstract: For the transmission of a telegram from the control device to the peripheral element an intermediate device receives the telegram from the control device and forwards it without amendment to the peripheral element. For the transmission of a telegram from the peripheral element to the control device the intermediate device receives the telegram from the peripheral element and forwards it without amendment to the control device. The telegrams are safety telegrams, so that telegrams forwarded to the control device or to the peripheral element from the respective receiving unit can be checked for freedom from errors.

Abstract: There is provided a transmitter device including an interface unit that is an interface for connection to a receiver device via a transmission path, a pre-emphasis unit configured to generate a pre-emphasis signal, the pre-emphasis signal being obtained by adding to an input signal another signal for compensating for a high-frequency component of the input signal, and a transmission control unit configured to acquire identification information indicating whether the receiver device is capable of performing a process of receiving the pre-emphasis signal, switch the receiver device to a state in which the receiver device is capable of performing the process of receiving the pre-emphasis signal in accordance with the identification information, and control the pre-emphasis unit to generate the pre-emphasis signal.

Abstract: Memory associated with a mobile communication device, such as memory removably inserted into a memory card slot, may be accessed, in the alternative, by a mobile communication platform or by a remote USB host. A memory access module connected to the memory card slots is operative in one of two modes: a pass-through mode and a USB mode. In the pass-through mode, the memory card slots are directly connected, via switching circuits, to memory interfaces on the mobile communication platform. A USB interface on the mobile communication platform may additionally be connected, in pass-through mode, via a USB hub to a remote USB host. In the USB mode, the memory card slots are connected, via switching circuits, second memory interfaces, and a controller, to a USB hub supporting USB 3.0 transfer protocols, and accessible by a remote host.

Abstract: Managing a data transfer from one or more source storage devices to one or more target storage devices. The data transfer comprises concurrent transfer of a multiplicity of data units pursuant to respective data transfer commands. The concurrent transfer of the multiplicity of data units is currently in-progress. A computer determines a currently-overloaded storage component involved in the data transfer. The computer determines a plurality of the data transfer commands that involve the overloaded storage component. The computer determines an approximately-minimum number of the data transfer commands to cancel to stop overload of the overloaded storage component. In response, the computer cancels the minimum number of the data transfer commands.

Abstract: The present invention is directed to a method which allows for substitution of standard SAS ALIGN primitives with an alternative, more spectrally pure set of SAS ALIGN primitives that allows for enhanced continuous adaptation performance. Two consenting SAS devices which are connected to each other may negotiate for and start communicating using the alternate set of ALIGN primitives, which may allow for improved jitter tolerance and reduced bit error rate.

Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.

Abstract: A fieldbus gateway using a virtual serial fieldbus port and a data transmission method thereof are provided. By receiving a fieldbus frame containing target data through a virtual serial fieldbus port connected to a source device or a target device via a fieldbus gateway and sending another fieldbus frame containing the target data via other fieldbus port to target devices or source devices, the system and the method can provide two or more remote devices to control one controlled device at the same time. The invention also achieves the effect of using one virtual serial fieldbus port to transmit data between multiple source devices and target devices concurrently.

Abstract: Methods and apparatus for enhancing efficiency (e.g., reducing power consumption and bus activity) in a data bus. In an exemplary embodiment, a client-driven host device state machine switches among various states, each comprising a different polling frequency. A client device on the data bus (e.g., serial bus) checks for non-productive periods of polling activity, and upon discovering such a period, informs the host. The state machine then alters its polling scheme; e.g., switches to a lower state comprising a reduced polling frequency, and polling continues at this reduced frequency. In one variant, the client device continuously monitors itself to determine whether it has any data to transmit to a host device and if so, the host is informed, and the state machine restarts (e.g., to its highest polling state). By eliminating extraneous polling, power consumption and serial bus activity is optimized, potentially on both the host and the client.

Abstract: The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side.

Abstract: A CD on which only music information specified by the CD-DA is recorded, or a CD on which both music information specified by the CD-DA and music information to be recorded on a CD-ROM are recorded is mounted upon an information processing terminal. When the CD on which only music information specified by the CD-DA is recorded is mounted, the information processing terminal acquires, from a directory server, an ISRC number that identifies the music information recorded on the CD, and distribution server location information that identifies a content distribution server. The information processing terminal acquires content that is the music information compressed according to the MP3 and encrypted, from the content distribution server identified by the acquired distribution server location information, and the decryption key. The information processing terminal then decrypts the acquired content using the acquired decryption key and reproduces music.

Abstract: A USB peripheral device with a power connector, such as a card reader, which serves as a peripheral device when it is connected to a host device such as a smart phone, while which can directly charge the host device when a charger is plugged in, is disclosed. The peripheral device has a USB connector and a controller. The ID, D+, D? and VBUS pins of the USB connector are connected to the controller and the power connector through a plurality of relays depending upon whether the power connector is connected by a charger or not. The peripheral device can be automatically switched to serve as a B-device or a power bridge transferring power from the charger to the host device.

Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Abstract: A computer-implemented method may include determining a number of virtual functions that each port of a hardware input/output adapter is capable of supporting. The computer-implemented method may include assigning a first portion of internal resources of the hardware input/output adapter to each port of the hardware input/output adapter. The computer-implemented method may also include, for a particular port of the hardware input/output adapter, assigning a second portion of the internal resources to each virtual function that the particular port is capable of supporting. The second portion of the internal resources may be a subset of the first portion of the internal resources. The computer-implemented method may further include configuring a virtual function prior to a runtime to use the assigned second portion of the internal resources.

Abstract: A transmitting section 7a outputs a transmission signal to the side of a transmission line 1. A first switching section Qa1 outputs the transmission signal to the transmission line 1. A second switching section Qa2 outputs the transmission signal from the transmission line 1. A receiving section 9a receives the transmission signal from the transmission line 1. A first detecting section 13a detects the transmission signal flowing through the first switching section Qa1. A second detecting section 19a detects the transmission signal flowing through the second switching section Qa2. When the transmission signal from the transmitting section 7a is not detected at both the first and second detecting sections 13a and 19a, a selecting section 15a selects the receiving section 9a and outputs a reception signal.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract: A television with at least one connection, either wired or wireless. Detection of an active device connected to the connection results in proper software and hardware configuration of the television to properly communicate with the device and provide, for example, proper user interface support and access to the device.

Abstract: Provided are a storage device, controller, and method for using host transfer rates to select a recording medium transfer rate for transferring data to a recording medium. A host transfer rate of data with respect to a buffer is measured. Provided are a plurality of recording medium transfer rates at which data is transferred between the buffer and the recording medium. A determination is made of an amount of decrease in the host transfer rate. The recording medium transfer rate is selected based on the amount of decrease in the host transfer rate.

Abstract: In a system-on-chip (SoC) including a processor, a method is provided for stashing packet information that prevents cache thrashing. In operation, an Ethernet subsystem accepts a plurality of packets and sends the packets to an external memory for storage. A packet descriptor is derived for each accepted packet and is added to an ingress queue. Packet descriptors are transferred from the ingress queue to an egress queue supplying the packet descriptors to a processor. A context manager monitors the fill level of packet descriptors in the egress queue. In response to monitoring the fill level, the context manager stashes packets from the external memory into a cache, where each stashed packet is associated with a packet descriptor in the egress queue. Packet descriptors are transferred from the ingress queue to the egress queue in response to a number of packet descriptors in the egress queue falling below the fill level.

Abstract: Some of the embodiments of the present disclosure provide a method comprising categorizing each data packet of a plurality of data packets into one of at least two priority groups of data packets; and controlling transmission of data packets of a first priority group of data packets during a first off-time period such that during the first off-time period, data packets of the first priority group of data packets are prevented from being transmitted to a switching module from one or more server blades. Other embodiments are also described and claimed.

Abstract: Systems, methods, and computer-readable media for resuming a media object presented on a mobile device following a data loss event that interrupts the presentation of the media object, wherein live streaming services are used to deliver the media object are provided. During presentation of the media object, a reduced data rate at which data is communicated to the mobile device is observed. The reduced data rate interrupting the presentation of the media object. An indication to pause delivery of the media object to the mobile device is provided. A preferred data rate at which data is communicated to the mobile device is observed and, thereafter, an indication to resume delivery of the media object to the mobile device is communicated.

Abstract: Systems, methods and computer program products for generic device integration within an auto-id system. The system includes an auto-id node operable to collect data emitted by one or more automatic data acquisition devices, process the data, and make the data available to one or more enterprise applications, user interfaces, or other auto-id nodes. The auto-id node includes a device integration layer that is operable to handle communication between the auto-id node and different types of automatic data acquisition devices, device controllers, or device management systems.

Abstract: An input/output (I/O) method, system, and computer program product are disclosed. An incoming I/O request is received from an application running on a processor. A tree structure including processor-executable instructions defines one or more layers of processing associated with the I/O request. The instructions divide the data in the I/O request into one or more chunks at each of the one or more layers of processing. Each instruction has an associated data dependency to one or more corresponding instructions in a previous layer. The instructions are sorted into an order of processing by determining a location of each chunk and data dependencies between chunks of different layers of processing. One or more instructions are inserted into a schedule that depends at least partly on the order of processing. The I/O request is serviced by executing the instructions according to the schedule with the processor according to the order of processing.

Abstract: To inhibit the occurrence of communication failures in the system in which a secondary storage control apparatus acquires journal data from a primary storage control apparatus and writes the data to a secondary volume. The primary storage control apparatus comprises a command processing unit, a journal data creation unit, a journal data transfer unit which reads journal data to the secondary storage control apparatus, and a transfer control unit. In specified occasions, the transfer control unit controls at least either one of the journal data transfer amount by the journal data transfer unit and the width of the communication band utilized for journal data transfer.

Abstract: A system and method for a establishing a data connection between peripherals through a global computer network. The global computer network having at least two computerized addressable stations connected to a network, and each of the stations including at least one input and at least one output. A computerized server with a storage assembly with software that includes sufficient data and instructions to communicate with the stations to keep a database with information of the station's peripheral resources updated. Each station includes a service software that initiates upon booting the station and keeps track of the peripheral resources and assigned address (ex. IP address) for periodically updating the server's database with changes. Users with friendly interfaces have access to the subscribed stations and their resources as requested and target stations.

Abstract: An efficient low latency buffer, and method of operation, is described. The efficient low latency buffer may be used as a bi-directional memory buffer in an audio playback device to buffer both output and input data. An application processor coupled to the bi-directional memory buffer is responsive to an indication to write data to the bi-directional memory buffer reads a defined size of input data from the bi-directional memory buffer. The input data read from the bi-directional memory buffer is replaced with output data of the defined size. In response to a mode-change signal, the defined size of data is changed that is read and written from and to the bi-directional memory buffer. The buffer may allow the application processor to enter a low-powered sleep mode more frequently.

Abstract: The present disclosure includes methods, devices, and systems for device to device flow control. In one or more embodiments, a system configured for device to device flow control includes a host and a chain of devices, including one or more memory device, coupled to each other and configured to communicate with the host device through a same host port. In one or more embodiments, at least one device in the chain is configured to regulate the flow of data by sending a token in downstream data packets, the token allowing devices downstream from the respective at least one device to send an upstream data packet to the respective at least one device.

Abstract: In one embodiment, a receiver on a credit-based flow-controlled interface is configured to free one or more data credits early when a data payload is received that incurs fewer unused data credits within a buffer memory that is allocated at a coarser granularity than the data credits. In another embodiment, header credits and data credits are dynamically adjusted based on actual packet data payload sizes.