Flow Controlling Patents (Class 710/29)
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Publication number: 20140297902Abstract: Techniques for rate governing of a display data stream are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a graphics management module comprising a differential analyzer. In some embodiments, the graphics management module may be operative on the processor circuit to determine a target display data transmission rate for one or more displays, determine, by the differential analyzer, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate, transmit the one or more display data packets based on the actual display data transmission rate, and accumulate a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets. Other embodiments are described and claimed.Type: ApplicationFiled: December 21, 2011Publication date: October 2, 2014Inventors: Nausheen Ansari, Todd M. Witter
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Patent number: 8843671Abstract: Various embodiments of the invention provide resource management of available data bandwidth of a SAS system in a non-uniform way. In certain embodiments, arbitration wait time values are adaptively modified to achieve a specified performance quota for a link.Type: GrantFiled: February 27, 2012Date of Patent: September 23, 2014Assignee: PMC-Sierra US Inc.Inventors: Gregory Arthur Tabor, Kurt Marshall Schwemmer, John Matthew Adams
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Patent number: 8837282Abstract: In one embodiment, a method includes obtaining a message associated with a data flow that includes a first indicator that identifies an amount of requested pool bandwidth and a second indicator that identifies a pool with which the data flow is associated. The pool is associated with a plurality of data flows that includes the data flow. The method also includes determining whether the pool has an overall bandwidth allocation, and, if so, determining whether reserving the amount of requested bandwidth would cause the overall bandwidth allocation to exceed a maximum pool bandwidth allocation. Finally, the method includes reserving approximately the amount of requested bandwidth when it is determined that reserving the amount of requested bandwidth would not cause the overall bandwidth allocation to exceed the maximum pool bandwidth allocation. Reserving approximately the amount of requested bandwidth includes increasing the overall bandwidth allocation by the amount of requested bandwidth.Type: GrantFiled: November 8, 2011Date of Patent: September 16, 2014Assignee: Cisco Technology, Inc.Inventors: James M. Polk, Paul E. Jones, Subhasri Dhesikan
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Patent number: 8838849Abstract: Sharing at least one link among a plurality of processes includes determining a capacity of the at least one link based on a number of I/O operations per unit time supported by the at least one link as a function of the amount of data provided by each of the I/O operations, determining a requirement of each of the processes based on user specifications and an amount of data provided by each I/O operation for each of the processes, and apportioning link capacity among the processes according to the requirement of each of the processes. In response to a sum of requirements for each of the processes being less than the capacity of the at least one link, additional link capacity may be provided to at least some of the processes.Type: GrantFiled: December 8, 2011Date of Patent: September 16, 2014Assignee: EMC CorporationInventors: David Meiri, Dan Arnon
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Patent number: 8819303Abstract: In one embodiment, a method includes determining a request for a transfer of content where the request is associated with a user device. It is determined if a deferred transfer should be performed. The deferred transfer defers the transfer of the content with a completion by a completion time. The request is stored in a queue where the request is associated with the completion time. The method processes the request from the queue to transfer the content at a start time. The content is transferred by the completion time. The method then adjusts, for a user associated with the user device, a charging parameter for the transfer due to the transfer being deferred.Type: GrantFiled: July 25, 2011Date of Patent: August 26, 2014Assignee: General Instrument CorporationInventors: Ajith Venugopal, Anita Ramachandran
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Patent number: 8819306Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.Type: GrantFiled: December 28, 2012Date of Patent: August 26, 2014Assignee: Intel CorporationInventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David Lee
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Patent number: 8819305Abstract: In one embodiment, the present invention provides for a layered communication protocol for a serial link, in which a link layer is to receive and forward a message to a protocol layer coupled to the link layer with a minimal amount of buffering and without maintenance of a single resource buffer for adaptive credit pools where all message classes are able to consume credits. By performing a message decode, the link layer is able to steer non-data messages and data messages to separate structures within the protocol layer. Credit accounting for each message type can be handled independently where the link layer is able to return credits immediately for non-data messages. In turn, the protocol layer includes a shared buffer to store all data messages received from the link layer and return credits to the link layer for these messages when the data is removed from the shared buffer. Other embodiments are described and claimed.Type: GrantFiled: November 16, 2009Date of Patent: August 26, 2014Assignee: Intel CorporationInventors: Daren J. Schmidt, Bryan R. White
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Patent number: 8812752Abstract: Methods and systems for a connector interface in a data pipeline are disclosed. A pipeline comprising two data source nodes and an activity node is configured. Each data source node represents data from a different data source, and the activity node represents a workflow activity that uses the data as input. Two connectors which implement the same connector interface are triggered. In response, data is acquired at each connector from the corresponding data source through the connector interface. The data is sent from the connectors to the activity node through the connector interface. The workflow activity is performed using the acquired data.Type: GrantFiled: February 11, 2013Date of Patent: August 19, 2014Assignee: Amazon Technologies, Inc.Inventors: Kathryn Marie Shih, Eider Brantly Moore, Richard Rex McKnight, Vaibhav Aggarwal, Peter Sirota, Richard Jeffrey Cole, James P. Bartlett, Carl Louis Christofferson
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Patent number: 8806178Abstract: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.Type: GrantFiled: August 14, 2013Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Jane H. Bartik, Lisa C. Heller, Damian L. Osisek, Donald W. Schmidt, Patrick M. West, Jr., Phil C. Yeh
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Patent number: 8804507Abstract: A method, apparatus and computer program product for temporal-based flow distribution across multiple packet processors is presented. A packet is received and a hash identifier (ID) is computed for the packet. The hash ID is used to index into a State Table and to retrieve a corresponding record. When a time credit field of the record is zero then the time credit field is set to a to a new value; a Packet Processing Engine (PE) whose First-In-First-Out buffer (FIFO) has the lowest fill level is selected; and a PE number field in the state table record is updated with the selected PE number. When the time credit field of the record is non-zero then the packet is sent to a PE based on the value stored in the record; and the time credit field in the record is decremented if the time credit field is greater than zero.Type: GrantFiled: March 31, 2011Date of Patent: August 12, 2014Assignee: Avaya, Inc.Inventor: Hamid Assarpour
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Patent number: 8806066Abstract: A method for expanding input/output in an embedded system is described in which no additional strobes or enable lines are necessary from the host controller. By controlling the transitions of the signal levels in a specific way when controlling two existing data or select lines, an expansion input and/or output device can generate a strobe and/or enable signal internally. This internal strobe and/or enable signal is then used to store output data or enable input data. The host controller typically utilizes software or firmware to control the data transitions, but no additional wires are needed, and no changes are needed to existing peripheral devices. Thus, an existing system can be expanded when there are no additional control lines available and no unused states in existing signals.Type: GrantFiled: March 5, 2012Date of Patent: August 12, 2014Assignee: Schuman Assets Bros. LLCInventor: Stephen Waller Melvin
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Patent number: 8799528Abstract: One embodiment provides a data transfer device, including: a register configured to set an upper limit value for a transfer data size; and a transfer size controller configured to compare the upper limit value and the transfer data size sent from an external device, and to reduce the transfer data size when the transfer data size is larger than the upper limit value.Type: GrantFiled: February 29, 2012Date of Patent: August 5, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Kikuchi
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Patent number: 8799535Abstract: In one example, multimedia content is requested from a plurality of storage modules. Each storage module retrieves the requested parts, which are typically stored on a plurality of storage devices at each storage module. Each storage module determines independently when to retrieve the requested parts of the data file from storage and transmits those parts from storage to a data queue. Based on a capacity of a delivery module and/or the data rate associated with the request, each storage module transmits the parts of the data file to the delivery module. The delivery module generates a sequenced data segment from the parts of the data file received from the plurality of storage modules and transmits the sequenced data segment to the requester.Type: GrantFiled: January 11, 2008Date of Patent: August 5, 2014Assignee: Akamai Technologies, Inc.Inventors: Michael G. Hluchyj, Santosh Krishnan, Christopher Lawler, Ganesh Pai, Umamaheswar Reddy
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Patent number: 8788732Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.Type: GrantFiled: August 21, 2013Date of Patent: July 22, 2014Assignee: NetLogic Microsystems, Inc.Inventors: Julianne J. Zhu, David T. Hass
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Patent number: 8782300Abstract: An electronic apparatus provided with a serial communication circuit achieving a baud rate adjustment with high precision is provided. For example, a bit width of each of a plurality of bits in received serial data is measured by a clock counter, and an average value of the bit width is calculated detecting its maximum value and minimum value. Moreover, for example, a maximum tolerance and a minimum tolerance are calculated as a value substantially 1.5 times the average value and a value substantially 0.5 times the average value, and determination is made as to whether or not the maximum value and the minimum value are within a range between the maximum tolerance and the minimum tolerance. If they are within the range, the corresponding average value is set in a baud rate setting register.Type: GrantFiled: December 3, 2012Date of Patent: July 15, 2014Assignee: Sanken Electric Co., Ltd.Inventors: Ayumi Hiromatsu, Masahiro Katayama, Takanaga Yamazaki
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Patent number: 8769164Abstract: In a first aspect, a first method is provided for self-adjusting allocation of memory bandwidth in a network processor system. The first method includes the steps of (1) determining an amount of memory bandwidth of a network processor used by each of a plurality of data types; and (2) dynamically adjusting the amount of memory bandwidth allocated to at least one of the plurality of data types based on the determination. Numerous other aspects are provided.Type: GrantFiled: September 18, 2003Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Merwin H. Alferness, William J. Goetzinger, Kent H. Haselhorst, Lonny Lambrecht, Joshua W. Rensch
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Patent number: 8761012Abstract: The packet relay apparatus is provided. The packet relay apparatus includes a receiver that receives a packet; and a determiner that determines to drop the received packet without storing the received packet into a queue among the multi-stage queue. The determiner determines to drop the received packet at a latter stage, based on former-stage queue information representing a state of a queue at any former stage which the received packet belongs to and latter-stage queue information representing a state of a queue at the latter stage which the received packet belongs to.Type: GrantFiled: January 18, 2011Date of Patent: June 24, 2014Assignee: Alaxala Networks CorporationInventors: Takahiro Yamada, Hideki Hinosugi
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Publication number: 20140173143Abstract: The present invention relates to the field of communications technologies and discloses a data processing method and apparatus to obtain a DPD non-linear distortion compensation coefficient under a QPSK mode. The embodiments of the present invention receive a first data flow, and perform interpolation into the first data flow to obtain a second data flow; receive a third data flow, and calculate a data flow signal quality difference between the third data flow and the second data flow; and obtain a DPD non-linear distortion compensation coefficient according to the data flow signal quality difference and the third data flow or the second data flow. The embodiments of the present invention are applicable to the scenarios of obtaining a DPD non-linear distortion compensation coefficient in QPSK mode.Type: ApplicationFiled: February 21, 2014Publication date: June 19, 2014Applicant: Huawei Technologies Co., Ltd.Inventors: Hai Li, Huaping Shi, Yanzhao Pang, Christian Mazzucco, Sergio Bianchi, Xianfeng Li
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Patent number: 8756349Abstract: Methods and apparatus relating to an inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline are described. In one embodiment, logic may arbitrate between two queues based on various rules. The queues may store data including local or remote requests, data responses, non-data responses, external interrupts, etc. Other embodiments are also disclosed.Type: GrantFiled: December 28, 2013Date of Patent: June 17, 2014Assignee: Intel CorporationInventors: James R. Vash, Bongjin Jung, Pritpal S. Ahuja
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Patent number: 8738825Abstract: Some of the embodiments of the present disclosure provide a method comprising categorizing each data packet of a plurality of data packets into one of at least two priority groups of data packets; and controlling transmission of data packets of a first priority group of data packets during a first off-time period such that during the first off-time period, data packets of the first priority group of data packets are prevented from being transmitted to a switching module from one or more server blades. Other embodiments are also described and claimed.Type: GrantFiled: April 22, 2013Date of Patent: May 27, 2014Assignee: Marvell International Ltd.Inventor: Martin White
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Patent number: 8738757Abstract: A network element disposed in a network, where the network element implements a process to manage load distribution across a plurality of network interfaces of the network. The network element redirects traffic flow directed toward the plurality of network interfaces in response to changes in configuration of the plurality of network interfaces, where each traffic flow is a set of protocol data units (PDUs), having an ordered delivery requirement, and where the PDUs are transmitted across the network between a source node and a destination node. The redirection process minimizes data traffic flow disruption when the load distribution is determined using a set of load distribution tables instead of a hashing algorithm.Type: GrantFiled: January 9, 2012Date of Patent: May 27, 2014Assignee: Telefonaktiebolaget L M Ericsson (Publ)Inventors: David Ian Allan, Eric Ward Gray, Joel Halpern, Scott Andrew Mansfield
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Patent number: 8732353Abstract: There is provided a transmitter device including an interface unit that is an interface for connection to a receiver device via a transmission path, a pre-emphasis unit configured to generate a pre-emphasis signal, the pre-emphasis signal being obtained by adding to an input signal another signal for compensating for a high-frequency component of the input signal, and a transmission control unit configured to acquire identification information indicating whether the receiver device is capable of performing a process of receiving the pre-emphasis signal, switch the receiver device to a state in which the receiver device is capable of performing the process of receiving the pre-emphasis signal in accordance with the identification information, and control the pre-emphasis unit to generate the pre-emphasis signal.Type: GrantFiled: June 24, 2013Date of Patent: May 20, 2014Assignee: Sony CorporationInventor: Shigehiro Kawai
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Patent number: 8706924Abstract: A data link transmitter in a PCI Express device for managing PCI-Express TLPs and DLLPs. The data link transmitter includes a priority system in which a DLLP for initializing flow control has highest priority, and an idle data character has lowest priority. Various embodiments include: a DLLP for power state entrance is lower priority than the DLLP for initializing flow control; a replay TLP for retry buffer re-transmission is lower priority than the DLLP for power state entrance, and a new TLP is lower priority than the replay TLP; an Ack/Nak DLLP is lower priority than the new TLP, a DLLP for updating flow control is lower priority than the Ack/Nak TLP, and a DLLP for acknowledging the DLLP for power state entrance is lower priority than the DLLP for updating flow control; a DLLP for updating flow control is lower priority than the DLLP for power state entrance.Type: GrantFiled: July 24, 2009Date of Patent: April 22, 2014Assignee: Via Technologies, Inc.Inventors: Yen-Ting Lai, Wen-Yu Tseng
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Patent number: 8705398Abstract: There is provided a mechanism for reporting buffer status information to a communication network control element when transmission via both a licensed and an unlicensed spectrum is conducted and offloading of traffic is executed. After an offloading value indicating the amount of traffic which can be offloaded from a transmission over a licensed spectrum to a transmission over an unlicensed spectrum is estimated, the UE determines a buffer size of at least one transmission buffer used in a transmission over the licensed spectrum and the unlicensed spectrum. Then, buffer status information is sent to the eNB wherein the estimated offloading value is considered. The eNB can then allocate resources for the transmission over the licensed band while benefits by the offloading to the unlicensed band are considered in the resource allocation.Type: GrantFiled: September 12, 2011Date of Patent: April 22, 2014Assignee: Broadcom CorporationInventors: Timo Koskela, Sami-Jukka Hakola, Samuli Turtinen
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Patent number: 8694700Abstract: Methods and apparatus for eliminating the need for a complete synchronization due to failure of a data protection appliance in a continuous data protection system having a replication splitter. In one embodiment, a continuous data protection system includes a source side having a source side storage array with a splitter and a data protection appliance, where processing includes initiating a source side splitter session, initializing a first I/O tracking mechanism for the splitter session, and activating the splitter to a source side processing active state to continuously push I/O data from the source side to the target side.Type: GrantFiled: September 29, 2010Date of Patent: April 8, 2014Assignee: EMC CorporationInventors: Assaf Natanzon, Arieh Don, David Meiri
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Method and apparatus for equalizing a bandwidth impedance mismatch between a client and an interface
Patent number: 8683089Abstract: One or more client engines issues write transactions to system memory or peer parallel processor (PP) memory across a peripheral component interconnect express (PCIe) interface. The client engines may issue write transactions faster than the PCIe interface can transport those transactions, causing write transactions to accumulate within the PCIe interface. To prevent the accumulation of write transactions within the PCIe interface, an arbiter throttles write transactions received from the client engines based on the number of write transactions currently being transported across the PCIe interface.Type: GrantFiled: December 30, 2009Date of Patent: March 25, 2014Assignee: Nvidia CorporationInventors: Raymond Hoi Man Wong, Samuel H. Duncan, Lukito Muliadi -
Patent number: 8683095Abstract: Systems, methods, and other embodiments associated with tracking packet identifiers are described. According to one embodiment, a method includes receiving packets of data, wherein each packet includes an encoded packet identifier, the encoded packet identifier being decoded into a decoded packet identifier, and after each packet is received, incrementing a first counter and a second counter for estimating a sequential value of the decoded packet identifier.Type: GrantFiled: May 19, 2011Date of Patent: March 25, 2014Assignee: Marvell International LtdInventors: Bin Ni, Darrel Burk
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Patent number: 8683094Abstract: A method for enhancing data transmission efficiency in a data transmission system having a host, a subsystem and a transmission interface, utilized for the host to transmit and receive a data from a memory of the subsystem via the transmission interface includes steps of the host outputting a query command to the subsystem via the transmission interface for querying available memory utilization of the subsystem; the subsystem outputting a return message to the host via the transmission interface for indicating the available memory utilization according to the query command; and controlling data transmission from the host to the subsystem according to the return message.Type: GrantFiled: October 16, 2009Date of Patent: March 25, 2014Assignee: Ralink Technology, Corp.Inventors: Ching-Hwa Yu, Chen-Hai Yu
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Patent number: 8683102Abstract: It may be difficult to give bus right to a bus master that cannot output a bus request signal when a bus arbitration apparatus is ready to grant bus permission precisely in a ratio of a preset number of times of the bus acquisition. The bus arbitration apparatus operates to wait until bus request signals of bus masters that have not performed transfers of the preset number of times of the bus acquisition are output while a bus slave operates.Type: GrantFiled: September 15, 2011Date of Patent: March 25, 2014Assignee: Canon Kabushiki KaishaInventor: Makoto Fujiwara
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Patent number: 8677032Abstract: A method of and apparatus for communicating between a host and an agent. The method includes the step of performing a first transaction between a host controller and a hub. The hub is operable to perform a single transaction with an agent based on the first transaction. The method then includes the step of performing a second transaction between the host controller and the hub. The second transaction is based on the single transaction.Type: GrantFiled: December 30, 2010Date of Patent: March 18, 2014Assignee: Intel CorporationInventors: John I. Garney, John S. Howard
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Patent number: 8671232Abstract: A system and method for dynamically migrating stash transactions include first and second processing cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), and an operating system (OS) scheduler. The first core executes a first thread associated with a frame manager. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers to indicate scheduling-out and scheduling-in of the first thread from the first core and to the second core. The STMMU uses the pre-empt notifiers to enable dynamic stash transaction migration.Type: GrantFiled: March 7, 2013Date of Patent: March 11, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Vakul Garg, Varun Sethi
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Patent number: 8671229Abstract: A method, computer program product, and computing system for receiving an IO request from a host concerning an IO operation to be performed on a data array. The IO request is processed to generate an IO descriptor. The IO descriptor defines a unique and proprietary memory space for each of a plurality of IO processing routines.Type: GrantFiled: June 30, 2012Date of Patent: March 11, 2014Assignee: EMC CorporationInventors: Alan L. Taylor, Miles A. de Forest, Michael D. Haynes
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Patent number: 8665725Abstract: A system and method for hierarchical adaptive dynamic egress port and queue buffer management. Efficient utilization of buffering resources in a commodity shared memory buffer switch is key to minimizing packet loss. Efficient utilization of buffering resources is enabled through adaptive queue limits that are derived from an adaptive port limit.Type: GrantFiled: June 15, 2012Date of Patent: March 4, 2014Assignee: Broadcom CorporationInventors: Bruce Kwan, Puneet Agarwal
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Patent number: 8667167Abstract: A method for controlling a transmission rate of a communication interface includes detecting, for a plurality of times, data traffic that passes through a first communication interface of a first device within a preset period; when the traffic rates at which the data traffic passes through the first communication interface within the preset period are lower than a first threshold, sending a rate reduction request message to a second device that includes a second communication interface, so that the second device configures a rate of the second communication interface as a first transmission rate that is lower than a current transmission rate of the second communication interface and that is supported by both communication interfaces after receiving the rate reduction request message. In this way, power consumption of the communication interface may be reduced.Type: GrantFiled: July 16, 2012Date of Patent: March 4, 2014Assignee: Huawei Technologies Co., Ltd.Inventor: Qingyin Fang
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Patent number: 8654626Abstract: A packet sorting device includes: a buffer for storing packets belonging to a plurality of communication flows; and a control section which determines, when receiving one of a series of packets, whether the one of the received packets is a disorder packet by a determination process, and sorts the received packets in a correct order by storing the disorder packet and communication flow information thereof in the buffer so that the disorder packet and communication flow identification information are correlated. The disorder packet is one of the received packets which is received in an order different from a transmission order of the packets. The communication flow information identifies the plurality of communication flows.Type: GrantFiled: August 4, 2011Date of Patent: February 18, 2014Assignee: NEC CorporationInventors: Kiyohisa Ichino, Norio Yamagaki
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Patent number: 8645592Abstract: Techniques are disclosed for managing the flow of IO jobs from a client to a hardware device such that resource starvation is reduced without significantly impacting throughput. Each flow can be assigned an amount of time that a hardware device can deplete completing IO jobs from the client. When the allocated amount of time is used IO jobs associated with the client can be stored in a queue until the client obtains more time.Type: GrantFiled: October 30, 2012Date of Patent: February 4, 2014Assignee: Microsoft CorporationInventors: Dustin L. Green, Yau Ning Chin, Bruce L. Worthington
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Patent number: 8645591Abstract: A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.Type: GrantFiled: January 26, 2012Date of Patent: February 4, 2014Assignee: AFTG-TG, LLCInventor: Phillip M. Adams
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Patent number: 8645527Abstract: A network monitoring device includes a data structure for maintaining information about endpoints involved in network flows. Each endpoint, either a source or a destination for a network flow, has information maintained in a modified binary trie, having a branch for each bit of the source or destination address, but with interior nodes having only a single child node elided. A pruning thread is given a limited amount of time for operation, with the effect that the data structure is maintained available for use except for only that limited amount of time. In the event that the pruning thread is unable to prune the entire data structure, it maintains a marker indicating where last it left off, and returns to that location in the data structure at a later pruning operation.Type: GrantFiled: July 25, 2008Date of Patent: February 4, 2014Assignee: Xangati, Inc.Inventors: Rosanna Lee, Xiaohong Pan, Rangaswamy Jagannathan, Derek Sanders, Kishor Kakatkar
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Patent number: 8645590Abstract: The present invention is directed to a method which allows for substitution of standard SAS ALIGN primitives with an alternative, more spectrally pure set of SAS ALIGN primitives that allows for enhanced continuous adaptation performance. Two consenting SAS devices which are connected to each other may negotiate for and start communicating using the alternate set of ALIGN primitives, which may allow for improved jitter tolerance and reduced bit error rate.Type: GrantFiled: January 18, 2012Date of Patent: February 4, 2014Assignee: LSI CorporationInventors: William W. Voorhees, Patrick R. Bashford, Harvey J. Newman
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Publication number: 20140032796Abstract: The present disclosure provides a system for processing local input/output. The system includes a processor coupled to a host memory through a memory controller. The system also includes an upper device communicatively coupled to the memory controller. The upper device includes one or more transmit/receive work queues. The system also includes a lower device communicatively coupled to the upper device, wherein the lower device is stateless. Data packets passed between the upper device and the lower include a data flow identifier used to identify data flow resources of the upper device and the lower device corresponding to the data packet.Type: ApplicationFiled: April 13, 2011Publication date: January 30, 2014Inventor: Michael R. Krause
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Publication number: 20140032795Abstract: The present disclosure provides an electronic device that includes a lower device configured to process local input/output communications between the electronic device and a host, wherein the lower device is stateless. The electronic device also includes a memory comprising a data flow identifier used to associate a data flow resource of the host with a data flow resource corresponding to the lower device. A data packet sent from the lower device to the host includes the data flow identifier.Type: ApplicationFiled: April 13, 2011Publication date: January 30, 2014Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventor: Michael R. Krause
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Patent number: 8631253Abstract: A mechanism for a manager and host-based integrated power saving policy in virtualization systems is disclosed. A method of the invention includes receiving configuration and power information of a host machine from a management agent on the host machine, performing a macro-level power saving scheduling algorithm that takes into consideration the received configuration and power information of the host machine, and requesting that the host machine alter a number of active running CPU cores as part of the macro-level power saving scheduling algorithm.Type: GrantFiled: August 17, 2010Date of Patent: January 14, 2014Assignee: Red Hat Israel, Ltd.Inventors: Dor Laor, Itamar Heim
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Patent number: 8626968Abstract: Methods and apparatus relating to an inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline are described. In one embodiment, logic may arbitrate between two queues based on various rules. The queues may store data including local or remote requests, data responses, non-data responses, external interrupts, etc. Other embodiments are also disclosed.Type: GrantFiled: December 26, 2010Date of Patent: January 7, 2014Assignee: Intel CorporationInventors: James R. Vash, Bongjin Jung, Pritpal S. Ahuja
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Patent number: 8626966Abstract: Systems and methods and computer program products are disclosed to determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method includes, forming a logical channel from a source device to a sink device where the logical channel is configured to carry the source data stream and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel. Another method includes, detecting a logical channel in a received data stream where the logical channel includes the source data stream, recovering one or more rate parameters from the received data stream, determining a data rate of the logical channel, and determining the data rate of the source data stream based on the data rate of the logical channel and the one or more rate parameters.Type: GrantFiled: March 23, 2012Date of Patent: January 7, 2014Assignee: ATI Technologies ULCInventors: Nicholas J. Chorney, Collis Q. Carter
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Patent number: 8621119Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.Type: GrantFiled: January 14, 2013Date of Patent: December 31, 2013Assignee: Hitachi, Ltd.Inventors: Kazuyoshi Serizawa, Yasutomo Yamamoto, Norio Shimozono, Akira Deguchi, Hisaharu Takeuchi, Takao Sato, Hisao Homma
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Patent number: 8619555Abstract: Method and system for handling error events on a current path for processing an I/O request for reading information from and writing information to a storage space is provided. A system is able to communicate with the storage space via more than one path. If the current path reports an error event, then an alternate path quality is determined to ascertain whether the alternate path will generate an error similar to the current path. The alternate path quality is determined based on a plurality of factors which are assigned certain weights. The weights are determined based on a likely contribution of each factor to a repetition of the error reported by the current path. If the alternate path quality is equal to or exceeds a programmable threshold value, then the alternate path is selected.Type: GrantFiled: November 17, 2010Date of Patent: December 31, 2013Assignee: Netapp, Inc.Inventors: William D. Dallas, Chris Busick
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Patent number: 8621100Abstract: A system improves bandwidth used by a data stream. The system receives data from the data stream and partitions the data into bursts. At least one of the bursts includes one or more idles. The system selectively removes the idles from the at least one burst and transmits the bursts, including the at least one burst.Type: GrantFiled: February 27, 2009Date of Patent: December 31, 2013Assignee: Juniper Networks, Inc.Inventors: Sharada Yeluri, Kevin Clark, Shahriar Ilislamloo, Chung Lau
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Patent number: 8612662Abstract: In one embodiment an electronic device comprises at least one processor, at least one PCI express link, a virtual channel/sub-link flow control module, and a memory module communicatively connected to the one or more processors and comprising logic instructions which, when executed on the one or more processors configure the one or more processors to determine, in an electrical device, whether a virtual channel/sub-link is inactive, and in response to a determination that at least one virtual channel/sub-link is inactive, reallocate queue space from the at least one inactive channel to at least one active channel.Type: GrantFiled: June 1, 2008Date of Patent: December 17, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventor: Hahn Vo Norden
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Patent number: 8612647Abstract: Devices, systems, and methods are provided involving queue management. One embodiment includes a computing device having a priority aware queue. In this embodiment, the device includes a queue having a number of counters associated therewith to monitor a number of items each having a classification level associated therewith. The device also includes computer executable instructions to review each of the number of counters to determine whether to discard the item based upon whether at least one of the counters indicates that a higher classification item is being held in the queue.Type: GrantFiled: April 12, 2005Date of Patent: December 17, 2013Assignee: Hewlett—Packard Development Company, L.P.Inventors: Lewis S. Kootstra, Jonathan M. Watts
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Patent number: 8606934Abstract: Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.Type: GrantFiled: January 5, 2009Date of Patent: December 10, 2013Assignee: Intel CorporationInventors: Mani Ayyar, Srinivas Chennupaty, Akhilesh Kumar, Doddabaliapur Narasimha-Murthy Jayasimha, Murugasamy Nachimuthu, Phanindra K. Mannava, Ioannis T. Schoinas