Abstract: A RAID controller attached to a storage network can detect the presence of multiple pathways to the same physical storage device. A path collection module can dynamically maintain all valid pathways to all attached storage devices. A path selection module can automatically and dynamically balance and rebalance desired paths to each storage device so as to simultaneously optimize data flow and provide continuity of I/O service throughout the attached storage network.

Abstract: To provide stable processing performance and perform an appropriate failure processing in a storage device. A storage device includes a plurality of controllers; a plurality of storage drives; and a switch device including a plurality of controller-side ports respectively connected to the plurality of controllers and a plurality of drive-side ports respectively connected to the plurality of storage drives. The switch device performs address translations between the plurality of controller-side ports and the plurality of drive-side ports.

Abstract: A communication device for a vehicle includes: a memory; and a processor that is coupled to the memory, the processor being configured to: generate a first address for a time at which a first control device, which carries out control of a vehicle, communicates with a second control device, carry out communication with the second control device via the first address, and receive, from the second control device, information that specifies the first control device, and on the basis of the information that is received, set, in place of the first address, a second address that corresponds to an instrument that the first control device controls.

Abstract: An apparatus and method are described, the apparatus comprising: a cache comprising a plurality of entries, each associated with a partition identifier; storage circuitry to store counters, each indicative of a number of entries in the cache associated with respective partition identifiers; and cache control circuitry responsive to a request identifying a given partition identifier to control allocation of an entry dependent on the counter associated with the given partition identifier. The cache control circuitry increments the counter associated with the given partition identifier in response to an entry associated with the given partition identifier being allocated, and decrements the counter associated with the given partition identifier in response to an entry associated with the given partition identifier being evicted or replaced.

Abstract: A system includes a memory, a processor, and an accelerator circuit. The accelerator circuit includes an internal memory, an input circuit block, a filter circuit block, a post-processing circuit block, and an output circuit block to concurrently perform tasks of a neural network application assigned to the accelerator circuit by the processor.

Abstract: An information processing apparatus includes a first controller and a second controller. The first controller performs processing dependent on hardware having a function. The second controller is connected to the first controller via a general-purpose communication path and performs processing not dependent on the hardware. Each of the first controller and the second controller transmits control information used for controlling the hardware to a counterpart controller of the first controller or the second controller via the communication path while varying a transmission interval in accordance with a type of the control information.

Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

Abstract: In various embodiments, methods and systems for implementing distributed data object management are provided. The distributed data object management system includes a local metadata-consensus information store and one or more remote metadata-consensus information stores for metadata-consensus information and a local data store and one or more remote data stores for erasure coded fragments. For a write operation, corresponding metadata writes and data writes are performed in parallel using a metadata write path and a data write path, respectively, when writing to the local metadata-consensus information store and the one or more remote metadata-consensus information stores and the local data store and the one or more remote data stores. And, for a read operation, corresponding metadata reads and data reads are performed in parallel using a metadata read path and a data read path, respectively, when reading from the metadata-consensus information stores and the data stores.

Abstract: A source device and a sink device may be connected using an interface cable comprising at least first and second physical channels. The first physical channel may be used to transmit video data unidirectionally from the source device to the sink device. In addition, the second physical channel may comprise an audio return channel wherein audio data can be transmitted unidirectionally from the sink device to the source device at a first rate. In addition, the second physical channel may also transmit bidirectional control data between the source and sink devices at a second rate slower than the first rate. The audio data may be overlaid on the control data, wherein the audio data is transmitted using differential signaling, while the control data is transmitted using common mode signaling.

Abstract: To provide stable processing performance and perform an appropriate failure processing in a storage device. A storage device includes a plurality of controllers; a plurality of storage drives; and a switch device including a plurality of controller-side ports respectively connected to the plurality of controllers and a plurality of drive-side ports respectively connected to the plurality of storage drives. The switch device performs address translations between the plurality of controller-side ports and the plurality of drive-side ports.

Abstract: A cascading board, a solid state drive (SSD) shared remote access system and method relate to the communications field and used to perform shared remote access to an SSD. One end of the cascading board is coupled to a remote direct memory access (RDMA) network, and another end is coupled to an SSD. The cascading board includes an access processing apparatus and a processor coupled to the access processing apparatus. The processor is configured to initialize the access processing apparatus and the SSD. The access processing apparatus is configured to implement RDMA to the SSD when receiving an access command from the RDMA network.

Abstract: Provided is a control apparatus that can correctly obtain the execution status information of the instruction whose sender is the control apparatus itself. The controller (3) controls operations of the IO-Link device (2) via the IO-Link master (1), and includes the writing part (300) transmitting an instruction for the IO-Link device (2) and an identification of the instruction to the IO-Link master (1) and the reading part (301) retrieving an execution status information (status) indicating the execution status of the instruction by using the identification information.

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

Abstract: Adaptive control of Input/Output (I/O) operations in a data storage system is provided to enable efficient use of the data storage system. More specifically, an interface is provided in order to adaptively control I/O operations to the data storage system. The interface receives a data request. The interface mediates with the data storage system and employs a handle which references one or more files. The handle designates how to process the data request associated with the referenced one or more files. The interface supports execution of the data request in accordance with the handle. Accordingly, the interface provides adaptive direct management of the data storage system at file granularity and/or at data request granularity as designated in the handle(s).

Abstract: Provided are an apparatus, system, and method relating to detecting, during a system boot operation, whether a device arranged to implement a first bus interface protocol is coupled to a system through a connector. A bus clock is programmed to be off in response to detection of no device implementing the first bus interface protocol being coupled to the system through the connector. After the bus clock is programmed to be off, a buffer is reprogrammed to assume that the connector implements a second bus interface protocol coupled to a storage device. After reprogramming the buffer, the apparatus, system, and method detect whether a device arranged to implement the second bus interface protocol is coupled to the connector, and the device arranged to implement the second bus interface protocol is initialized in response to detection that the device is coupled to the connector. Other embodiments are described and claimed.

Abstract: A method and a device for sharing a PCIe I/O device, and an interconnection system are provided. The method includes: determining a shared PCIe I/O device in a PCIe interconnection system; establishing, by using a BAR at a working node, a first mapping relationship between an address of a CSR of the shared PCIe I/O device and an address, used for processing the CSR, in a working node domain. The method also includes establishing, by using an A-LUT fragment at a management node side of the NTB, a second mapping relationship between an address, used for receiving an MSI-X interrupt of the shared PCIe I/O device, in a management node domain and an address, used for processing the MSI-X interrupt, in the working node domain.

Abstract: The present invention relates to a method and system for installing software onto a client in the NIM environment and corresponding client. Said method includes: initializing said client, wherein a virtual mapping device associated with a memory driver of the client is created, the virtual mapping device for scheduling between the client's memory driver and the remote NIM server with respect to the I/O operation for running the software so as to direct the I/O operation for running said software to the client's memory driver or the remote NIM server; running said software on the client; acquiring the resources desired for running software; and conducting data migration operation from the NIM server to the client while running said software, wherein the migrated data is the resource data obtained from NIM server and desired for installing said software; and the software installation being completed when all the data desired for installing said software are migrated to the memory driver of the client.

Abstract: In general, embodiments of the technology relate to writing data to storage appliances. More specifically, embodiments of the technology are directed to writing data to storage media using a push-based mechanism in which clients provide the data to write to the storage media and then subsequently provide a command to write the data to the storage media.

Abstract: Two computing devices utilizing remote direct memory access to exchange digital data across a computer network can utilize existing registered memory and can transmit the digital data in slices, one after another while simultaneously registering a larger quantity of memory and, when complete, the rest of the digital data can be transmitted as a single block. Completion of the memory registration triggers a notification comprising a token, providing the sending computing device with direct access to the registered memory on the receiving computing device, and further a quantity of the digital data that has already been properly received via the slices. On the sending computing device, the registered memory is that from which the digital data is being sliced, and, on the receiving computing device, that into which the digital data is being reassembled from the slices.

Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

Abstract: This invention discloses a data processing circuit and a data processing method. The data processing method controls data transmission between a USB control unit and a USB interface, and includes the steps of: detecting a voltage of a configuration channel pin of the USB interface to generate a detection signal; determining whether the USB control unit and the USB interface are connected according to the detection signal; and performing an audio signal processing procedure when the USB control unit and the USB interface are not connected.

Abstract: A hypervisor receives a request pertaining to a multi-function device managed by the hypervisor from a guest operating system of a virtual machine where the multi-function device comprises a main function and a plurality of sub-functions and the request identifies an address within a configuration space associated with one of the plurality of sub-functions of the multi-function device. The hypervisor determines the main function of the multi-function device in view of the address of the configuration space associated with the sub-function, accesses a data structure associated with the main function to obtain an indicator of availability of the main function to the guest operating system, and determines, view of the indicator of availability, whether the main function is available to the guest operating system.

Abstract: Peripherals (18, 20, 22, 24, 26) are connected to a processor (6) and a programmable peripheral interconnect (10) is connected to each peripheral. One of the peripherals (18) is configured to signal an event to the interconnect, and one of the peripherals (20) is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral (20) has a task register (40), addressable by the processor (6), and performs the task in response to a change in the contents of the register (40). The interconnect (10) accesses a memory (14) in which a mapping is stored between an event of a first peripheral (18) and a task of a second peripheral (20), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (40). The mapping causes the interconnect (10) to provide a channel by sending a task signal to the second peripheral (20) in response to a signal of the event from the first peripheral (18).

Abstract: A new serial bus interface module that enables constrained sensor systems to better match flash-based storage devices' (SD card) read and write performance. The serial bus interface module augments existing flash-based storage with non-volatile random-access memory to form a hybrid storage system using the most popularly used master-slave bus architecture. Together with PSC-like features, the serial bus interface module not only enables slave-to-slave transfer (therefore eliminating the double-transaction problem) but also reads caching (one source to multi-sink) and buffering while flushing. These transaction types enable multi-sector write for significantly faster speed and lower energy overhead, while the use of non-volatile memory for metadata caching means low risk of file-system corruption in the event of power failure. The serial bus interface also enables the direct data transfer from sensors to storage or communication modules without requiring the microprocessor's intervention.

Abstract: In one aspect, a method includes filtering one or more available ports on a data storage system to determine candidate ports based on at least their hardware redundancy information. The data storage system includes one or more data storage volumes. The method also includes allocating one or more ports to the data storage volume from the candidate ports based on a usage metric to enable communication from a host, using the one or more allocated ports, to the data storage volume through the one or more storage components.

Abstract: Multiple storage apparatuses each provide a virtual logical volume composed of multiple logical pages to a host computer. A management computer determines a target logical page to which data are migrated to achieve a volume goal performance on the basis of access path information that can identify a storage apparatus that receives an I/O request in which the virtual logical volume is specified, an actual volume response performance, the volume goal performance to be attained, a page response performance of the logical page, and storage destination information that can identify a storage apparatus in which a storage area allocated to the logical page is present, and migrates data of the logical page between storage apparatuses.

Abstract: A method for providing application-related data includes connecting a mobile terminal and a device, determining an object displayed on the mobile terminal, determining a data file associated with the object, and controlling the data file associated with the object to be accessible by the connected device and controlling information of the data file to be displayed on a display of the connected device according to the determination of the object. A terminal that provides application-related data includes a connection unit connecting the terminal and another device to each other; and a synchronization unit, when the connection unit is connected to the another device, synchronizing related data of an application that is in the middle of execution in the terminal or an application selected by a user after the connection with the another device.

Abstract: A common touch panel controller is used for performing touch detection by driving both a touch panel superimposed on a display panel of a touch panel display portion for display, and a touch sensor superimposed on a touch key pattern of a touch key input portion for buttons. A control circuit capable of switching detection characteristics of a detection circuit common to the both in accordance with detection from the touch panel display portion and detection from the touch key input portion is adopted in the touch panel controller.

Abstract: A musical apparatus including a first audio looping device for being electrically coupled to a second audio looping device is provided. The first audio looping device being configured to receive a first audio signal from a first musical instrument and to store the first audio signal. The first audio looping device being further configured to playback the stored first audio signal as a first loop a first number of times. The first audio looping device being further configured to transmit synchronization information to the second audio looping device that stores a second audio signal and that plays back the stored second audio signal as a second loop a second number of times. The synchronization information enabling the first loop and the second loop to be synchronized with one another during playback.

Abstract: The present invention relates to a protection switching for use in a communication network, and more particularly, to a method and a system for protection switching provision by a distributed or extended protection group in a communication network.

Abstract: Methods and apparatus are provided for virtualizing resources such as host bus adapters connected to a storage area network. Resources are offloaded from individual servers onto a resource virtualization switch. Servers are connected to the resource virtualization switch using an I/O bus connection. Servers are assigned resources such as virtual host bus adapters and share access to physical host bus adapters included in the resource virtualization switch. Redundancy can be provided using multipathing mechanisms.

Abstract: A microcontroller has an input capture peripheral, wherein the input capture peripheral is configured to store timer values of an associated timer in a memory and wherein the input capture peripheral has a gating input which controls whether an input capture function is activated.

Abstract: A system including a host and a device. The device has at least one non-prefetchable storage location. The host and the device are configured to map the at least one non-prefetchable storage location into memory mapped input/output space that is addressed via greater than 32 address bits.

Abstract: A communication system is provided that includes at least two peripheral devices, wherein each peripheral device has at least one I/O interface and the peripheral devices are connected to each other by at least one data bus and exchange data by means of a communication relationship via the data bus. At least one interface device has a peripheral device interface and has a data bus interface, the interface device being connectable by the peripheral device interface thereof to one of the peripheral devices via an I/O interface thereof, and the interface device being connected by the data bus interface thereof to the data bus, and the communication relationship can be preset in the interface device.

Abstract: A device comprises circuitry configured for being communicatively coupled to a transceiver. In operation, the device is configured to receive a first message from another device to support at least one aspect of attachment of the device and the another device and to send, to the another device, a second message after the first message and prior to attachment. In operation, the device is further configured to receive, from the another device, a third message that is sent after the second message and prior to attachment and send, directly to the another device, data utilizing at least one channel for data transfer utilizing a second one of the addresses for identification in association with the device on the shared wireless communication medium, for data transfer after attachment in connection with a group that is controlled by the another device.

Abstract: The disclosed packet scheduler implements the deficit round robin (DRR) approximation of weighted fair queuing (WFQ), and is capable of achieving complete fairness across several hundred source flows, for example, each of which can be mapped to one of several destination ports. In addition to achieving fairness, the packet scheduler allows the user to map one or more optional strict-priority flows to each port. The packet scheduler keeps these strict-priority flows “outside” of the group of flows for which fairness is enforced. Each destination port can be optionally configured to chop its data packets into sub-packet pieces. The packet scheduler works in two mutually orthogonal dimensions: (1.) it selects destination ports based on a round-robin scheme, or using another method, such as guaranteed rate port scheduling (GRPS), and (2.) it implements optional strict-priority scheduling, and DRR scheduling.

Abstract: A method of operation of a storage controller system includes: accessing a first controller having a synchronization bus; accessing a second controller, by the first controller, through the synchronization bus; and receiving a first transaction layer packet by the first controller including performing a multi-cast transmission between the first controller and the second controller through the synchronization bus.

Abstract: A bridging board configured for connecting a processor with a hard disk backboard includes a first signal connecting apparatus, a second signal connecting apparatus, a plurality of duplexer and a signal conditioner. The first signal connecting apparatus is electronically connected to the processor. The second signal connecting apparatus electronically connected to the hard disk backboard. Each duplexer has an input terminal electronically connected to the first signal connecting apparatus, and two output terminals electronically connected to the second signal connecting apparatus to allow the processor to communicate with the backboard via the bridging board. The signal conditioner is electronically connected between the first signal connecting apparatus and the second signal connecting apparatus to amplify signals transmitted from the processor to the hard disk backboard.

Abstract: A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.

Abstract: A parameter management apparatus manages a plurality of parameters provided for control of an externally connected acoustic apparatus. The parameter management apparatus has a storing portion for storing a plurality of parameters stored in the acoustic apparatus. The parameter management apparatus selects, from among the parameters stored in the storing portion and the acoustic apparatus, respectively, at least one parameter for which a match is caused between the storing portion and the acoustic apparatus. The parameter management apparatus then causes exact a match between the at least one parameter stored in the storing portion and the at least one parameter stored in the acoustic apparatus.

Abstract: A method of extending a standard primitive in a data storage fabric is disclosed. A group of primitives are combined into a sequence including the standard primitive and a variable information primitive. The variable information primitive includes data particular to a broadcast of the sequence. The sequence is broadcast through the data storage fabric.

Abstract: An SD switch box embedded within a cellular handset, including circuitry for switching access to NAND storage that is embedded within the cellular handset, between a consumer electronic device that is external to and connected to the cellular handset, and between a base band modem that is embedded within the cellular handset, so as to enable shared use of the NAND memory by the consumer electronic device and by the base band modem, thereby enabling the cellular handset to be operational for cellular communication via its internal base band modem while its internal NAND memory is accessible to the external consumer electronics device.

Abstract: A computer system for obtaining vital product data (VPD) of a non-active component installed in the computer system. The computer system includes an active component, wherein the active component includes an optical sensor, wherein the optical sensor is positioned such that the optical sensor is able to scan an optically machine-readable representation of VPD of a non-active component when the non-active component is installed in the computer system, and wherein the non-active component includes the optically machine-readable representation of the VPD of the non-active component. The computer system is operable to scan the optically machine-readable representation of the VPD of the non-active component, decode the optically machine-readable representation of the VPD to determine the VPD of the non-active component, and store the determined VPD of the non-active component.

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A plurality of read lines (18), write lines (20) and data lines (22) interconnect the computers (12). When one computer (12) sets a read line (18) high and the other computer sets a corresponding write line (20) then data is transferred on the data lines (22). When both the read line (18) and corresponding write line (20) go low this allows both communicating computers (12) to know that the communication is completed. An acknowledge line (72) goes high to restart the computers (12).

Abstract: An electronic measuring device includes a detection channel module, a sampling module, a control unit, a data path selector and a memory device. A user will be able to selectively enable the desired detection channels and store only data collected from enabled channels. The data collected from the detection channels are in serial data form. The device utilizes a serial-parallel shifter in its sampling module to convert the serial data to parallel data bytes. Two indicators in the storage unit of the memory device allow users to effectively store the parallel data bytes in designated locations. The innovative data conversion and storage methods of this invention will significantly conserve memory space that otherwise will be occupied by data from the disabled channels and allow accurate and efficient reading of the stored data.

Abstract: A communication processing device includes a communication data processing circuit that (i) issues an access request for a buffer specified by a descriptor, among a plurality of buffers in a first memory, and (ii) outputs a predetermined switching permission signal at a time when a data access for one of the plurality of buffers is completed. The communication processing device also includes a second memory and a transmission destination switching circuit. The second memory includes a plurality of alternative buffers corresponding to the plurality of buffers. The transmission destination switching circuit switches a transmission destination of the access request from one of the plurality of buffers in the first memory to one of the plurality of alternative buffers in the second memory, based on the switching permission signal.

Abstract: Provided are a method for selecting a path comprising ports on primary and secondary clusters to use to transmit data at a primary volume to a secondary volume. A request is received to copy data from a primary storage location to a secondary storage location. A determination is made from a plurality of primary clusters of an owner primary cluster for the primary storage location, wherein the primary clusters are configured to access the primary storage location. A determination is made as to whether there is at least one port on the owner primary cluster providing an available path to the secondary storage location. One port on the owner primary cluster is selected to use to copy the data to the secondary storage location in response to determining that there is at least one port on the owner primary cluster available to transmit to the secondary storage location.

Abstract: An interface for implementing a loopback configuration which offers improved calibration and/or testing of an electronic system is disclosed. More specifically, embodiments provide a bi-directional interface with at least two portions or partitions capable of communicating data in opposite directions and implementing a loopback configuration between components of an electronic system, thereby enabling more flexible, efficient and effective calibration and/or testing of the electronic system using a single interface. The loopback of the partitioned bi-directional interface may be used to perform data link training and/or electronic system testing. In one embodiment, the loopback configuration of the interface may be reversible. Additionally, the looped or coupled end of the partitions may be switched from one component to another, thereby reversing the configuration of the loopback in one embodiment.

Abstract: Techniques herein include systems and methods for driver-assisted BAR mapping that virtualize PCI functions, but without virtualizing the storage media itself. Such techniques make use of unused BARs (Base Address Registers) of a master (Operating system-facing) device to gain access to other PCIe logical instances, while still exposing only a single PCIe function (connection or channel) to system software. This technique provides a new concept of logical PCIe device instances through BAR mapping by making use of unused BARs to extend access to any number of PCIe instances or memory-mapped I/O devices behind a master device such that only a single PCIe function is exposed to system software. Embodiments can thus extend access to one or more additional storage devices through one level of BAR indirection. As a result, such techniques and embodiments enable the multiplication of storage capacity and performance through the aggregation of multiple, similar hardware components.