Abstract: First and second networks, for example Controller Area Networks (CANs), of different physical layers are interfaced by applying signals of the busses of the two networks to respective transceivers. A dominant state of one of the busses is sensed and data is transferred between the two transceivers in a direction from the dominant bus. The two busses are interfaced by a logic circuit interposed between the transceivers. A control circuit is coupled to the first and second logic units for mutually exclusively activating and deactivating the first and second logic units to control the direction of data transfer between the busses.

Abstract: A hardware-based offload engine is disclosed for mapping protected data into frames. For a write operation, the HBA determines host addresses and the size of data to be read from those addresses. The HBA also determines the frame size and protection scheme for data to be written. A frame transmit engine reads each host descriptor in the host data descriptor list to determine the location and byte count of the data to be read. A DMA engine reads the protection information/scratch area to determine the exact data size used to fill each frame and the protection scheme, and retrieves one or more free frame buffers. Check bytes are inserted alongside the data and stored in free frame buffers. After each frame is filled, the frame transmit engine also generates and stores header information for that frame, and then combines header, data and check bytes for transmission over the network.

Abstract: A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes interconnect logic that couples the processing unit to one or more of the plurality of communication links and an originating master coupled to the interconnect logic. The originating master originates an operation by issuing a write-type request on at least one of the one or more communication links, receives from a snooper in the data processing system a destination tag identifying a route to the snooper, and, responsive to receipt of the combined response and the destination tag, initiates a data transfer including a data payload and a data tag identifying the route provided within the destination tag.

Abstract: A memory device containing data to be protected is integrated with a microprocessor and includes a first and a second memory portion with different accessibilities. The integration of the memory device on the same integrated circuit (IC) or chip as the microprocessor permits a combination of protective hardware and software measures that are not possible with a memory device that is on a different IC than the microprocessor. The first memory portion holds an initialization program that also serves as a boot program during decryption, and the second memory portion holds a user program, for example, a program for decrypting and/or decoding received data. Such data may be, for example, audio data encoded according to the MP3 standard and encrypted with a secret or public password against unauthorized reception.

Abstract: A data transfer interface system is provided that directly transfers data from one data storage drive to another data storage drive under the control of a host. The host and data storage drives are jointly connected to one another with data lines and control lines. Each data storage drive is connected separately to the host with a read/write command line. The host initializes the data storage drives providing initialization data to the drives where the data may include position information and commend information. After initialization, the host concurrently instructs one data storage drive to read the data from the drive while the other data storage drive writes the data to memory.

Abstract: A semiconductor device and data transfer method capable of efficient DMA transfer processing. The device comprises: a sector buffer which temporarily stores data during transfer, the buffer having an I/O port used for DMA transfer with a system bus and having an I/O port used for data transfer with the I/O controller; a switching section which switches whether to connect between the system bus and the I/O controller, or to connect between the sector buffer and the I/O controller or the system bus; and a sector buffer controller which separately starts data transfer through the I/O ports and which, when detecting completion of the data transfer of a transfer unit between the sector buffer and the I/O controller, transmits to the switching section a control signal for cutting off data transfer between the sector buffer and the I/O controller and for connecting the system bus and the I/O controller.

Abstract: According to one embodiment, a storage apparatus configured to connect to other apparatus through a communication interface, includes: a memory device; an analysis object data writing module configured to write, when a predetermined event occurs, analysis object data corresponding to the event in the memory device; a response data generator configured to generate response data corresponding to a request input through the communication interface; and a data output module configured to output the response data through the communication interface when the response data exist, and output the analysis object data stored in the memory device through the communication interface by using a non-transmission time interval of the response data.

Abstract: A target interface system for flexibly routing and timing communication signals exchanged between selected components of a communication system and methods for manufacturing and using same. Under the control of a host system, the target interface system samples an output data signal provided by the host system and includes a reconfigurable datapath for flexibly routing the sampled data signal to a selected target I/O pin of the target interface system. The selected target I/O pin provides the sampled data signal as an outgoing target data signal to a target system and likewise receives an incoming target data signal from the target system. Upon sampling the incoming target data signal, the target interface system flexibly routes the sampled data signal to the host system as an input data signal. The target interface system thereby facilitates exchanges of communication signals between the host system and the target system.

Abstract: An effective method for securing the release of the transmission, rendering, and outputting of an imaging/print job at an imaging device, for imaging/print jobs that originate in traditional print/spooling subsystems include the following steps. A print job header is associated with an imaging/print job to form a headed imaging/print job. A secured release input (that may be input at a secured release input apparatus of the client host device) is associated with the print job header by including a secured release indicative command/code in the print job header. The headed imaging/print job is divided into data packets. Initial data packet(s) are transmitted to the imaging device. It is determined whether the secured release indicative command/code is present in the initial data packet(s). Acceptance of subsequent data packets of the headed imaging/print job are prevented if the secured release indicative command/code is present in the initial data packet(s).

Abstract: An industrial controller includes a processing unit and a memory. The industrial controller is operable to communicate using an optimized connection packet including I/O data from a plurality of I/O modules arranged as an unstructured data block. The processing unit is operable to operate on the I/O data within the optimized connection packet to control a process. The memory is operable to store a plurality of cast tags. Each cast tag is associated with one of the I/O modules and provides a logical reference to a subset of the unformatted data block including at least a portion of the I/O data for the associated I/O module.

Abstract: Upon reception of data via a first communication device, a unit connects the first communication device with a storage unit to store the data to be transferred and, after completion of data reception, the unit switches connections of the storage unit to a second communication device and transmits the stored data to the second communication device.

Abstract: Device, system, and method of utilizing PCI Express packets having modified headers. For example, an apparatus includes a credit-based flow control interconnect device to generate a credit-based flow control interconnect Transaction Layer Packet in which one or more bits of an ID field carry non-ID data.

Abstract: A method and system that allows a host system application to securely communicate with a legacy device is provided. A redirector software module receives data that is destined for a host system serial COM port. Data is secured and re-directed to a legacy device via a network port instead of the serial COM port. Conversely, data destined for the host system is provided to a device server via a server COM port by the legacy serial device. The data can be encrypted and sent to the host system via the network. The redirector software module decrypts the encrypted data and presents it to the consumer application as if the data had arrived via the local COM port.

Abstract: A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.

Abstract: Methods and systems for automatically and dynamically identifying capabilities of devices connected to a storage system controller port and setting operating parameters of that port are described. In particular, a storage system controller administers scanning and probing functions to determine capabilities of devices connected to a given port. Based on the determined capabilities of all or a subset of the devices connected to that port, an operating parameter is assigned to that port.

Abstract: There is provided the first storage unit for storing original data, and the second storage unit for storing meta-data. Under the control of a path control unit, an optimal connection process can be performed. As a result, a stream from the first storage unit for storing the original data can always be transmitted at maximum.

Abstract: A method, system, and computer-usable medium for coupling a collection of devices to a bridge, wherein the collection of devices includes high-performance devices and low-performance devices, coupling a data bus to the bridge, utilizing a collection of transfer credits to allow transfer of commands to the collection of devices, transferring commands to the collection of devices only when at least one transfer credit is available, and in response to determining a number of transfer credits falls below a predetermined threshold, utilizing a command arbitration scheme that gives priority to commands to the high-performance devices among the collection of devices.

Abstract: Methods and systems for a low noise amplifier with tolerance to large inputs are disclosed and may include generating at least one control signal that controls a plurality of directional modes of at least one contact pad on a mobile multimedia processor (MMP) in an integrated circuit. Selectable modes may include: bidirectional, input, and an output mode. Each of the modes includes a bypass mode and a processing mode that may be controlled by the generated control signal. Received data may be processed by circuitry in the MMP when the processing mode may be enabled. Received data may be passed through the MMP without being processed by the MMP when the bypass mode may be enabled. An additional signal may be generated to dynamically pull-down a potential of the at least one contact pad and/or to pull-up a potential of said at least one contact pad.

Abstract: A personal video recorder (PVR) (10) comprises a receiving stage (12) which receives media content and an internal storage device (24) such as a hard-disk. The PVR has an interface (26) for connecting to an external storage device (30). The PVR is operable to receive an instruction to record content directly to the external storage device (30). The PVR determines if the external storage device (30) can store the media content at a required transfer rate. If the external storage device (30) is unable to store the media content at the required rate, it uses the internal storage device (24) to record the received media content and to transfer the stored media content from the internal storage device (24) to the external storage device (30). The achievable transfer rate can be determined once transfer has commenced.

Abstract: A Small Computer System Interface (SCSI) input/output (I/O) coordinator of an apparatus in an example caches in memory local to the SCSI I/O coordinator one or more I/O request contexts stored in memory non-local to the SCSI I/O coordinator.

Abstract: In a DVD playback mode only, the first type interface is disabled and a DVD driver unit having a hardware DVD decoder connected to a DVD reader unit arranged to read video data from a DVD inserted therein is powered on. In the described embodiment, the DVD decoder unit is also connected to the display screen by way of a second type interface is powered on. The video data is read from the DVD by the DVD reader unit and sent by the DVD reader unit to the hardware DVD decoder unit which then decodes the video data before passing it directly to a timing controller unit coupled to the display screen by way of the second type interface. The timing controller unit converts the video data at a native resolution to a display screen resolution that is then displayed on the display screen.

Abstract: A bus station in the form of a hardware dongle, operates in conjunction with a USB Device running suitable software. When the bus station determines that a bus host is connected to a first bus communication port thereof, it acts as a transceiver to allow conventional bus communications between said bus host and a bus device connected to a second bus communication port thereof. When the bus station determines that a bus device running suitable software is connected to the first bus communication port thereof, it acts as an alternate host to allow bus communications between said bus device connected to the first bus communication port and a bus device connected to a second bus communication port.

Abstract: A system for coordination for quality of service in multi-layer storage virtualization environments includes a first, second and third storage entity at a respective first, second and third layer of virtualized storage. The first storage entity sends a request for an I/O task to the second storage entity. In response to the request, the second storage entity may be configured to cooperate with the third storage entity to perform one or more I/O operations to satisfy one or more quality of service requirements associated with the I/O task.

Abstract: An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including compressing/decompressing the data transferred to and from the disk. An improved decoder is also provided that reduces the number of bounds checks needed on average for typical compressed data by first guaranteeing that there is sufficient room to decode literals and small substrings, whereby bounds checking is not needed. A combination hibernation mode and a suspend mode is also provided that essentially maintains power to the RAM while transparently backing the RAM with the hibernation file, such that if power to the RAM is interrupted, the RAM contents are automatically restored from the hibernation file when power is restored.

Abstract: A method involves generating a block-level write operation, which causes a value to be written to a primary volume, and generating information indicative of whether any of the block-level write operation should be transferred to a secondary site during replication of data in the primary volume. The information can indicate that all, part, or none of the block-level write operation should be transferred to the secondary site. If the information indicates that less than all of the block-level write operation should be transferred to a secondary site, the information can also indicate that logical information associated with the block-level write operation should be transferred to the secondary site instead of transferring the value being written by the block-level write operation.

Abstract: A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list of processes to perform on the packet of data and an ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes.

Abstract: A system employing asymmetric distributed block virtualization includes a volume server, a plurality of volume clients, and one or more physical block devices. The volume server aggregates storage in the physical block devices into a logical volume and makes the logical volume accessible to the volume clients for input/output (I/O) operations. In order to manage different I/O access requirements (such as read-only access versus read-write access) of the volume clients, the volume server maintains a different I/O access policy for each volume client to control the kinds of input/output operations that the volume client is allowed to perform on the logical volume.

Abstract: This invention is a system and method for managing one or more data storage networks using a new architecture.

Abstract: This invention is a system and method for managing one or more data storage networks using a new architecture.

Abstract: An image capture device has a first image transfer method for storing a captured digital image on a storage medium and transferring the digital image to a communication device, and a second image transfer method for storing the digital image on the storage medium, reading the digital image from the storage medium and then transferring the digital image to the communication device. The first image transfer method or the second image transfer method is manually or automatically set.

Abstract: A computer program product for managing connections comprises a computer readable storage medium having the following computer instructions. The instructions cause a controller to perform: outputting an image including icons representing respective devices connected to an IEEE 1394 serial bus to display means; and establishing a logical connection between two of the connected devices by updating the contents of iPCR and oPCR stored in register spaces in the two connected devices and updating data for management of a band and a channel that is stored in a register space provided in an isochronous resource manager, which is a node for isochronous resource management on the IEEE 1394 serial bus, when a user enters a selection of the two connected devices to be logically connected to each other from among the connected devices on the bus.

Abstract: Systems, devices, and methods, including logic and/or executable instructions are described in connection with a buffer circuit. One buffer circuit includes a flip-flop based first-in first-out (FIFO) buffer having an input and an output, selection logic coupled in series with the FIFO buffer input, and a random access memory (RAM) FIFO coupled in parallel with the selection logic. The selection logic diverts incoming data to the RAM FIFO after the FIFO buffer is filled to a first capacity level, and reloads the FIFO buffer using data from the RAM FIFO until the RAM FIFO is emptied to a second capacity level. Data is extracted without read data latency from the output of the FIFO buffer as an output of the buffer circuit.

Abstract: A peripheral interface and process for data transfer, especially for laser scanning microscopes. The peripheral interface permits a gap-free transfer of data with high transmission speed at low cost and using a non-real-time-enabled operating system of the control computer. In a peripheral interface having a connection for a system bus of a control computer, a peripheral connection for a peripheral device and a control unit serving for one-way transmission of a predetermined amount of data from the control computer to the peripheral device and/or vice versa accesses via the system bus, a work memory region of the control computer serves as buffers preassigned to it, where the control unit prepares for the control computer a progress report of the transfer for retrieval and the control unit of the control computer is informed of the progress of the processing of the buffer independently of the transfer, in which case it allows for the progress of the processing when accessing the buffer.

Abstract: An integrated data accessing system having control apparatus for multi-directional data transmission is described. The integrated data accessing system includes a control apparatus, a plurality of communication interface engines. The control apparatus includes a plurality of bi-directional transmission modules, a control unit, a multi-directional transferring engine, and a memory unit. The control unit detects a source storage and a target storage. The multi-directional transferring engine selectively transfers the data content among storage units. The multi-directional transferring engine includes a first switch module, a second switch module, and a data buffer. The first switch module switches to the first bi-directional transmission module to select the source storage. The second switch module switches to the second bi-directional transmission module to select the target storage. The data buffer stores the data content transmitted from the source storage and the target storage.

Abstract: Provided is a computer system which includes computers and a storage system coupled to the computers. The storage system includes a first load measuring module that measures a first access load for each channel adaptor. At least one of the computers includes a path management module that manages paths through which the computers access logical units. The path management module includes a second load measuring module that measures a second access load imposed by access from the computer to the logical unit, and an active path setting module that selects one of the channel adaptors based on the first access and the second access load measured by the first and second load measuring modules, and setting an active path passing through the channel adaptor. Thus, a load on an entire system is balanced, thereby improving performance while a cache hit rate of a storage system is maintained.

Abstract: A controller system with programmable bi-directional input/output terminals includes a micro controller, a terminal block and an interface unit connected between the micro controller and the terminal block. The interface unit includes a predetermined number of uni-directional input terminals, a predetermined number of uni-directional output terminals, and a predetermined number of bi-directional terminals. The micro controller can selectively set the bi-direction terminals as input terminals or output terminals according to an ID signal from the interface unit or a user parameter. Therefore, the number of input/output terminals for the controller system can be flexibly adjusted.

Abstract: A flexible printing subsystem is enabled with a printer filter pipeline. A configurable and arbitrary number of printer filters forming a printer filter pipeline are applied to files that are to be printed. In a described implementation, the printer filter pipeline may implement enhancement features and conversion functions as determined by the individual printer filters forming the printer filter pipeline. The printer filter pipeline is established in accordance with a printer filter configuration file. The printer filter configuration file stipulates a printer filter order and includes a printer filter entry associated with each printer filter to be part of the printer filter pipeline. Each printer filter entry identifies the associated printer filter by name and enumerates the interfaces thereof. Printer filters may be adjacently linked in a printer filter pipeline when their mating interfaces match.

Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

Abstract: A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.

Abstract: A device, a method and a system for portable data storage and transfer through a simplified device interface. The operations of the device are restricted, in order to increase the ease of use of the device, and in order to provide certain core functions. These core functions include reading data, writing data and exchanging data with a similar device and/or with an external computer. The device features a minimal set of hardware components for accomplishing these functions, such as a data processor of some type, a memory storage medium or media, and a data exchange mechanism, which may optionally be an infrared port for example.

Abstract: A method for remotely communicating with a computer system in a headless environment is provided. The system includes a service processor in communication with a computer through a UART communication channel and in communication with a remote console through a communication connection. The service processor manages communication commands between the computer and the remote console. The service processor transmits data communication received from the remote console to the computer through the UART channel, and the service processor transmits data communication received from the computer to the remote console through the UART channel. In addition, a multiplexer may be employed to direct communication between one of a plurality of computers and the service processor in combination with a multiplexer control to select one of the computers for communication with the service processor. The multiplexer directs the communication through the UART channel.

Abstract: The invention relates to design optimization of microprocessors using spare driver outputs for discrete input interfaces. An output driver or pre-FET driver is used to interface a discrete input for a microprocessor. To read the discrete interface, a fault detection mechanism of the pre-FET driver or the output driver is used. Monitoring the fault register of the output driver allows the condition of the external switch to be understood. The circuit is able to read either a switched to battery type interface or a switched to ground type interface, thereby eliminating hardware proliferation. The fault register is read through a serial peripheral interface (SPI) bus, thereby removing the need for a dedicated microprocessor pin required for the interface. Toggling the gate in the pre-FET driver interface permits adding diagnostic capability for the discrete input interface.

Abstract: A method, computer program product, and system are provided for transmitting data in a data network. A first processor of the data network receives data to be transmitted to a second processor within the data network. A determination is made if the data has previously been routed through an indirect communication link from a source processor, the indirect communication link being a communication link that does not directly couple the source processor to a final destination processor which is to receive the data. A communication link is selected over which to transmit the data from the first processor to the second processor based on results of determining if the data has previously been routed through an indirect communication link. Finally, the data is transmitted from the first processor to the second processor using the selected communication link.

Abstract: A computer management apparatus is provided for interconnecting a single user console including user interface devices, such as a console keyboard, a console video display unit, a console mouse, and speakers for connecting to a plurality of host computers, thereby allowing the user to access one or more of the host computers from the user console. In one embodiment, the user may easily switch between the host computers by use of an RF wireless remote control device that activates a switching circuit contained within the body of the computer management apparatus. The cables utilized with the apparatus and the device indicator on the remote control device are color coded for easy hook-up and identification of the host computer selected with the remote control device to activate the switching circuit.

Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Abstract: Methods and systems for virtualization and re-direction of I/O connections to peripheral devices are disclosed. Aspects of one method may include virtualizing one or more peripheral devices via corresponding PCI/PCIe level functions. The virtualization may comprise, for example, emulating peripheral device controllers. The PCI and/or PCIe level functions may then redirect accesses to peripheral devices to corresponding virtual devices. Since a PCI/PCIe level function may emulate a peripheral device controller, the redirecting may occur without modifying an operating system for the electronic system or the corresponding device driver used to access the peripheral device. Accordingly, virtualization and redirection may enable controlling a remote electronic system over a network. The controlling of a remote electronic system may comprise, for example, storing and accessing data in a remote storage device, booting from the remote storage device, and scanning and/or printing at the remote device.

Abstract: A method and system of simplified configuration of a network element. A network element having a direct access module and an arbitrary unknown address is coupled to a same physical subnet as a management node. The management node broadcasts a discovery broadcast to identify the existence of the network element. If a response is received indicating an address outside an access range of the management node, it sends an additional broadcast targeted to the network element force the network element to change its address to one within an access range of the management node. Once the address is changed, the management node may connect to and configure the network element using standard protocols.

Abstract: An interface between USB devices employs isolation techniques to provide electrical isolation of a USB signal for transmission of the USB signal between the devices. Unidirectional isolator channels are utilized to transmit the USB signals, and a selection of an isolator channel operating in an intended direction is performed by either direction control logic or a USB hub function. Logic may be employed to detect a device attempting to initiate a USB signal. The logic operates to enable a transmitter on a receiving side and isolate the USB signal through an isolator channel operating in a transmission direction.

Abstract: In an apparatus and method for providing device sharing, a first plurality of upstream ports are each connectable to a respective host and at least one downstream port is connectable to a device. A virtual port is defined that is associated a routing table to effect device virtualization by redirection of information packets received by the virtual port.

Abstract: An apparatus for linking a hot-plug device to a host includes a slave interface circuit for connection to the host; a master interface circuit for connection to the hot-plug device; and direction, data, and clock lines that link the master and slave interface circuits. A control logic circuit detects a Presence Detect signal on the direction line. A method of determining a connection between a host and a hot-plug device includes asserting a direction signal on a direction line to control a direction of a flow of data between the host and the hot-plug device; toggling the direction signal to indicate a presence of the hot-plug device; and indicating a disconnect after a given period of inactivity in the toggling. A method of linking a host and a hot-plug device interface circuit for connection to a hot-plug device includes asserting a Presence Detect signal on the direction line.