Abstract: Techniques herein include systems and methods for driver-assisted BAR mapping that virtualize PCI functions, but without virtualizing the storage media itself. Such techniques make use of unused BARs (Base Address Registers) of a master (Operating system-facing) device to gain access to other PCIe logical instances, while still exposing only a single PCIe function (connection or channel) to system software. This technique provides a new concept of logical PCIe device instances through BAR mapping by making use of unused BARs to extend access to any number of PCIe instances or memory-mapped I/O devices behind a master device such that only a single PCIe function is exposed to system software. Embodiments can thus extend access to one or more additional storage devices through one level of BAR indirection. As a result, such techniques and embodiments enable the multiplication of storage capacity and performance through the aggregation of multiple, similar hardware components.

Abstract: Systems, methods, and apparatus for facilitating communications between an external controller and Fieldbus devices are described. A primary linking device in communication with the controller and one or more Fieldbus devices may be configured to direct the communication of a timing message to the controller and determine whether a response to the timing message has been received from the controller. Based upon the determination, the primary linking device may direct a switching of communications control to a secondary linking device.

Abstract: Described are techniques for processing requests. A request is received at a data storage system. The request is a command to perform first processing and the request is sent from a client over a virtualized path. The virtualized path includes a virtual target port of the data storage system. The virtual target port is a first physical target port that provides a virtualized counterpart port for a second physical target port whereby requests directed to the second physical target port are routed to the first physical target port rather than the second physical target port. First processing is performed and a response to the request is generated. The response includes first information consistent with sending the request over a non-virtualized path to the second physical target port. The response is sent to the client.

Abstract: A serial data transfer apparatus includes a transport controller that performs a process of a transport layer, a link controller that performs a process of a link layer, and a physical layer circuit that performs a process of a physical layer. The serial data transfer apparatus transmits and receives data with a destination apparatus via a serial bus. The link controller outputs idle data, which is received from the destination apparatus, to the physical layer circuit, and stops to operate of a unit responsible for generating data to transmit to the destination apparatus while outputting the idle data to the physical layer circuit. This enables to output idle data defined in the standard in an idle period of the serial data transfer apparatus and also reduce the power consumption.

Abstract: A relay apparatus in a print system in which a print server, the relay apparatus, and a plurality of print apparatuses are connected to a network, and which performs print processing, comprises: a search unit configured to search for a print apparatus with which the relay apparatus can communicate; a sending unit configured to send, to the print server, pieces of information of the relay apparatus and the print apparatus found by the search unit; and a relay unit configured to receive a print instruction that is issued by the print server and includes location information of document data to be printed and information of a print apparatus used to perform print processing, to download the document data based on the location information included in the print instruction, and to send both the print instruction and the downloaded document data to the print apparatus designated by the print instruction.

Abstract: A data processing system 100 comprising a monitor 120 is provided and corresponding system-on-chip, method for monitoring and computer program product. The data processing system comprises multiple processing devices 104, 106, 116, 116 and a monitor 120. The monitor is configured to monitor characteristics of the data streams 102, 112, occurring among the plurality of data processing devices. The monitor comprises a means to determine whether a system characteristic substantially deviates from an expected system characteristic and to raise an anomaly signal if so. The system characteristic depends on the first characteristic and the second characteristic. In this way the monitor increases robustness by monitoring for problems related to deviations in the relation between multiple data streams.

Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.

Abstract: Embodiments related to switching of data packets have been described.

Abstract: For the transmission of a telegram from the control device to the peripheral element an intermediate device receives the telegram from the control device and forwards it without amendment to the peripheral element. For the transmission of a telegram from the peripheral element to the control device the intermediate device receives the telegram from the peripheral element and forwards it without amendment to the control device. The telegrams are safety telegrams, so that telegrams forwarded to the control device or to the peripheral element from the respective receiving unit can be checked for freedom from errors.

Abstract: According to one embodiment, a cable includes a first plug and a second plug, a voltage application line which is formed by a metal wire connected between the first plug and the second plug, and to which a voltage is applied from one of the first plug and the second plug, a plurality of optical fibers which are connected between the first plug and the second plug, and transmit a video signal, and a controller connected to the voltage application line, and configured to detect a transmission direction of the video signal between the first plug and the second plug by sensing a change in voltage of the voltage application line and perform processing in accordance with the detected transmission direction.

Abstract: An information processing apparatus and method for controlling printing, the apparatus and method including acquiring printing apparatus identification information for identifying a printing apparatus from a removable medium connected to the information processing apparatus, producing print data to be printed by the printing apparatus using a printer driver compatible with the printing apparatus identified by the printing apparatus identification information, storing the print data produced by the print data production unit on the removable medium.

Abstract: Auto-trespass can be at least temporarily disabled subsequent to an automatic failover. The automatic failover exchanges roles between an active path and a passive path, such that the passive path becomes the active path and vice versa. By disabling auto-trespass, hosts that are unaware that the automatic failover has occurred will not trigger another failover when those hosts attempt to perform I/O operations via the formerly-active path. This can reduce performance decreases that would otherwise occur due to the active role being traded in a “ping-pong” manner between the paths.

Abstract: A transmitting section 7a outputs a transmission signal to the side of a transmission line 1. A first switching section Qa1 outputs the transmission signal to the transmission line 1. A second switching section Qa2 outputs the transmission signal from the transmission line 1. A receiving section 9a receives the transmission signal from the transmission line 1. A first detecting section 13a detects the transmission signal flowing through the first switching section Qa1. A second detecting section 19a detects the transmission signal flowing through the second switching section Qa2. When the transmission signal from the transmitting section 7a is not detected at both the first and second detecting sections 13a and 19a, a selecting section 15a selects the receiving section 9a and outputs a reception signal.

Abstract: In a computer system configured to handle I/O signals received by the computer system from input devices and/or output signals output by the computer system, a virtual attachment module includes logic for selecting such that program code for coupling can alter the operating system's selection of I/O devices used for particular I/O device operations, coupling to a wireless I/O device at least for determining whether the wireless I/O device is available, and causing redirection of I/O signals destined to a default I/O device to be to the wireless I/O device, if the program code for coupling determines that the wireless I/O device is available. A virtual connection module could be used to intercept system messages indicating a wireless device is present and connected, determine whether the wireless device is present and/or connected, and determine which intercepted messages to forward, drop, delay or reformulate.

Abstract: This invention relates to methods and apparatus for providing a resilient network database. The invention relates particularly, but not exclusively, to the IP Multimedia Subsystem (IMS). The invention is directed to an interface for a database node comprising: a port for receiving a request for information from a network node; a processor for determining if the database node can respond to said request; and a transmitter for forwarding the request to another database node if the particular database node cannot respond. The invention is also directed to a distributed database comprising a number of database nodes, wherein a request received by one node is forwarded to other nodes in the distributed database if the particular node cannot handle the request.

Abstract: To inhibit the occurrence of communication failures in the system in which a secondary storage control apparatus acquires journal data from a primary storage control apparatus and writes the data to a secondary volume. The primary storage control apparatus comprises a command processing unit, a journal data creation unit, a journal data transfer unit which reads journal data to the secondary storage control apparatus, and a transfer control unit. In specified occasions, the transfer control unit controls at least either one of the journal data transfer amount by the journal data transfer unit and the width of the communication band utilized for journal data transfer.

Abstract: A computer-implemented method for creating incremental images of cluster volumes. The method may include 1) maintaining a parallel cluster comprising a plurality of cluster nodes connected to a cluster volume; 2) creating a first incremental image of the cluster volume by capturing changes to the cluster volume on a first mirror during a first period of time; 3) for each cluster node in the parallel cluster, blocking write completions for writes to the cluster volume; 4) while the write completions are blocked, switching to a second mirror to create a second incremental image of the cluster volume by capturing changes to the cluster volume on the second mirror during a second period of time; and 5) after switching to the second mirror, unblocking the write completions for writes to the cluster volume. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining information of the processor complex responsive to the first write request, and transmitting a second write request from the processor complex to the peripheral device including the information. Other embodiments are described and claimed.

Abstract: A method to improve a solid state disk performance by using a programmable bus arbiter is generally presented. In this regard, in one embodiment, a method is introduced comprising delaying a request from a solid state drive for access to an interface for a time to allow a host to access the interface to transmit a command to the solid state drive. Other embodiments are described and claimed.

Abstract: An electronic device includes a response-request transmitting unit and a response receiving unit. The response-request transmitting unit transmits a response request including an identifier of the response-request transmitting unit on a second network to an external device through a first net work. The response receiving unit that receives a response including an identifier of the external device on the first network, transmitted through the second network in response to the response request.

Abstract: In one embodiment, a computer-implemented method for creating redundant system configurations is presented. The computer-implemented method creates a set of virtual function path authorization tables, and receives a request from a requester to provide requested data from a virtual function wherein the virtual function is performed by a single root or a multi-root peripheral component interconnect device. Further a receive buffer is created in a selected address range in a set of addresses ranges as well as a virtual function work queue entry for the virtual function containing an address of the receive buffer in the selected address range. Responsive to a determination that the virtual function is authorized, writing the requested data into the receive buffer of the selected address range in the one or more systems, and responsive to writing the requested data, issuing a notice of completion to the requester.

Abstract: Disclosed here is a semiconductor memory device including: a semiconductor substrate; a plurality of pads formed on the semiconductor substrate and configured to permit data input and output; and a memory core block and an I/O block integrated on the semiconductor substrate. The data items are input and output to and from the plurality of pads at twice a maximum access rate in effect.

Abstract: In some embodiments a Universal Serial Bus cable includes a first differential pair to transmit bus signals, and a second differential pair to transmit bus signals in a same direction as the bus signals transmitted by the first differential pair. In this manner, a bandwidth of the Universal Serial Bus cable is doubled in that same direction. Other embodiments are described and claimed.

Abstract: Skip based control logic for first in first out buffer is disclosed. In one embodiment, a host controller interface (HCI) device includes an isochronous receive first in first out (IRFIFO) buffer. The IRFIFO buffer includes a storage for storing an isochronous data packet received from a guest device. Further, the IRFIFO buffer includes a write pointer for pointing to a write address of the storage for a write operation. Furthermore, the IRFIFO buffer includes a read pointer for pointing to a read address of the storage for a read operation. In addition, the IRFIFO includes a control logic for incrementing the read pointer by a value of a skip parameter of a skip register if the isochronous data packet is not valid for the read operation.

Abstract: Skip based control logic for first in first out buffer is disclosed. In one embodiment, an isochronous data packet placed in an isochronous receive first in first out (IRFIFO) buffer coupled to an isochronous receive direct memory access (IRDMA) is detected. Further, a header of the isochronous data packet is read. Furthermore, a validity of the isochronous data packet is determined. Also, a read operation of remaining data of the isochronous data packet is skipped if the isochronous data packet is determined as invalid.

Abstract: A storage system provides virtual ports, and is able to transfer the virtual ports among physical ports located on multiple storage control units making up the storage system. The storage system is able to manage logical volumes and/or virtual volumes and virtual ports as a group when considering whether to move logical/virtual volumes and/or virtual ports to another storage control unit in the storage system. When the storage system is instructed to transfer volumes, virtual ports, or a group of volumes and virtual ports among the storage control units, the storage system determines whether an inter-unit network will be required to be used following the transfer. When the storage system determines that the inter-unit network will be required if the transfer takes place, the storage system determines and presents an alternate storage control unit for the transfer to avoid use of the inter-unit network, thereby avoiding degraded performance.

Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.

Abstract: A data transmission method and the transmission circuit thereof for transmitting data between a host and a peripheral apparatus are disclosed. The data transmission method includes the following steps. First, a clock signal is transmitted by a first pin. Then, a data signal is transmitted by a second pin according to the timing of the clock signal.

Abstract: A recording and/or reproducing apparatus includes a plurality of devices in which a first device has a connecting unit connected with a host device to perform a data transfer with the host device, a second device shares a temporarily recording area with the first device to perform the data transfer between the first and second devices via the temporarily recording area, and the data transfer is performed by using the temporarily recording area shared with the first device and using the connecting unit of the first device when the second device performs the data transfer with the host device, in this way, a power consumption is reduced.

Abstract: A data storage device is provided, including a first data storage device electrically storing write data, a second data storage device magnetically storing write data, and a controller partitioning write data into first and second write data portions. The first write data portion is programmed to the first data storage device and the second write data portion if magnetically written to the second data storage device at the same time.

Abstract: A hybrid serial peripheral interface (SPI) data transmission architecture adapted in a network device for connecting a host and a network is provided. The architecture comprises a RX buffer and RX SPI for maintaining a data receiving process, a TX buffer and TX SPI for maintaining a data transmission process, a configuration and status register and a hybrid SPI processing module. The hybrid SPI processing module makes the RX SPI performs the data transmission process as well when the RX SPI idles and the data transmission process proceeds at the same time and makes the TX SPI to performs the data receiving process as well when the TX SPI idles and the data receiving process proceeds at the same time. A hybrid SPI data transmission method is disclosed herein as well.

Abstract: A two-way connectivity USB control device and its operation method are disclosed. The present invention solves a problem of the prior art that requires users to manually switch a USB controller between an active mode and a passive mode and set a predetermined time interval as in prior art. The two-way connectivity USB control device detects whether or not there is a voltage input. If the detection result is yes, then the two-way connectivity USB control device is switched to a transmit mode, or else the two-way connectivity USB control device is switched to a transparent mode for accessing data stored in an external device by issuing a control command directly.

Abstract: A first node includes a DMA engine for transferring data specified by a sequence of control blocks to a second node. When a control block does not require synchronization between memories, the DMA engine sends an end of transfer (EOT) message after the last datum, increments an EOT counter, and processes the next control block. When a control block requires synchronization and the EOT counter is at zero, the DMA engine sends an EOT with a flag after the last datum, increments the EOT counter, and waits for the EOT counter to return to zero before processing the next control block. A memory controller at the second node detects the EOT with or without a flag and generates an EOT acknowledgement with or without a flag. When a link interface at the second node detects the EOT acknowledgement with a flag, it sends an interrupt to a local processor complex.

Abstract: Method and apparatus for inter-IC communication are described. In some examples, an integrated circuit (IC) includes core circuitry configured to process input data and provide output data; input/output (IO) circuitry configured to receive the input data, and transmit the output data; a control circuit configured to provide a selection signal; and an inter-IC communication port coupled between the core circuitry and the IO circuitry and configured to pass the input data and the output data, the inter-IC communication port having a memory interface and a memory controller, the inter-IC communication port configured to selectively couple either the memory interface or the memory controller between the core circuitry and the IO circuitry responsive to the selection signal.

Abstract: The present invention relates to a method for data transfer between a host and a device as well as to respective apparatus. A host is seen as a communication apparatus which organizes data traffic. A device is seen as dependent on the host. In a tiered-star topology there are usually multiple devices connected to one host. A method for data transfer between a host and a device through pipes is presented. The available memory in the host is divided into multiple segments. The assignment of segments is changed between pipes in dependence on the pipe traffic.

Abstract: A serial data transfer apparatus includes a transport controller that performs a process of a transport layer, a link controller that performs a process of a link layer, and a physical layer circuit that performs a process of a physical layer. The serial data transfer apparatus transmits and receives data with a destination apparatus via a serial bus. The link controller outputs idle data, which is received from the destination apparatus, to the physical layer circuit, and stops to operate of a unit responsible for generating data to transmit to the destination apparatus while outputting the idle data to the physical layer circuit. This enables to output idle data defined in the standard in an idle period of the serial data transfer apparatus and also reduce the power consumption.

Abstract: A peripheral interface and process for data transfer, especially for laser scanning microscopes. The peripheral interface permits a gap-free transfer of data with high transmission speed using a non-real-time-enabled operating system of the control computer. A peripheral connection for a peripheral device and a control unit serving for one-way transmission of a predetermined amount of data from the control computer to the peripheral device and/or vice versa accesses via a system bus of a control computer, a work memory region of the control computer serves as buffers preassigned to it, where the control unit prepares for the control computer a progress report of the transfer for retrieval and the control unit of the control computer is informed of the progress of the processing of the buffer independently of the transfer.

Abstract: An interface device includes a parallel-to-serial converting unit, a driver, a receiver, and a serial-to-parallel converting unit. The parallel-to-serial converting unit converts parallel signals into a single-ended signal. The driver converts the single-ended signal from the parallel-to-serial converting unit into a differential signal and transmits the differential signal to an external device via signal lines. The receiver converts a differential signal received via the signal lines from an external device into a single-ended signal. The serial-to-parallel converting unit converts the single-ended signal from the receiver into parallel signals. A direction in which the differential signal is to be transmitted is determined based on a control signal.

Abstract: A plurality of registers may function as both the control and status registers. Each bit location of the registers is writable to set a value on a control signal and readable to read a current value on a status signal. A multiplexer provides readability of the current value of each of the registers.

Abstract: Methods and systems for encoding and/or decoding digital signals representing serial attached SCSI (SAS) out of band (OOB) signals exchanged over an optical communication between two SAS devices. A SAS OOB signal to be transmitted from a first SAS device to a second SAS device is first encoded as a digitally encoded signal representing the analog SAS OOB signal and then transmitted over an optical communication medium to another SAS device. A receiving SAS device coupled to an optical communication medium decodes a received digitally encoded signal to detect a received, encoded SAS OOB signal and processes the received SAS OOB signal when receipt is detected. The digitally encoded signal may comprise an idle word portion and a burst word portion to represent various SAS OOB signals. Further, the digitally encoded signal may be precomputed in a variety of disparity forms and stored in a memory for lookup and retrieval.

Abstract: A portable data storage device compatible with both standard and high definition digital video cameras is provided. The device includes at least one SDI I/O, and preferably at least one audio I/O and preferably at least one medium speed I/O interface. A device controller takes the high speed serial data, packetizes it, and then sends it out to a plurality of memory modules. Preferably each memory module includes four NAND clusters, each NAND cluster consisting of a flash memory controller and two NAND flash memories. Interposed between the device controller and the memory modules are a plurality of memory controllers, each memory controller controlling a group of memory modules. A user interface is coupled to the device controller, the interface including a display capable of at least two user-selectable orientations, record/playback controls and a four-way directional control pad.

Abstract: In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining information of the processor complex responsive to the first write request, and transmitting a second write request from the processor complex to the peripheral device including the information. Other embodiments are described and claimed.

Abstract: A computing device includes a communication port, memory resources, and one or more processors. The one or more processors are configured to combine with the memory resources to operate one or more of the plurality of modules. The plurality of modules are operative in order to handle exchange of communications with a primary computer over the communication port. The one or more modules include a first module that is operative in a first communication mode in enabling exchange of communications with the primary computer over the communication port. The exchange of communications causes the primary computer to access and execute one or more autorun files from the computing device. The one or more modules may also include a second module that is operative in a second communication mode to be operative in enabling an alternative function to be performed with or for the primary computer over the communication port.

Abstract: A USB control circuit for increasing USB endpoints includes a token detection circuit. The USB control circuit is configured to receive a first logical endpoint (LEP) address and a USB token. The token detection circuit is configured to determine a direction of a USB data transfer in accordance with a USB token type. The USB control circuit includes an endpoint configuration and status control logic circuit in communication with the token detection circuit. The endpoint configuration and status control logic circuit is configured to control configuration and status information associated with each of a plurality of LEP input buffers and LEP output buffers. The USB control circuit is configured to generate a second LEP address in accordance with a combination of the first LEP address and the determined direction to increase a quantity of LEPs without increasing a quantity of physical endpoint buffers of a USB device.

Abstract: Proposed is technology for shortening the time required for analyzing and processing commands issued from multiple hosts and speeding up the processing. When a controller receives a command including random IO processing and the reception of commands is complete, it determines whether the valid extents prescribed in seek parameters attached to an LOC command overlap, and executes extent exclusive wait processing which causes access to the logical volume to enter a wait state or access processing to the logical volume based on the determination result. If the reception of commands is incomplete, the controller determines whether the access ranges (extents) designated in a DX command overlap, and executes extent exclusive wait processing or access processing to the logical volume based on the determination result.

Abstract: Methods and systems for a low noise amplifier with tolerance to large inputs are disclosed and may include generating at least one control signal that controls a plurality of directional modes of at least one contact pad on a mobile multimedia processor (MMP) in an integrated circuit. Selectable modes may include: bidirectional, input, and an output mode. Each of the modes includes a bypass mode and a processing mode that may be controlled by the generated control signal. Received data may be processed by circuitry in the MMP when the processing mode may be enabled. Received data may be passed through the MMP without being processed by the MMP when the bypass mode may be enabled. An additional signal may be generated to dynamically pull-down a potential of the at least one contact pad and/or to pull-up a potential of said at least one contact pad.

Abstract: A method of transmitting data on a data line between a central control device and a decentralized data processing device. During a normal operation of the system, the central control device periodically sends synchronization pulses to the at least one data processing device via the data line in order to request data packets, and the decentralized data processing device sends the data thereof to be transmitted, as data packets, to the central control device, following the synchronization pulse. The data line is embodied as a data bus. Each of the decentralized data processing devices is configured by the central control device before the first transmission of data packets to the central control device. In order to configure the system, a bi-directional communication is carried out between the central control device and the at least one decentralized data processing device.

Abstract: A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.

Abstract: An interface to transfer data between a host processor and an external coprocessor is provided. The interface may operate in several write modes, in which in a first write mode the write operation is transferred across the interface in two clock cycles and in a second write mode the write operation is transferred across the interface in a single clock cycle. The interface can perform a first read operation initiated by the host processor and a second read operation initiated by the external coprocessor. The interface can include buffers to store read and write operations and clock gates to selectively gate off clock signals provided to the buffers to synchronize transfer of data into and out of the buffers. A selectable priority scheme can be modified to select between priorities that control a preference in transferring operations over the interface when both read and write operations are queued for transfer.

Abstract: A method, article of manufacture, and apparatus for accessing data during data recovery. In some embodiments, this includes sending an I/O request from an application to an object, wherein the object is being recovered, establishing an I/O intercept, intercepting the application's I/O request with the I/O intercept, and redirecting the I/O request based on the status of the object's sub-objects.