Abstract: A method for burst transferring of data in a processing system is provided. The processing system has a data bus width of W bytes (W even) and a cache line length of L bytes (L even). The cache line has L/W banks, the lowermost bank being in an odd position and the uppermost bank being in an even position. In a request for a particular data entity, a series of addresses are issued on the address bus to fill the associated cache line. The first address is always for a particular cache bank to which the particular data entity is mapped. The remaining addresses are sequenced ascending linearly, modulo L. If the particular data entity is mapped to an even cache bank, but not to the uppermost cache bank, then L/W remaining addresses are issued, beginning with the base address of the cache bank immediately following the cache bank to which the particular data entity is mapped.

Abstract: Th present invention coordinates access to a shared resource, comprised of a plurality of segments, between a first device and a second device using an index and count mechanism. The present invention includes a respective descriptor, for each of the plurality of segments. Entries to the respective descriptors of the segments are maintained by the first device to inform the second device of activity between the first device and the shared resource. The present invention also includes a descriptor queue register, coupled to the first device and the second device. The first device writes an index into the descriptor queue register for indicating a starting descriptor of a corresponding segment that is available to the second device for access. The first device also writes a count into the descriptor queue register for indicating a subsequent number of descriptors, from the starting descriptor, of any corresponding segments that are available to the second device for access.

Abstract: A method for transmitting information between each electronic unit, comprising the steps of (a) transmitting information whose amount does not exceed a predetermined data amount, (b) determining whether or not the predetermined data amount is larger than a desired information amount, (c) when the determined result at step (b) is No, transmitting remaining information for the predetermined amount or less, and (d) repeating the steps (a) to (c) until there is no remaining information.

Abstract: A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.

Abstract: A disk drive and a method for controlling the disk drive in which an additional read from a medium can be performed as needed while minimizing the command overhead to the minimum. In a disk drive device 10, even if a read command is issued, and all the required data is stored in the cache memory such that the data transfer can be performed without the intervention of a local MPU 16, a HIC 15 performs the data transfer so as to leave the last one block and waits for the intervention of the local MPU 16. The local MPU 16 provides instructions to transfer the last one block when the preparation for the command termination is completed, and if a plurality of blocks of data to be transferred are remaining when the local MPU 16 instructs the HIC 15 to transfer the last one block, the HIC 15 executes all the data transfer without stopping the data transfer before the last one block, completing the command.

Abstract: In a massively parallel processing (MPP) system, bandwidth efficiency and message packet latency rates are improved by providing routing elements that detect, isolate and identify various routing errors. More specifically, during the transmission of a message packet from a first routing element to a second routing element in the MPP system, link lock-up can be prevented effectively by determining whether the message packet contains a certain predefined quantity of data. Control codes, used for establishing the end to the message packet, can then be inserted into the message packet if it is determined that the message packet does, in fact, contain the predefined quantity of data.

Abstract: A communication control device has a central processing unit (3), an input data buffer (14), an output data buffer (15), a readout reload register (17), an output reload register (18), and a timer (19) located between an input terminal (1) and an output terminal (2). The timer (19) reads count values stored in both the reload registers (17, 18) alternately, that have already been set by the central processing unit (3) according to a protocol to be processed, and performs a counting operation based on the count values. Communication data items stored in both the data buffers (14, 15) are latched based on a time out output from the timer (19).

Abstract: A PCMCIA host adapter includes the capability to master a non-DMA system bus and control a DMA data transfer between a DMA capable peripheral and the internal system memory. A peripheral can be coupled to the system through a PCMCIA card plugged into a PCMCIA expansion slot. A DMA controller coupled to the PCMCIA expansion slots through a PCMCIA bus controls a DMA transfer between the internal system memory and the peripheral. A bus master disables the CPU and takes control of the system bus during a DMA data transfer. In an alternative embodiment, the PCMCIA host adapter can be used with either a system having a system bus with DMA capability or with a system having a system bus without DMA capability. In this alternate embodiment if the system bus has DMA capability, the PCMCIA host adapter effectively passes the DMA signals between the peripheral and the system bus.

Abstract: A data processing system (20) having a burst address generator (BAG) 55, with a programmable transaction mode applicable to both cache and pre-fetch architecture types. BAG 55 asserts a data acknowledge (DTACK) signal to end a burst transfer on either a physical boundary, as in pre-fetch mode at the end of a row in a memory device, or a limit detection, as in cache mode where the limit is determined by the length of a cache line. BAG 55 increments the burst address internally, and for operations in pre-fetch mode, the user determines if the incremented address is provided external to data processor (22).

Abstract: A media server system and method for reducing the probability of data starvation or underflow in a media server system. The media server system preferably comprises a video server computer system which stores a plurality of encoded data streams, wherein the computer system is coupled through a SCSI (Small Computer Systems Interface) bus to one or more MPEG decoder blocks. The media server system thus utilizes a single control channel for multiple video channels. The present invention operates to fill the FIFO buffer of a channel to a higher level during startup, thus reducing the probability of data underflow. In one embodiment, the host computer or server begins data transmission prior to sending the "play" function or play command in order to pre-fill or pre-load the buffer. In another embodiment where the host server is not configured to pre-load the buffer prior to issuing the play command, the MPEG decoder block disables the FIFO buffer when the play command is received.

Abstract: An apparatus for recording the transfer information transferred to it includes a plurality of recording media for recording the transfer information transferred from an information transfer apparatus, a writing control unit for controlling the writing of the transfer information in the recording media, and a transfer control unit for transmitting the transfer control information and an information transfer request signal to the information transfer apparatus. The transfer control information is the information for determining the transfer sequence of information blocks when the information transfer apparatus transmits the transfer information as the information blocks. The information recording apparatus transmits an information transfer request signal after transmitting the transfer control information to the information transfer apparatus.