Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a plurality of flow controllable queues containing data to be transmitted. The queues are organized by flow. The apparatus also includes a plurality of destinations to receive data from the plurality of queues. The apparatus further includes a controller to continually maintain an aggregate count of data ready for transmission to the destinations and determine next queue to transmit data from based at least partially on the aggregate counts.

Abstract: A FIFO memory receives data transfer requests before data is stored in the FIFO memory. Multiple concurrent data transfers, delivered to the FIFO memory as interleaved multiple concurrent transactions, can be accommodated by the FIFO memory (i.e., multiplexing between different sources that transmit in distributed bursts). The transfer length requirements associated with the ongoing data transfers are tracked, along with the total available space in the FIFO memory. A programmable buffer zone also can be included in the FIFO memory for additional overflow protection and/or to enable dynamic sizing of FIFO depth.

Abstract: Various embodiments of a scalable routing system for use in an interconnection fabric are disclosed. In this routing scheme, a routing directive describes a route in the interconnection fabric between a sending node and a destination node. Either the sending node or a sending device connected to the sending node encodes the routing directive in a message to be sent to the destination node. The routing directive may include a variable number of segments. Each segment includes a distance component and a direction component that tell each node along the route how it should send the message. Generally, each distance component describes a distance in the interconnection fabric while each direction component specifies a direction in the interconnection fabric.

Abstract: Schemes for determining whether all of the fragments of a datagram are received are described herein. The schemes described herein can allocate fifteen bits of memory to one or more counters to facilitate a determination of whether all of the fragments of a datagram are received.

Abstract: Exemplary systems, methods, and devices dynamically characterize a portion of a total cache as a read cache or a write cache in response to a host workload. Exemplary systems, methods, and devices receive a host workload parameter and allocate cache memory to either of a read cache or a write cache based on the host workload parameter.

Abstract: A system includes logic configured for counting transitions between data on a bus and data to be put onto the bus. Where the counted transitions exceed a threshold, the data to be put onto the bus is complemented. As a result, complemented data is put on the bus where the threshold was exceeded and un-complemented data is put on the bus where the threshold was not exceeded.

Abstract: A communications control circuit includes: a common work RAM storing communications data; an address register; a data-set-count register; an information register; an address counter; a data set counter; a RAM control circuit reading transmission data from a common memory in response to a transmission data request, writing reception data to the common memory in response to a reception data request, and generating a counter clock; a transmission circuit; a reception circuit; and a communications controller setting the address counter to an address upon transmission/reception and a counter to a number of sets of data, and if transmission/reception has been successful, writing the address back to the address register and the number of sets of data back to the register.

Abstract: Various embodiments of systems and methods for implementing a streaming I/O protocol are disclosed. In some embodiments, a method may involve: receiving a packet initiating a streaming write operation, where the packet indicates that the size of the streaming write is larger than the size of the packet; initiating a write access having a size larger than the size of the packet to a storage device; receiving subsequent packets included in the streaming write operation; and writing data received in the subsequent packets to the storage device as part of the write access initiated in response to the earlier packet. In some embodiments, streaming read operations may also be supported.

Abstract: An interface card includes data transmission routes which allow for data transmission in a plurality of data transmission modes and a mode selection switch for selecting a data transmission mode from the plurality of modes. With the interface card, a user is able to select an optimal data transmission mode for the environment.

Abstract: Logic (also called “re-ordering semaphore”) issues semaphore grants to access a shared resource in an order different from the order in which semaphore requests for accessing the shared resource are received. The re-ordering semaphore needs to receive a semaphore release between any two semaphore grants. There is no limit on the duration between a semaphore grant and a semaphore release, so that a task that receives a semaphore grant can use the shared resource for any length of time. In one embodiment, each request is associated with a number indicative of the order in which grants are to be issued, and the re-ordering semaphore uses this number in deciding which request is to be granted. The number can be a sequence number that is indicative of the order of arrival of packets that generated the requests.

Abstract: Embodiments are provided in which a method is described for transferring data in a digital system including a first bus, a second bus, a PCI-X bridge coupling the first and second buses, and a first device and a second device residing on the first and second buses, respectively. The first bus has the same or higher bandwidth than that of the second bus. According to the method, the PCI-X bridge immediately starts or resumes forwarding split completion data from the first device to the second device if the first device starts or resumes split completion data transfer to the PCI-X bridge at the beginning of a block (i.e., the start or resume byte address has the form of 128N). If the first device starts transfer to the PCI-X bridge not at the beginning of a block, the PCI-X bridge refrains from forwarding split completion data until (a) the first device sends the data byte at the beginning of the next block to the PCI-X bridge or (b) the byte transfer count is exhausted, whichever occurs first.

Abstract: A head and tail caching system. The system includes a tail FIFO memory having a tail input to receive incoming data. A memory is included that is operable to store data that is output from the tail FIFO and output the stored data at a memory output. A multiplexer is included having first and second multiplexer inputs coupled to the tail FIFO and the memory, respectively. The multiplexer has a control input to select one of the multiplexer inputs to coupled to a multiplexer output. A head FIFO memory receives data from the multiplexer output, and outputs the data on an output data path. A controller is operable to transfer one or more blocks data having a selected block size from the tail FIFO to the memory and from the memory to the head FIFO, to achieve a selected efficiency level.

Abstract: A system for transmitting and receiving data between a data transmitting device such as a computer and a data receiving device such as a peripheral device is capable of shortening the time required to complete transmission and receipt of all of the data, including re-transmission of missed data. The data transmitting device is provided with a first transmitting section to periodically and sequentially send a plurality of split data obtained by splitting data to be transmitted to the peripheral device, and with a second transmitting section. The second transmitting section sends split data, when the data receiving device was unable to receive split data fed from the first transmitting section, to the data receiving device during a period of time between time bands in which the first transmitting section transmits the split data.

Abstract: A communication system, network interface and communication port is provided that includes a media local bus. The local bus is connected between a controller and one or more multimedia devices located within a node of the communication system. The controller periodically broadcasts addressing signals to the source devices to synchronize data transmission from those devices according to those addresses. Source devices will thereafter transmit a command which signifies the type of data being transmitted from that source device within the address channel. The channel is maintained and data is transmitted until the next address is sent from the controller. Each channel can be set up in a customized fashion to add flexibility in channel length and data types being transferred throughout the local bus without having to assign fixed and regimented time slots for those data types and for each device connected to the local bus.

Abstract: A method for facilitating transfer of data between a master block and a slave block through a bus. The method includes ascertaining a transfer size of the data. The method also includes designating a first possible transfer size in a set of possible transfer sizes a chosen transfer size, the set of possible transfer sizes including possible transfer sizes ranging from 20 to 2n, where 2n at least equals to the largest transfer size desired between the master block and the slave block, the first possible transfer size presenting the largest possible transfer size in the set of possible transfer sizes that is less than or equal to the transfer size. The method additionally includes transferring a first data portion of the data from the master block to the slave block, the first data portion having a size that is equal to the chosen transfer size.

Abstract: A memory controller for a multi-byte burst memory device may control access to memory based on parameters set up by a client. These parameters may include a byte address and a byte count that indicates the number of bytes the client is requesting from memory. These values, and an integer representing the number of bytes in a burst-accessed word, may be operated on to produce a word that may be used to identify valid bytes in the burst-accessed word.

Abstract: A method for processing a PCI-X transaction in a bridge is disclosed, wherein data is retrieved from a memory device and is stored in a bridge then delivered to a requesting device. The method may comprise the acts of allocating a buffer in the bridge for the PCI-X transaction, retrieving data from a memory device, wherein the data comprises a plurality of cachelines, storing the plurality of cachelines in the buffer, wherein the plurality of cachelines are tracked and marked for delivery as the plurality of cachelines are received in the buffer, and delivering the plurality of cachelines to the requesting device in address order, the plurality of cachelines transmitted to the requesting device when one of the plurality of cachelines in the buffer aligns to an ending address of an allowable disconnect boundary (ADB) and the remaining cachelines are in address order.

Abstract: A method for verifying clock signal frequency of a sound interface of a computer system is disclosed. The processes include steps of initializing and setting a DMA controller and the sound interface, starting DMA data transfer, resetting a time out counter. During the DMA data transfer, a step of incrementing the time out counter is performed until the selected DMA channel of the DMA controller reaches a terminal count condition. After each increment, it is checked if DMA data transfer is time out. When the DMA channel of the DMA controller reaches the terminal count condition, the current count of the time out counter is compared with a maximum tolerable count and a minimum tolerable count. If the count of the time out counter is between the maximum and minimum tolerable counts, a message indicating the clock signal frequency of the sound interface is correct is issued, otherwise a message indicating the clock signal frequency is incorrect is issued.

Abstract: A method and apparatus for processing bytes received from a data stream includes multiple parallel byte processing engines that simultaneously process a first set of bytes received from a data channel during a first cycle and simultaneously process a second set of bytes received from the data channel during a second cycle. The method and apparatus further includes a state memory for storing byte information pertaining to the first set of bytes. When processing HDLC protocol bytes, the multiple parallel byte processing engines process the first and second set of bytes to identify at least one delineating byte contained within the data channel in accordance with a HDLC protocol.

Abstract: The data transfer apparatus and method employs two queue counters to maintain the status of a first-in-first-out buffer memory. A master count (251) indicates the number of entries available for use within the FIFO (410). New data can be allocated to the FIFO only if this master count is non-zero. This master count is decremented (401) upon allocation of new data to the FIFO. A remote count (252) stores the number of data entries stored in the FIFO. This remote count is incremented (413) upon allocation of data to the FIFO and decremented (414) upon reading data from the FIFO. A confirm decrement signal (408) from the remote count triggers an increment of the master count. This two counter technique makes better use of the available bandwidth than the prior art by not requiring a FIFO depth equal the to the data transfer latency. This technique is particularly useful in systems with delays between the data source and data destination and a mismatch of maximum data transfer rates.

Abstract: A method and an architecture capable of adaptively accessing data and instructions are provided, in which a plurality of data transfer levels are predefined and a current data transfer level is used for accessing data and instructions of a memory. Each data transfer level corresponds to a length of a continuous data transfer via an interface between the memory and a cache device. Thus, the invention can dynamically adjust the current data transfer level based on burst lengths actually occurred as a processor kernel accesses data/instructions.

Abstract: An apparatus for limiting a data transfer bandwidth through handshake suppression is configured to generate a first reset signal, generate a second reset signal a predetermined number of clock cycles after generating the first reset signal, generate a handshake count representing a number of receptions, between the first reset signal and the second reset signal, of a first Ready to Send (“RTS”) handshake signal and a first Ready to Receive (“RTR”) handshake signal, and disable a second RTR handshake signal and the first RTS handshake signal based on a comparison of the handshake count and a maximum value.

Abstract: An input data processing circuit according to one aspect of the present invention comprises a phase detector 50 adapted to detect a clock phase difference between the first and second clocks which are sent from doubled circuits. The readout circuitry 60 selects one of the first and second FIFO buffers (10 or 30) if the clock phase difference is greater than a predetermined time corresponding to a half of data length of the frame, namely, “m” bytes of the input data sets. In this case, the selected FIFO buffer (10 or 30) has a faster clock by the clock phase difference than another clock between the first and second clocks. Then the readout circuitry 60 reads the frame out of only the selected FIFO buffer. As the results, no occurrence of “data lack” in FIFO buffers even if a clock rate difference exists between clocks generated by doubled circuits.

Abstract: An apparatus and method for executing an instruction with a register bit mask for transferring data between a plurality of registers and memory inside a processor is provided. The method includes adding the N bits in the N-bit decode information together to form an initial count value, and generating a plurality of register identification (ID) numbers equivalent in number to the initial count value. The register ID numbers correspond to the positions in the N-bit decode information that has a bit value ‘1’. According to the register ID number, a link is created between the plurality of registers corresponding to the register ID numbers and a memory unit so that the memory unit and the registers are free to exchange stored data.

Abstract: Described are techniques for performing compression and decompression of statistical data. This data may be used in connection with performing optimizations. A delta value for each statistic is determined representing a difference between a current value and a previous value. Delta values are stored in a statistics table in a compressed form using a monotonic compression scheme. Small tables are used to determine decompressed values estimating the observed values when information is retrieved for use to within a predetermined relative error. Statistical information is stored and represented in a statistics table and an events table. Statistical information is selectively fetched and loaded into memory from a storage device. Indexing techniques are used to force physical continuity rows of the tables in accordance with a specified retrieval order.

Abstract: An apparatus and method for controlling packet generation in a bus that couples a host to a plurality of devices. The apparatus includes a host controller for use with the bus and the host. The host controller has an SOF packet generator capable of delaying the generation of an SOF packet if there is another transaction occurring in the bus until the transaction is complete, thereby to relax the frame timing of SOF packet generation sequences.

Abstract: An initial address register holds a transfer destination address as an initial address. Data is written into an input data register to which a unique address is allocated. The written data is put together into a data block having a predetermined transfer destination data size. This enhances the efficiency of data transfer from a software program for processing data in several byte units to a memory and a coprocessor optimized for data transfer in block units of several tens of bytes, and thus improves system performance.

Abstract: Provided is a method, system, and program for enabling a client to access a service, wherein the client is capable of communicating with a server. The client accesses an object from the server that includes code to enable the client to access the service. The accessed object includes a request rate indicating a rate at which the client transmits requests for the service. The client generates requests for the service using code included in the object accessed from the server. The client then transmits the generated requests for the service at the request rate included in the object.

Abstract: An amount of data to be pre-fetched during read operations is adaptively modified based upon the experience of previous reads. If previous reads were terminated before all the data desired was obtained, subsequent read amounts may be increased. The initial amount of pre-fetched data may be pre-set or modified dynamically.

Abstract: A simultaneous and redundantly threaded, pipelined processor can execute the same set of instructions simultaneously as two separate threads to provide, for example, fault tolerance. One thread is processed ahead of the other thread thereby creating a “slack” between the two threads so that the instructions in one thread are processed through the processor's pipeline ahead of the corresponding instructions from the other thread. The thread, whose instructions are processed earlier, is called the “leading” thread. The other thread is the “trailing” thread. By setting the amount of slack appropriately, all or at least some of the cache misses or branch misspeculations encountered by the trailing thread can be resolved by the time the corresponding instructions from the trailing thread are fetched and processed through the pipeline. The invention, therefore, improves the performance of a fault tolerant, simultaneous and redundantly threaded processor.

Abstract: DMA transfer request signals corresponding to respective channels are received and held in respective transfer request holding circuits. DMA transfers are assigned to the DMA transfer request signals respectively in a channel transfer request arbitrating circuit according to priorities set in advance for the DMA transfer request signals, and the DMA transfers for the DMA transfer request signals are performed in the order of lower priority. Also, a transfer waiting time period from the reception of one DMA transfer request signal to the assignment of the DMA transfer is measured in a transfer waiting time counter for each DMA transfer request signal, and the transfer waiting times are, for example, stored in a storing circuit and are selectively read out.

Abstract: The present invention is directed to a buffer partitioning system and a method employing the system to dynamically partition buffer resources among multiple data streams. The buffer partitioning system utilizes context information relating to the streaming data to control the flow of data through the buffer resource. By including a buffer partitioning system, multiple data streams may be more efficiently transferred through buffer resources thus resulting in faster data transfers.

Abstract: According to one aspect of the present invention, a method is provided in which a device, in response to a read request issued by a host, transfers data to the host through a series of direct memory access (DMA) data in bursts. The host is allowed to interrupt the data transfer and terminate the data in burst upon completion of a portion of the data transfer.

Abstract: A method and apparatus for transferring optical data from a DVD in response to a request from a host. When a data request is issued, a portion of the request containing the target ID for the target data block is used by a comparator circuit to locate the target data block. Another portion of the request containing the number of data blocks requested is used by a monitoring circuit to monitor data block transfer from a DVD to a data buffer once the target data block is located. The monitoring circuit stops data transfer when all of the requested data blocks have been transferred. Each data block is transferred into a data buffer containing areas separated by pointers. In a scratch area of the data buffer, the data block is error corrected, error checked and descrambled.

Abstract: An FIFO data transfer control device includes an instruction analyzing portion for analyzing an instruction for data transfer to an FIFO storage device including a plurality of banks, and calculating an amount of data to be transferred; a data count portion for calculating, from the data amount calculated by the instruction analyzing portion, an amount of the data written in the bank being in an outputting state, and issuing a determination flag indicating whether the free space of the bank being in the outputting state satisfies predetermined conditions or not; and a full check portion for inhibiting processing of a next instruction until the determination flag sent from the data count portion or the full flag issued from the FIFO storage device is reset.

Abstract: Recording control with additional information superposed on data and recording control in response to a type of a recording medium on which data are recorded are disclosed. A recording apparatus for recording data onto a recording medium includes an identification data detection section for detecting identification data for identification of data from the data, a copying count data detection section for detecting copying count data for limiting the number of times of copying the data from the data, and a recording control section for controlling recording of the data onto the recording medium based on the identification data detected by the identification data detection section and the copying count data detected by the copying count data detection section.

Abstract: A communications system comprises a PDA and a Bluetooth peripheral device. The Bluetooth peripheral device is connected to the PDA by a data channel. The Bluetooth peripheral device enables the PDA to communicate with remote data networks using the Bluetooth wireless protocol. The system is configured to operate according to an algorithm that enables the Bluetooth peripheral device to enter an ultra-low power mode in which a receiver associated with data transfer can be disabled when no data is required to be transmitted. Data loss is prevented through the use of a hardware handshake mechanism that stops the PDA from sending data while the Bluetooth peripheral device is in the low power mode. Latency in the PDA responding to a change in handshake signals is provided.

Abstract: A telecommunications data conferencing platform has a secure zone and a partly secure zone connected by a secure firewall. The secure zone contains a master data server, a billing system a reservation system and an audio bridge connected to the firewall. The partly secure zone contains a pair of slave data servers. The first slave data server can be connected through a public firewall to the public Internet. The first slave data server can receive incoming calls from the public switched telecommunications network via a bank of modems. The secure firewall restricts the passage of messages from the partly secure zone to the secure zone to messages which originate directly in the partly secure zone but allows the passage of conference data. Thus, unauthorised parties are unable to gain access to the reservation system or the master data server. In order to establish a conference, the reservation system creates a conference on the master data server.

Abstract: If a recording medium having a medium ID is used, a secure manager manages enciphering/decoding of a content with use of the medium ID for each recording medium. If a HDD having no medium ID is used, the secure manager obtains a device ID specific to a computer system through a BIOS and manages enciphering/decoding of a content to be recorded into the HDD, with use of the device ID. The device ID is stored in a safe area in the computer system. As a result, even if a content is recorded into an open recording medium such as a hard disk drive, the content can be protected from improper use so that utility and protection of digital contents can be improved.

Abstract: An output interface allows a user circuit to access data for multiple objects in an interleaved fashion. Status information is provided to guarantee data availability before each transfer sequence is started. An identifier is provided for each object. Each identifier, after data transfer has ended, may be subsequently reused to identify a different object. The interface provides the ability to retrieve all data in an object or to cancel the object before reaching the end and discarding the unretrieved data. The objects are provided to the appropriate processing mechanisms within the printer to implement a printing task. These objects correspond to images and text to be printed on a page. Object data is temporarily stored in limited data memory of the memory system and object headers are stored in header memory before transfer via the output interface. Each object to be printed has an object header and may, or may not, have associated object data.

Abstract: Disclosed are a system and method of transmitting and receiving data through a peripheral device coupled to a transmission medium. The peripheral device is coupled to a host processing system through a data bus. The peripheral device includes logic to discriminate among data cells based upon virtual channels and maintains a receive buffer for storing data cells for each virtual channel. When a buffer fills, the peripheral device transmits the data cells to a receive buffer queue associated with a virtual channel and maintained in the host processing system. The host processing system may also maintain a plurality of transmit buffer queues for storing data cells for transmission in virtual channels. The peripheral device may also comprise logic for scheduling data cells in the transmit buffer queues for transmission according a quality of service (QoS) associated with one or more virtual channels.

Abstract: A data processing system comprises: a plurality of data processing modules for performing a series of data processing, wherein each of the plurality of data processing modules processes data; a bus connected to each of the plurality of data processing modules; a memory controller for writing the data processed by each of the plurality of data processing modules into a memory via the bus, and for reading out the written data from the memory via the bus; a DMA controller for determining operation of each of the plurality of data processing modules, and outputting an address to the memory controller, the data processed by said data processing module being written at the address and the DMA controller including a data parallel processing control section. The plurality of data processing modules includes first and second data processing modules, and the second data processing module is subsequent to the first data processing module in the series of processing.

Abstract: A method is described for controlling commands and data in a serial data stream received by a serial controller in a serial interface. A character count register is programed with a maximum number of characters that a serial controller will send to a direct memory access controller (DMAC) before sending an end of frame (EOF) indication. Characters in an incoming data stream are counted using the character count register. An EOF signal is passed to the DMAC after the maximum number of characters programmed in the character count register have been written to a direct memory access (DMA) buffer. The character count register is reset any time the serial controller passes an EOF to the DMAC. In one embodiment, a character is programmed into a match register. Data in an incoming data stream is compared with the character in the match register. When a character in the incoming data stream matches the character programmed in the match register, a match bit is set corresponding to the match register.

Abstract: A method and apparatus for controlling the flow of information (e.g., graphics primitives, display data, etc.) to an input/output unit within a computer controlled graphics system. The system includes a processor having a first-in-first-out (FIFO) buffer, a separate input/output unit with its FIFO buffer, and a number of intermediate devices (with FIFO buffers) coupled between the input/output unit and the processor for moving input/output data from the processor to the input/output unit. Mechanisms are placed within an intermediate device which maintain an accounting of the number of input/output data sent to the input/output unit, but not yet cleared from the input/output unit's buffer. These mechanisms regulate data flow to the input/output unit. The system also includes an efficient return channel to minimizine the amount of data transfer bandwidth required in returning status information on the FIFO buffer of the input/output unit.

Abstract: A data transmission buffer circuit is provided for buffering communication data, which is divided into a plurality of multiple-bit data frames that have a start and an end. The buffer circuit includes a first-in-first-out (FIFO) buffer and a frame counter. The FIFO buffer has a write port and a read port. The write port includes a data input, a write control input and an end-of-frame flag input, which indicates whether data on the data input includes the end of one of the data frames. The read port includes a data output, a read control input, and an end-of-frame flag output, which indicates whether data on the data output includes the end of one of the data frames. The frame counter is coupled to the write port and the read port and generates a frame count output that represents a number of the data frames stored in the FIFO buffer.

Abstract: To reduce FIFO access cycles across a system bus in a multi-processor system in which two processors communicate across a system bus through a FIFO, two separate FIFO descriptors are provided. The first descriptor is maintained by the processor located on-board with the FIFO, and the second descriptor is maintained by an off-board processor which communicates with the FIFO across the bus. When one processor performs a FIFO operation, the processor updates the other processor's descriptor via a memory access across the bus. Additionally, one module passes credits to the other to indicate that the latter has permission to perform a plurality of FIFO operations consecutively. In one embodiment a special non-valid data value is used to indicate an empty FIFO position.

Abstract: A system transfers BIOS instructions from a BIOS ROM to a processor for either execution or storage in a system memory. The BIOS ROM has an address bus coupled to an address bus of the processor and a data bus coupled to the an intelligent drive electronics (“IDE”) controller through the data bus portion of an IDE bus. In operation, the processor applies addresses directly to the address bus of the BIOS ROM, and the corresponding instructions are coupled through the IDE data bus and the system controller to the data bus of the processor.

Abstract: Data is converted from a first granularity to a second granularity different from the first granularity. The ratio “n” of the second granularity of the data to the first granularity of the data is determined as a power of 2. The least significant n bits of the beginning alignment of the data are added to the least significant n bits of the beginning count of the data, and the carry bit of the sum is designated as “c”. A logical “OR” is performed of the bits of the resulting sum to obtain a value designated as “d”. A number of data units, equal to the sum of “c” and “d”, is added to the data.

Abstract: An information processing apparatus connected to a network to which plural information processing units are connected, in order to enable variation of the image frame rate in a specified information processing apparatus, thereby displaying a watched image in a smoother manner or decreasing the frame rate of unwatched images to increase the frame rate of another image. The information processing apparatus comprises a configuration for recognizing an instruction for varying the amount of image data released from an arbitrary one among the plural information processing apparatus and controlling the amount of image data released from the arbitrary information processing apparatus according to the recognition.

Abstract: A command queue control device, when there is the command which is not completed in spite of a lapse of prescribed time period, is capable of facilitating the command processing of the disk device, even though delay occurs in the command processing of the disk device, by causing the disk device to facilitate acceleration of the command.