Group Patents (Class 710/42)
  • Patent number: 11907582
    Abstract: Systems, methods, and non-transitory computer-readable media for providing a cloud storage device implementing C-ZNS architecture. The cloud storage device including a housing and a plurality of blades, with at least one blade including a plurality of storage devices and an electronic processor. The electronic processor is configured to receive data and a command from a host application to write the data to a corresponding zone of a first storage device of the plurality of storage devices, initialize a buffer in response to receiving the data, store the data in the buffer that is initialized, determine one or more parameters in response to receiving the command, determine that the command is error-free based on the one or more parameters, and write the data from the buffer into the corresponding zone in response to determining that the command is error-free.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: February 20, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Senthil Kumar Veluswamy
  • Patent number: 8918557
    Abstract: A SAS expander configured to operate as a SAS expander hub receives IO requests from a plurality of connected SAS expanders. Each SAS expander determines if it is capable of servicing a received IO request and sending such IO requests to the SAS expander hub if necessary. The SAS expander hub relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: December 23, 2014
    Assignee: LSI Corporation
    Inventor: Brett J. Henning
  • Patent number: 8918558
    Abstract: Method and structures for performing round robin priority selection receive an input vector into an input port. The methods and structures group the bits of the input vector into groups of bits and supply the groups of bits to round robin priority selectors. Then, the methods and structures simultaneously identify an individual group priority bit within each group of bits based on the starting bit location, using the round robin priority selectors. The methods and structures also choose, using the group selector, a round robin priority selector based on the starting bit location. The methods and structures then output, from the group selector to a multiplexor, the individual group priority bit of the selected round robin priority selector. Following this the method outputs, from the multiplexor, an output vector having a first value (e.g., 1) only in the individual group priority bit output by the group selector.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventor: Jay G. Heaslip
  • Patent number: 8874807
    Abstract: Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: October 28, 2014
    Assignee: Oracle International Corporation
    Inventors: Sue K. Lee, Vivekananda C. Kolla, Akshay D. Shah, Sumanta Chatterjee, Margaret Susairaj, Juan R. Loaiza, Alexander Tsukerman, Sridhar Subramaniam
  • Patent number: 8850059
    Abstract: Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits and similar electronic components having different communication capacities or clock domains. The interface supports communication between any components having any difference in capacity and over any distance. The interface utilizes request and acknowledge phases and signals and an initiator-target relationship between components that allow each side to throttle the communication rate to an accepted level for each component or achieve a desired bit error rate.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey D. Hoffman, Allan R. Bjerke
  • Patent number: 8843672
    Abstract: An access method includes: obtaining, by a computer, a result of monitoring a busy rate and a number of access operations per unit time of a storage device, the storage device having a first storage area and a second storage area; calculating a characteristic of correlation between the busy rate and the number of access operations per unit time based on the result; calculating a second number of access operations per unit time based on the characteristic of the correlation such that a sum of a first busy rate corresponding to a first number of access operations per unit time and a second busy rate corresponding to a second number of access operations per unit time becomes equal to or lower than a given busy rate; and controlling a number of operations to access the second storage area per unit time based on the second number of access operations.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: September 23, 2014
    Assignee: Fujitsu Limited
    Inventors: Kazuichi Oe, Kazutaka Ogihara, Yasuo Noguchi, Tatsuo Kumano, Masahisa Tamura, Yoshihiro Tsuchiya, Takashi Watanabe, Toshihiro Ozawa
  • Patent number: 8683103
    Abstract: Exemplary system and computer program embodiments for hierarchy multi-tenancy support for configuration of a plurality of host attachment through a plurality of resource groups in a computing storage environment are provided. In one embodiment, multiple data storage subsystems are configured with multiple operators for configuration and management of multiple host attachments to multiple logical volumes. A logical operator is designated with the responsibility of designating authority to a host attachment operator and the ability to configure multiple logical volumes. Limited authority is provided for the host attachment operator to configure multiple volume groups and multiple host ports to a specific user.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventor: Richard A. Ripberger
  • Patent number: 8683104
    Abstract: Exemplary method embodiments for hierarchy multi-tenancy support for configuration of a plurality of host attachment through a plurality of resource groups in a computing storage environment are provided. In one embodiment, multiple data storage subsystems are configured with multiple operators for configuration and management of multiple host attachments to multiple logical volumes. A logical operator is designated with the responsibility of designating authority to a host attachment operator and the ability to configure multiple logical volumes. Limited authority is provided for the host attachment operator to configure multiple volume groups and multiple host ports to a specific user.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventor: Richard A. Ripberger
  • Patent number: 8671138
    Abstract: A network interface adapter includes a network interface and a client interface, for coupling to a client device so as to receive from the client device work requests to send messages over the network using a plurality of transport service instances. Message processing circuitry, coupled between the network interface and the client interface, includes an execution unit, which generates the messages in response to the work requests and passes the messages to the network interface to be sent over the network. A memory stores records of the messages that have been generated by the execution unit in respective lists according to the transport service instances with which the messages are associated. A completion unit receives the records from the memory and, responsive thereto, reports to the client device upon completion of the messages.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: March 11, 2014
    Assignee: Mellanox Technologies Ltd.
    Inventors: Michael Kagan, Diego Crupnicoff, Gilad Shainer, Ariel Shahar
  • Patent number: 8521923
    Abstract: Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: August 27, 2013
    Assignee: Oracle International Corporation
    Inventors: Sue K. Lee, Vivekananda C. Kolla, Akshay D. Shah, Sumanta Chatterjee, Margaret Susairaj, Juan R. Loaiza, Alexander Tsukerman, Sridhar Subramaniam
  • Patent number: 8417849
    Abstract: A method to adjust a multi-path device reservation by supplying a computing device and a storage controller interconnected with a communication link. The method further reserves a data storage device in communication with the storage controller, where that data storage device reservation is held by a first communication path group comprising a first plurality of communication paths configured in the communication link. If the method detects a failed communication path configured in the first communication path group, the method configures a second communication path group by removing the failed communication path from the first communication path group, wherein the second communication path group maintains the data storage device reservation.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: April 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Clint Alan Hardy, Matthew Joseph Kalos, Richard Anthony Ripberger
  • Patent number: 8332549
    Abstract: A method for communication between an initiator system and a block storage cluster may include receiving a first input/output (I/O) request from the initiator system. The method may also include sending a referral response from a first storage system included in a plurality of storage systems of the block storage cluster to the initiator system when data associated with the first I/O request is stored in more than one storage system of the plurality of storage systems of the block storage cluster. Additionally, the method may include directing a referral I/O to the first storage system and the second storage system for transferring data to or transferring data from the first storage system and the second storage system, and transferring data associated with the referral I/O to or transferring data associated with the referral I/O from the first storage system and the second storage system.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: December 11, 2012
    Assignee: LSI Corporation
    Inventors: Andrew J. Spry, Ross Zwisler, Gerald J. Fredin, Kenneth J. Gibson
  • Patent number: 8200888
    Abstract: Methods and apparatuses for delaying execution of input/output (I/O) requests for solid state drives are contemplated. Some embodiments comprise receiving I/O requests for a solid state drive and calculating amounts of time based on characteristics of the requests, such as differences of the logical block addresses (LBAs) of the requests. The embodiments may then delay responses by the solid state drive for the requests. Calculating the amounts of time and delaying the responses by the amounts of time may allow the solid state drives to emulate the responses of various types of hard disk drives. Some embodiments comprise an apparatus for delaying execution of the I/O requests for solid state drives. The apparatuses may have numerous modules, such as a request receiver to receive the I/O requests, a calculation module to calculate the amounts of delay times, and a delay module to delay the responses of the I/O requests.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: June 12, 2012
    Assignee: Intel Corporation
    Inventor: Svanhild Simonson
  • Patent number: 8185896
    Abstract: A method is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: May 22, 2012
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Ravi K. Arimilli, Ramakrishnan Rajamony, Edward J. Seminaro, William E. Speight
  • Patent number: 8145806
    Abstract: Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on a one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: March 27, 2012
    Assignee: Oracle International Corporation
    Inventors: Sue K. Lee, Vivekananda C. Kolla, Akshay D. Shah, Sumanta Chatterjee, Margaret Susairaj, Juan R. Loaiza, Alexander Tsukerman, Sridhar Subramaniam
  • Patent number: 8141077
    Abstract: A system, method and medium for reducing the number of system calls from an application program to an operating system kernel. In an embodiment, a method includes the steps of creating a list of requests issued by an application program, associating an indicia with the list indicating whether the list contains a request, querying the indicia to determine if the list contains a request, and adding a new application program request to the list when the indicia indicates that the list includes a request.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: March 20, 2012
    Assignee: Red Hat, Inc.
    Inventor: Alan Cox
  • Patent number: 8140731
    Abstract: A system is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Ravi K. Arimilli, Ramakrishnan Rajamony, Edward J. Seminaro, William E. Speight
  • Patent number: 8108571
    Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: January 31, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventor: Daniel L. Bouvier
  • Patent number: 8099532
    Abstract: A single fibre channel switch or serial attached SCSI expander applies zoning on the initiator ports to each of the two ports of one or more drives. The fibre channel switch or serial attached SCSI expander uses zoning to connect both ports of each drive to a single expander and set the zones in the expander such that each zone includes at least one initiator port and one drive port.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: January 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brian James Cagno, John Charles Elliott, Gregg Steven Lucas
  • Patent number: 8095706
    Abstract: The various embodiments of the present invention relate generally to the analysis of the mechanical properties of materials. More particularly, the various embodiments of the present invention relates to systems and methods of deriving the static and dynamic mechanical properties of deformative materials, for example, but not limited to, biological surfaces. The systems and methods of the present invention can be used to derive and evaluate the mechanical properties of many biological surfaces and subsurfaces, including but not limited to the skin.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: January 10, 2012
    Assignee: Georgia Tech Research Corporation
    Inventors: Stephen Sprigle, Linghua Kong, Qi Wang, Vincent Hayward, Jayme Caspall
  • Patent number: 8019902
    Abstract: A network interface adapter includes a network interface and a client interface, for coupling to a client device so as to receive from the client device work requests to send messages over the network using a plurality of transport service instances. Message processing circuitry, coupled between the network interface and the client interface, includes an execution unit, which generates the messages in response to the work requests and passes the messages to the network interface to be sent over the network. A memory stores records of the messages that have been generated by the execution unit in respective lists according to the transport service instances with which the messages are associated. A completion unit receives the records from the memory and, responsive thereto, reports to the client device upon completion of the messages.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: September 13, 2011
    Assignee: Mellanox Technologies Ltd.
    Inventors: Michael Kagan, Diego Crupnicoff, Gilad Shainer, Ariel Shahar
  • Patent number: 7958182
    Abstract: A mechanism is provided for performing collective operations. In hardware of a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In hardware of the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: June 7, 2011
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Ravi K. Arimilli, Ramakrishnan Rajamony, William E. Speight
  • Patent number: 7958282
    Abstract: Embodiments of the invention include a method and apparatus for managing SAS zoning using initiator isolation. The method includes assigning initiator devices in the SAS domain to a first initiator zone group, assigning target devices in the SAS domain to a second target zone group, and establishing an access control policy in which each of the initiator devices assigned to the first initiator zone group can communicate with each of the target devices assigned to the second target zone group but no initiator devices assigned to the first initiator zone group can communicate with any other initiator devices assigned to the first initiator zone group. Assignment of devices can be based on attachment information associated with each device, such as the ZPSDS entry point of the device, the SAS address of the device, and the phy of the zoning expander device in the SAS domain that is closest to the device.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: June 7, 2011
    Assignee: LSI Corporation
    Inventors: Louis Henry Odenwald, Jr., Roger Hickerson
  • Patent number: 7840737
    Abstract: This invention provide a data processor capable of multiplexing data transfers with desired data transfer characteristics guaranteed, without multiplexing buses. The data processor includes: a transfer path that mutually connects plural processors and plural transfer element circuits such as memory; an arbitration circuit that controls data transfer in the transfer path; and a control register that defines the priority and minimum guaranteed bandwidth of data transfer. The arbitration circuit decomposes data packets sent from plural data transfer sources into subunits, and reconstructs plural data packets having the same data transfer target, based on priority and minimum guaranteed bandwidth stored in a control register. Thereby, the one reconstructed data packet can include subunits of plural data packets from transfer sources having different priorities, and data amounts of subunits contained in it can satisfy minimum guaranteed bandwidth of data transfer.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: November 23, 2010
    Assignee: Renesas Electronics Corporation
    Inventor: Takanobu Tsunoda
  • Patent number: 7822885
    Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: October 26, 2010
    Assignee: Applied Micro Circuits Corporation
    Inventor: Daniel L. Bouvier
  • Patent number: 7797468
    Abstract: In certain, currently available data-storage systems, incoming commands from remote host computers are subject to several levels of command-queue-depth-fairness-related throttles to ensure that all host computers accessing the data-storage systems receive a reasonable fraction of data-storage-system command-processing bandwidth to avoid starvation of one or more host computers. Recently, certain host-computer-to-data-storage-system communication protocols have been enhanced to provide for association of priorities with commands. However, these new command-associated priorities may lead to starvation of priority levels and to a risk of deadlock due to priority-level starvation and priority inversion. In various embodiments of the present invention, at least one additional level of command-queue-depth-fairness-related throttling is introduced in order to avoid starvation of one or more priority levels, thereby eliminating or minimizing the risk of priority-level starvation and priority-related deadlock.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: September 14, 2010
    Assignee: Hewlett-Packard Development Company
    Inventors: George Shin, Rajiv K. Grover, Santosh Ananth Rao
  • Patent number: 7730235
    Abstract: A storage apparatus is provided that is capable of reducing data maintenance management costs with a performance that is both highly reliable and fast. The present invention is storage apparatus where an intermediary device is arranged between a controller and a plurality of disk devices of different performances arranged in a hierarchical manner. The controller unit carries out I/O accesses to and from the disk devices via the intermediary devices based on access requests sent from host apparatus. The intermediary device includes a power saving control function for the disk device and carries out operation control such as spin off and spin up of disk devices in accordance with conditions set in advance.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: June 1, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Kumasawa, Takashi Chikusa, Satoru Yamaura
  • Patent number: 7716390
    Abstract: A direct memory access controller is provided, in which an internal storage section storing control setting information; and a control section loading the control setting information from an external storage section to the internal storage section when a transfer request signal does not belong to a first group, and not loading the control setting information from the external storage section to the internal storage section when the transfer request signal belongs to the first group; are included, and a data transfer by a direct memory access is performed in accordance with the control setting information within the internal storage section.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: May 11, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Koji Takenouchi, Seiji Suetake
  • Patent number: 7676752
    Abstract: Systems and methods to specify device specific user interface information in firmware of a USB device are described. In one aspect, a USB device receives a host-specific device request from an application executing on a computing device coupled to the USB device. The USB device identifies a host-defined string descriptor defined by the application. The host-defined string descriptor is stored in firmware of the USB device.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: March 9, 2010
    Assignee: Microsoft Corporation
    Inventors: Firdosh K. Bhesania, Kenneth D. Ray, Stephane St. Michel
  • Patent number: 7603429
    Abstract: A network interface adapter includes a network interface and a client interface, for coupling to a client device so as to receive from the client device work requests to send messages over the network using a plurality of transport service instances. Message processing circuitry, coupled between the network interface and the client interface, includes an execution unit, which generates the messages in response to the work requests and passes the messages to the network interface to be sent over the network. A memory stores records of the messages that have been generated by the execution unit in respective lists according to the transport service instances with which the messages are associated. A completion unit receives the records from the memory and, responsive thereto, reports to the client device upon completion of the messages.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: October 13, 2009
    Assignee: Mellanox Technologies Ltd.
    Inventors: Michael Kagan, Dieo Crupnicoff, Gilad Shainer, Ariel Shahar
  • Patent number: 7565484
    Abstract: Provided are methods, apparatus arid computer programs for scheduling storage input and/or output (I/O) requests. A method for scheduling storage access requests determines a request processing sequence calculated to maximize SLA-based revenues achievable from processing a number of requests. A storage controller includes a scheduler which implements a revenue-based scheduling function to determine a revenue-maximizing processing sequence, and then assigns storage access requests to locations in a queue corresponding to the determined sequence. In an on-line mode, the scheduler can adapt to additional received requests, evaluating the revenue function for the additional requests and modifying the schedule if required. The method may include analyzing a request stream to predict requests that are likely to be received in the near future, and taking account of the predicted requests when determining a processing schedule.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: July 21, 2009
    Assignee: International Business Machines Corporation
    Inventors: Sugata Ghosal, Rohit Jain, Akshat Verma
  • Patent number: 7529873
    Abstract: A system and firewall for controlling access to resources within an information technology system. Commands received from a requesting entity request access to a resource associated with each command. An assigned authority level of the requesting entity is identified. At least one required authority level of the requesting entity is determined for each command as a function of each command and a resource criticality classification of the resource associated with each command. The requesting entity is granted or denied the requested access to the resource associated with each command if a determination has been made that each condition of at least one specified condition has or has not been satisfied, respectively. The at least one specified condition is specific to each command and includes a condition of the assigned authority level matching or exceeding an authority level of the at least one required authority level of each command.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: May 5, 2009
    Assignee: International Business Machines Corporation
    Inventors: Simon Keith Lambourn, Andrew David Missen, Marian Morgan, legal representative, Guy Iain Tarrant Sidford, William Bruce Morgan
  • Patent number: 7506075
    Abstract: An apparatus, program product and method of processing access requests for a direct access storage device utilize a “fair elevator” algorithm to schedule access requests from a plurality of requesters desiring access to a direct access storage device (DASD). In particular, a fair elevator algorithm arbitrates requests by taking into account both the requesters with which various requests are associated, as well as the relative positions of the data to be accessed on the DASD. By sorting access requests based upon both requester identity and DASD position, both multitasking performance and DASD throughput are improved in a balanced manner, thus improving overall system performance.
    Type: Grant
    Filed: December 7, 1999
    Date of Patent: March 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Troy David Armstrong, Michael Steven Faunce
  • Patent number: 7469305
    Abstract: In response to multiple data transfer requests from an application, a data definition (DD) chain is generated. The DD chain is divided into multiple DD sub-blocks by determining a bandwidth of channels (BOC) and whether the BOC is less than the DD chain. If so, the DD chain is divided by the available DMA engines. If not, the DD chain is divided by an optimum atomic transfer unit (OATU). If the division yields a remainder, the remainder is added to a last DD sub-block. If the remainder is less than a predetermined value, the size of the last DD sub-block is set to the OATU plus the remainder. Otherwise, the size of the last DD sub-block is set to the remainder. The DD sub-blocks are subsequently loaded into a set of available DMA engines. Each of the available DMA engines performs data transfers on a corresponding DD sub-block until the entire DD chain has been completed.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: December 23, 2008
    Assignee: International Business Machines Corporation
    Inventors: Lucien Mirabeau, Tiep Q. Pham
  • Patent number: 7409480
    Abstract: It becomes possible for a user to set a transmission or reception channel arbitrarily and easily. Each of equipment connected to an IEEE 1394 bus may include a register provided within a RAM 113 to thereby set a transmission or reception default channel. If channels used in the transmission and the reception are not set when the transmission is started, then default channel may be used. When equipment is set to a channel setting mode by operating an operation section 116, a control section 112 may display a channel setting picture on a display section 115. In this state, a user may select a set channel by operating an up-key 116a and a down-key 116b of the operation section 116. Thereafter, when a user operates a “YES” key 116c, the control section 112 may write a selected channel in the above-mentioned register, and ends a default channel setting operation. A user can set the transmission or reception channel arbitrarily and easily.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: August 5, 2008
    Assignee: Sony Corporation
    Inventors: Hajime Hata, Junji Kato, Makoto Sato
  • Publication number: 20080126616
    Abstract: A storage apparatus is provided that is capable of reducing data maintenance management costs with a performance that is both highly reliable and fast. The present invention is storage apparatus where an intermediary device is arranged between a controller and a plurality of disk devices of different performances arranged in a hierarchical manner. The controller unit carries out I/O accesses to and from the disk devices via the intermediary devices based on access requests sent from host apparatus. The intermediary device includes a power saving control function for the disk device and carries out operation control such as spin off and spin up of disk devices in accordance with conditions set in advance.
    Type: Application
    Filed: October 11, 2006
    Publication date: May 29, 2008
    Applicant: HITACHI, LTD.
    Inventors: Hiroyuki Kumasawa, Takashi Chikusa, Satoru Yamaura
  • Patent number: 7366812
    Abstract: A method, system, and firewall for controlling access to resources within an information technology (IT) system. Commands received from a requesting entity request access to a resource associated with each command. An assigned authority level of the requesting entity is identified. At least one required authority level of the requesting entity is determined for each command as a function of each command and a resource criticality classification of the resource associated with each command. The requesting entity is granted or denied the requested access to the resource associated with each command if a determination has been made that each condition of at least one specified condition has or has not been satisfied, respectively. The at least one specified condition is specific to each command and includes a condition of the assigned authority level matching or exceeding an authority level of the at least one required authority level of each command.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: April 29, 2008
    Assignee: International Business Machines Corporation
    Inventors: Simon Keith Lambourn, Andrew David Missen, Marian Morgan, legal representative, Guy Iain Tarrant Sidford, William Bruce Morgan
  • Patent number: 7340542
    Abstract: A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: March 4, 2008
    Inventors: William C. Moyer, Brett W. Murdock
  • Publication number: 20080005399
    Abstract: Command handling logic receives a plurality of command requests and groups the plurality of command requests into one of a plurality of command tracking classifications to produce classification tagged command requests. The plurality of classification tagged command requests and corresponding plurality of command responses are communicated via a bus. Command classification tracking logic tracks the plurality of classification tagged command requests and a corresponding plurality of classification tagged command response to determine when there are no outstanding command requests associated with one of the plurality of command tracking classifications. There are no outstanding command requests associated with one of the plurality of command tracking classifications when the command classification tracking logic has received a number of classification tagged command responses equal to the number of sent classification tagged command requests associated with the same command tracking classification.
    Type: Application
    Filed: May 16, 2006
    Publication date: January 3, 2008
    Applicant: ATI Technologies Inc.
    Inventors: Andrew E. Gruber, Mark Grossman
  • Patent number: 7277984
    Abstract: Provided are methods, apparatus and computer programs for scheduling storage input and/or output (I/O) requests. A method for scheduling storage access requests determines a request processing sequence calculated to maximize SLA-based revenues achievable from processing a number of requests. A storage controller includes a scheduler which implements a revenue-based scheduling function to determine a revenue-maximizing processing sequence, and then assigns storage access requests to locations in a queue corresponding to the determined sequence. In an on-line mode, the scheduler can adapt to additional received requests, evaluating the revenue function for the additional requests and modifying the schedule if required. The method may include analysing a request stream to predict requests that are likely to be received in the near future, and taking account of the predicted requests when determining a processing schedule.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: October 2, 2007
    Assignee: International Business Machines Corporation
    Inventors: Sugata Ghosal, Rohit Jain, Akshat Verma
  • Patent number: 7209981
    Abstract: A system is provided for switching the I/O channel for disk drives between multiple computers. The system incorporates the switch into removable drive modules, or a docking base for a removable drive module. The incorporation of switching into the system, such that it is integral with the drives, can reduce overall system failures, by reducing the number of elements which flow through a central switching element. Thus, even where a switch fails other drive modules of the system may continue to operate in the system and provide information to different computers of the system.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: April 24, 2007
    Assignee: Z Microsystems, Inc.
    Inventors: Jack P. Wade, Joel Brown
  • Patent number: 7181607
    Abstract: In response to requests for I/O processing sent from a computer, I/O which should be processed at a priority is enabled to be processed without being affected by other processing, by classifying I/O into those to be processed at a priority and those not to be processed at a priority. The storage control apparatus comprises an I/O processing controller with a memory that is common for the whole controller. The storage control apparatus manages information for dividing and controlling a plurality of I/O processes as priority and non-priority in that memory and operates while suppressing non-priority I/O processing on the basis of information in the memory.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: February 20, 2007
    Assignees: Hitachi, Ltd., Hitachi Software Engineering Co., Ltd.
    Inventors: Takeshi Ido, Youichi Gotoh, Shizuo Yokohata, Shigeo Honma, Toshiyuki Yoshino
  • Patent number: 7127678
    Abstract: The described system and procedure provide for storing device-specific UI information into firmware on a USB device. Responsive to receiving a host specific device request, the USB device communicates the device specific information to a requester such as an operating system or other computer program application. Thus, the system and procedure allow OEMs/IHVs to provide additional brand specific information in a USB device in a format that can be determined by an operating system. Moreover, the system and procedure allows OEMs/IHVs to store device-specific UI information in the firmware of a USB device such that installation media does not need to be distributed with each USB device to specify the device-specific information.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: October 24, 2006
    Assignee: Microsoft Corporation
    Inventors: Firdosh K. Bhesania, Kenneth D. Ray, Stephane St. Michel
  • Patent number: 7120715
    Abstract: A digital system and method of operation is provided in which several processors (740(0)–740(n)) are connected to a shared resource (750). Each processor has an access priority register (1410) that is loaded with an access priority value by software executing on the processor. A memory management unit (MMU) (700) is connected to receive a request address (742) from each respective processor. The MMU has a set of entries that correspond to pages of address space. Each entry provides a set of attributes for the associated page of address space, including an address space priority value 309a. For each request, the MMU accesses an entry corresponding to the request address and provides an address space priority value associated with that requested address space page. Arbitration circuitry (1430) is connected to receive a request signal from each processor along with the access priority value from each access priority register and the address space priority value from each MMU.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: October 10, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Dominique D'Inverno
  • Patent number: 7003379
    Abstract: In a limit cycle autotuning method, the first limit cycle of alternately outputting a heat-side manipulated variable set point and a cool-side manipulated variable set point is generated. The first control response corresponding to the first limit cycle is detected. The second limit cycle is generated by changing one of the heat-side manipulated variable set point and the cool-side manipulated variable set point on the basis of predetermined change instruction information for instructing which one of the heat-side manipulated variable set point and the cool-side manipulated variable set point is to be changed after the first limit cycle and a predetermined manipulated variable change ratio indicating the degree of the change. The second control response corresponding to the second limit cycle is detected. The control parameter for each of the heat mode and the cool mode is calculated on the basis of the detected first and second control responses. A heat/cool control apparatus is also disclosed.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: February 21, 2006
    Assignee: Yamatake Corporation
    Inventor: Masato Tanaka
  • Patent number: 6950869
    Abstract: The invention is to provide an information processing apparatus capable of easily setting operation parameters in acquiring various status from the plural peripheral apparatus, and a method therefor. In an image for setting the time-out value for a protocol for acquiring the status of the peripheral apparatus on the network, a change by the user on a time-out value for all the status acquisition from the peripheral apparatus is reflected on the time-out values for acquisitions of various statuses.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: September 27, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventor: Toshiaki Iizuka
  • Patent number: 6832273
    Abstract: The following system and procedure for specifying an extended configuration descriptor includes a USB device that responds to device requests from a host. In response to receiving a host-specific device request that specifies a predetermined index, the USB device returns an extended configuration descriptor to the requester. The extended configuration descriptor includes information that can be used by the requestor to control the USB device. When the USB device is a composite device, the extended configuration descriptor includes function information corresponding to a plurality of sub-devices. Each function comprises one or more interfaces.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: December 14, 2004
    Assignee: Microsoft Corporation
    Inventors: Kenneth D. Ray, Firdosh K. Bhesania, John C. Dunn
  • Patent number: 6807588
    Abstract: A sectioned ordered queue in an information handling system comprises a plurality of queue sections arranged in order from a first queue section to a last queue section. Each queue section contains one or more queue entries that correspond to available ranges of real storage locations and are arranged in order from a first queue entry to a last queue entry. Each queue section and each queue entry in the queue sections having a weight factor defined for it. Each queue entry has an effective weight factor formed by combining the weight factor defined for the queue section with the weight factor defined for the queue entry. A new entry is added to the last queue section to indicate a newly available corresponding storage location, and one or more queue entries are deleted from the first section of the queue to indicate that the corresponding storage locations are no longer available.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: October 19, 2004
    Assignee: International Business Machines Corporation
    Inventors: Tri M. Hoang, Tracy D. Butler, Danny R. Sutherland, David B. Emmes, Mariama Ndoye, Elpida Tzortzatos
  • Patent number: 6771556
    Abstract: The present relief module equipped random access memory avoids the need for enforced idle cycles for the processors, thereby enabling the State Machine to operate at its maximum speed. This relief module equipped random access memory also enables the Central Processing Unit to access the data in the single-port Random Access Memory as required to read and write the data contained therein. This is accomplished by the addition of a single-port Random Access Memory module to the plurality of Random Access Memory modules that are typically specified for a particular application. The extra Random Access Memory module alternates its output with each of the others of the plurality of Random Access Memory modules, on a sequential basis, thereby providing effectively extra clock cycles for each Random Access Memory module.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: August 3, 2004
    Assignee: Lucent Technologies Inc.
    Inventor: Charles Melvin Aden
  • Patent number: 6754734
    Abstract: Systems, methods, and computer products that improve the performance of computer-implemented I/O operations for complex applications, such as a database, that are ported to target computer systems that are not tailored to support the high-performance services that may benefit applications. Complex applications, such as a database, often manage I/O access operations by a caching mechanism that is tailored to the needs of the application. When porting an application to a target computer system that does not support certain I/O access features, I/O performance of the application may be limited. The present invention may be implemented by introducing specialized I/O access features that are tailored to enhance I/O access performance for complex applications, such as a database.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: June 22, 2004
    Assignee: International Business Machines Corporation
    Inventors: David Harold Goode, William Earl Malloy