Access Prioritization Patents (Class 710/40)
  • Patent number: 11508422
    Abstract: Systems, apparatuses, and methods for operating a memory device or devices are described. A memory device or module may introduce latency in commands to coordinate operations at the device or to improve timing or power consumption at the device. For example, a host may issue a command to a memory module, and a component or feature of the memory module may receive the command and modify the command or the timing of its execution in manner that is invisible or non-disruptive to the host while facilitating operations at the memory module. In some examples, components or features of a memory module may be disabled to effect or introduce latency in operation without affecting timing or operation of a host device. A memory module may operate in different modes that allow for different latencies; the use or introduction of latencies may not affect other features or operability of the memory module.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: November 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Eric J. Stave, George E. Pax, Yogesh Sharma, Gregory A. King, Chan H. Yoo, Randon K. Richards, Timothy M. Hollis
  • Patent number: 11455124
    Abstract: Aspects of a storage device including a memory and a controller are provided which re-prioritize commands based on zone properties. The controller receives from a host commands associated with a plurality of zones, allocates the memory into a plurality of zone resources based on zone properties indicated by the host for the zones, and identifies a utilization state of the memory for one of the zones. The controller changes a priority order of the commands based on the zone properties and the utilization state for the one of the zones. The controller then executes the commands in the memory or zone resources according to the priority order. As a result, execution of commands may be balanced between zones and lower latencies may be achieved overall for each zone. Improved performance or throughput of the storage device in handling zone commands may therefore result.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: September 27, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dinesh Kumar Agarwal, Amit Sharma
  • Patent number: 11307987
    Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 19, 2022
    Assignee: Texas Instmments Incorporated
    Inventors: Abhijeet Ashok Chachad, David Matthew Thompson, Naveen Bhoria, Peter Michael Hippleheuser
  • Patent number: 11102295
    Abstract: Systems, methods and devices relating to a network-accessible data storage device comprising a network interface in data communication with a network, the network interface for receiving and sending data units, the data units being assigned to at least one of a plurality of network data queues depending on at least one data unit characteristic; a data storage component communicatively coupled with the network interface, the data storage component comprising a plurality of data storage resources for receiving and responding to data transactions communicated in data units; and a queue mapping component for mapping each network data queues to at least one data storage resource for processing of data transactions.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: August 24, 2021
    Assignee: Open Invention Network LLC
    Inventors: Andrew Warfield, Mihir Nanavati
  • Patent number: 11068267
    Abstract: An aspect includes receiving a flush request at a processing unit that is in a current state defined by contents of registers in a register file. The processing unit includes a plurality of slices and the flush request includes an identifier of a previously issued instruction. The processing unit is restored to a previous state defined by contents of the registers in the register file prior to the previously issued instruction being issued. The restoring includes searching previous state buffers in at least two of the plurality of slices to locate data describing the contents of the registers in the register file prior to the previously issued instruction being issued. The restoring also includes combining the located data to generate results of the searching and updating the contents of the registers in the register file using a single port based at least in part on the results.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven J. Battle, Brandon Goddard, Dung Q. Nguyen, Joshua W. Bowman, Brian D. Barrick, Susan Eisen, Salma Ayub, Christopher M. Mueller
  • Patent number: 11023253
    Abstract: An information processing apparatus includes an extraction unit, an acquisition unit, and a presentation unit. The extraction unit extracts pieces of characteristic information of an initialization target program to be installed and initialized. The acquisition unit acquires at least one set value for initializing the initialization target program from at least one different program that has been installed. The acquisition unit acquires the set value in an ascending order of priorities assigned to the multiple different programs in accordance with a degree of matching in the pieces of characteristic information extracted by the extraction unit. The presentation unit presents the set value acquired by the acquisition unit.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: June 1, 2021
    Assignee: FUJI XEROX CO., LTD.
    Inventor: Masaru Fujii
  • Patent number: 10866733
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: December 15, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hiroshi Nishimura, Hideki Yoshida, Hiroshi Murayama
  • Patent number: 10856331
    Abstract: An example device detects a pattern of medium reservations by a first wireless device by detecting that the first wireless device has indicated a reservation duration that meets or exceeds a threshold duration value. Responsive to detecting the pattern of medium reservations, the device provides a mitigation operation to prevent a second wireless device from yielding the medium to the first wireless device.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: December 1, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kamesh Medapalli, Sangho Seo, Kenneth Ma
  • Patent number: 10782887
    Abstract: A distributed storage schemes manages implementation of QoS targets for IOPs across compute nodes executing applications, primary storage nodes storing a primary copy of a logical storage volume, and clone storage nodes. On the compute node, a maximum priority is assigned to a minimum number of IOPs in a queue within a time window from a time of receipt of a last unexecuted IOP. Other IOPs are assigned a minimum priority. On the storage node, maximum priority IOPs are assigned to high priority queues, from which IOPs are executed first, and low priority IOPs are assigned to low priority queues. Methods for determining the capacity of storage nodes and allocating storage requests are also disclosed.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: September 22, 2020
    Assignee: ROBIN SYSTEMS, INC.
    Inventors: Shravan Kumar Vallala, Dhanashankar Venkatesan
  • Patent number: 10705838
    Abstract: Microcode is stored in a program memory and intended to be executed by a central processing unit of a processing unit. The processing unit may include a memory controller associated with each program memory and a hardware peripheral. The method includes, in response to a request to update the microcode, a transmission, to each hardware peripheral, of a global authorization request signal obtained from an elementary authorization request signal generated by each corresponding memory controller, a transmission of a global authorization signal obtained from an elementary authorization signal generated by each hardware peripheral in response to the global authorization request signal and after satisfying a predetermined elementary condition, and an updating of each microcode by the corresponding memory controller only after the global authorization signal is received.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: July 7, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Vincent Onde
  • Patent number: 10657087
    Abstract: A semiconductor storage device includes a controller including a data direct memory access (DDMA) controller. The controller receives a plurality of read commands segmented into data transfer descriptors associated with data tags from a host device and directs a plurality of the data transfer descriptors to the DDMA controller. The DDMA controller pre-fetches one or more descriptors from the host device associated with one or more of the plurality of data tags, a first data tag having an associated number of descriptors corresponding to contiguous blocks of memory. The DDMA controller determines if the associated number of descriptors satisfies a threshold, and, if it does not, moves the first data tag to a first list, when at a head of the first list moves the first data tag to a second list, and when at a head of the second list, transmits the data associated with the first data tag.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 19, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Andrew J. Tomlin
  • Patent number: 10613896
    Abstract: A computer-implemented method according to one embodiment includes identifying an input/output (I/O) operation to be implemented within a distributed computing environment, where the distributed computing environment executes a plurality of different jobs, determining information associated with the I/O operation indicating that the I/O operation is associated with a recovery of one of the plurality of different jobs, and assigning an implementation priority to the I/O operation, based on the information associated with the I/O operation.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Subashini Balachandran, Lukas Rupprecht, Rui Zhang
  • Patent number: 10545890
    Abstract: An information processing device includes a memory, and a plurality of processor cores that access the memory. The plurality of processor cores respectively executes processes to be executed by the plurality of processor cores in accordance with execution priority levels of the processes. When a polling process for repeatedly determining whether reception data for input/output processing is received is underway in one of the plurality of processor cores, the plurality of processor cores respectively executes the input/output processing in response to a determination, made by the polling process, that the reception data have been received, and when the polling process is not underway in any of the plurality of processing cores, the plurality of processor cores respectively executes the input/output processing in response to a processor interrupt issued upon reception of the reception data.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: January 28, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Kosuke Suzuki, Kohta Nakashima
  • Patent number: 10547703
    Abstract: Described herein are systems, devices, and methods for content delivery on the Internet. In certain non-limiting embodiments, a caching model is provided that can support caching for indefinite time periods, potentially with infinite or relatively long time-to-live values, yet provide prompt updates when the underlying origin content changes. In one approach, an origin server can annotate its responses to content requests with tokens, e.g., placing them in an appended HTTP header or otherwise. The tokens can drive the process of caching, and can be used as handles for later invalidating the responses within caching proxy servers delivering the content. Tokens may be used to represent a variety of kinds of dependencies expressed in the response, including without limitation data, data ranges, or logic that was a basis for the construction of the response.
    Type: Grant
    Filed: July 22, 2018
    Date of Patent: January 28, 2020
    Assignee: Akamai Technologies, Inc.
    Inventors: Martin T. Flack, Moritz M. Steiner, Stephen L. Ludin, Jozef Hatala
  • Patent number: 10505733
    Abstract: Methods, systems, computer-readable media, and apparatuses may provide creation and management of composite tokens for use with services in a virtual environment without the user having to re-authenticate each time the user accesses a different service. A composite identity server may receive a request to upgrade a first authentication token for a user. The composite identity server may redirect a user agent to an identity provider for authentication and, in response, may receive a second authentication token for the user. The composite identity server may send the second authentication token to a federated microservice and, in response, may receive one or more claims of the second authentication token designated for inclusion in a composite token. The composite identity server may generate a composite token including the one or more claims of the first authentication token and one or more claims of the second authentication token.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 10, 2019
    Assignee: Citrix Systems, Inc.
    Inventors: Bradley Markus Rowe, Ricardo Feijoo, Tom Michael Kludy, Ayush Jain, Gerald Haagsma
  • Patent number: 10474587
    Abstract: Smart weighted container data cache eviction preserves write evict units (WEUs) containing the most frequently and recently accessed blocks to maintain low latency data cache. Prior to performing cache eviction, the WEUs are weighted based on the page statistics maintained for each WEU. Page statistics include page hit/frequency and recency statistics associated with each WEU and data cache eviction is performed at the WEU level of granularity. Therefore, an entire WEU can be evicted based on page hit/frequency and recency statistics associated with the WEU.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 12, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Satish Kumar Kashi Visvanathan, Rahul Ugale
  • Patent number: 10416908
    Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include a semiconductor device in which data are stored, and a memory controller for communicating with the semiconductor device, sequentially processing tasks included in a descriptor, detecting an error section by checking the tasks in reverse order when an error occurred in the tasks, and reprocessing the tasks included in the detected error section.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 10404820
    Abstract: Described herein are systems, devices, and methods for content delivery on the Internet. In certain non-limiting embodiments, a caching model is provided that can support caching for indefinite time periods, potentially with infinite or relatively long time-to-live values, yet provide prompt updates when the underlying origin content changes. Origin-generated tokens can drive the process of caching, and can be used as handles for later invalidating origin responses within caching proxy servers delivering the content. Tokens can also be used to control object caching behavior at a server, and in particular to control how an object is indexed in cache and who it may be served to. Tokens may indicate, for example, that responses to certain requested URL paths are public, or may be used to map user-id in a client request to a group for purposes of locating valid cache entries in response to subsequent client requests.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: September 3, 2019
    Assignee: Akamai Technologies, Inc.
    Inventors: Martin T. Flack, Stephen L. Ludin, Moritz M. Steiner
  • Patent number: 10383160
    Abstract: The present disclosure discloses a data processing method, apparatus, and device. The method includes: sending, by a user equipment UE, updated metadata; obtaining a metadata index value corresponding to the updated metadata; and broadcasting, by the UE, the obtained metadata index value.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: August 13, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Qiang Yi, Guowei Ouyang, Hui Jin, Yue He
  • Patent number: 10345890
    Abstract: A task management method and device where the method may include determining, according to a foreground task, a first scenario corresponding to the foreground task, searching for at least one background task corresponding to the first scenario, when the first scenario corresponding to the foreground task is in a first list, where the first list includes a scenario in which task limitation is allowed, and performing limitation processing on the at least one background task corresponding to the first scenario, where the limitation processing refers to processing for reducing system resource usage, and the method may reduce power consumption and power loss of a device.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 9, 2019
    Assignee: HUAWEI DEVICE CO., LTD.
    Inventors: Konggang Wei, Yu Peng, Jing Zhao
  • Patent number: 10255093
    Abstract: Various embodiments are generally directed to providing virtualization using relatively minimal processing and storage resources to enable concurrent isolated execution of multiple application routines in which one of the application routines is made visible at a time. An apparatus to virtualize an operating system includes a processor component, a visibility checker for execution by the processor component to make a visibility check call to a kernel routine to request an indication of whether an instance of a framework routine that comprises the visibility checker is visible, and resource access code of the instance for execution by the processor component to perform a resource access operation to access a hardware component based on the indication and on receipt of an application programming interface (API) call from an application routine that specifies an API function to access the hardware component. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: April 9, 2019
    Assignee: INTEL CORPORATION
    Inventor: Shoumeng Yan
  • Patent number: 10200330
    Abstract: Techniques for ephemeral message are described. In one embodiment, an apparatus may comprise a delayed-action worker module operative to wake according to a wake timer; determine a current update object for a delayed-action cursor for a recipient update queue for a messaging system, the delayed-action cursor associated with an action delay for the recipient update queue; determine a delayed-action activity for the current update object; perform the delay-action activity for the current update object; determine a next update object for the delayed-action cursor for the recipient update queue; and determine a next wake timer for the delayed-action worker module based on the action delay and a creation time for the next update object. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: February 5, 2019
    Assignee: FACEBOOK, INC.
    Inventors: Matthew Steiner, Jeremy Fein, Erik Murphy-Chutorian, Ting Yang, Pierre-Luc Bertrand, Neil John Fulwiler
  • Patent number: 10140149
    Abstract: A method for a transactional commit in a storage unit is provided. The method includes receiving a logical record from a storage node into a transaction engine of a storage unit of the storage node and writing the logical record into a data structure of the transaction engine. The method includes writing, to a command queue of the transaction engine, an indication to perform an atomic update using the logical record and transferring each portion of the logical record from the data structure of the transaction engine to non-persistent memory of the storage unit as a committed transaction. A storage unit for a storage system is also provided.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: November 27, 2018
    Assignee: Pure Storage, Inc.
    Inventors: John Hayes, Brian Gold, Shantanu Gupta, Robert Lee, Hari Kannan
  • Patent number: 10095765
    Abstract: The present disclosure describes techniques and apparatuses for a hardware-implemented Adelson-Velskii and Landis' (AVL) tree module. In some aspects, commands are received at the AVL tree module that request operations be performed for an AVL tree table stored in memory. Each command is written to one of multiple hardware threads of the AVL tree module that perform AVL tree operations by causing records of the AVL tree table to be read from memory using a single read operation and then written to the AVL tree module, modifying those records without accessing memory, and causing modified records to be written back to memory using a single write operation. Once a command is written to a hardware thread, the hardware thread can perform the corresponding AVL tree operation. After the AVL tree operation is performed, results are returned to the requesting agent to indicate whether the AVL tree operation was performed successfully.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: October 9, 2018
    Assignee: Marvell International Ltd.
    Inventors: Tianan Tim Ma, Timothy J. Donovan
  • Patent number: 10089266
    Abstract: Disclosed herein is a technique for maintaining a responsive user interface for a user while preserving battery life of a user device by dynamically determining the interrupt rate/interrupt time at the user device. Based on priority tier information associated with the I/O requests along with the directionality and size of the I/O requests, a determination can be made regarding how the interrupt rate/interrupt time can be adjusted to achieve acceptable user interface (UI) responsiveness and maximum power savings.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: October 2, 2018
    Assignee: Apple Inc.
    Inventors: Christopher J. Sarcone, Manoj K. Radhakrishnan, Etai Zaltsman
  • Patent number: 10063652
    Abstract: Described herein are systems, devices, and methods for content delivery on the Internet. In certain non-limiting embodiments, a caching model is provided that can support caching for indefinite time periods, potentially with infinite or relatively long time-to-live values, yet provide prompt updates when the underlying origin content changes. In one approach, an origin server can annotate its responses to content requests with tokens, e.g., placing them in an appended HTTP header or otherwise. The tokens can drive the process of caching, and can be used as handles for later invalidating the responses within caching proxy servers delivering the content. Tokens may be used to represent a variety of kinds of dependencies expressed in the response, including without limitation data, data ranges, or logic that was a basis for the construction of the response.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: August 28, 2018
    Assignee: Akamai Technologies, Inc.
    Inventors: Martin T. Flack, Moritz M. Steiner, Stephen L. Ludin, Jozef Hatala
  • Patent number: 9961143
    Abstract: Techniques are described for providing client computing nodes with enhanced access to data from remote locations, such as by providing and using local capabilities specific to the remote locations. In at least some situations, the access of a client computing node to data from a remote location may be enhanced by automatically performing activities local to the client computing node that improve the efficiency of communications sent between the client computing node and the remote location. As one example, access to data from a remote service may be enhanced by locally performing activities specific to the remote service, such as by using information about the remote service's internal mechanisms to cause the desired data to be provided from internal storage devices of the remote service without passing through front-end or other intermediate devices of the remote service while traveling to the client computing node.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: May 1, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Allan H. Vermeulen, Luis Felipe Cabrera, Peter N. DeSantis
  • Patent number: 9940244
    Abstract: A system and method of improved storage request handling in host-side caches includes a host-side cache with a cache controller, a plurality of request queues, and a cache memory. The cache controller is configured to receive a storage request, assign a priority to the storage request based on a queuing policy, insert the storage request into a first request queue selected from the plurality of request queues based on the assigned priority, extract the storage request from the first request queue when the storage request is a next storage request to fulfill based on the assigned priority, forward the storage request to a storage controller, and receive a response to the storage request from the storage controller. The queuing policy is implemented using a rule-based policy engine. In some embodiments, the cache controller is further configured to update one or more monitoring metrics based on processing of the storage request.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: April 10, 2018
    Assignee: NETAPP, INC.
    Inventors: Robert Quimbey, John Fullbright
  • Patent number: 9870275
    Abstract: Provided are a computer program product, system, and method for managing processor threads of a plurality of processors. In one embodiment, a parameter of performance of the computing system is measured, and the configurations of one or more processor nodes are dynamically adjusted as a function of the measured parameter of performance. In this manner, the number of processor threads being concurrently executed by the plurality of processor nodes of the computing system may be dynamically adjusted in real time as the system operates to improve the performance of the system as it operates under various operating conditions. It is appreciated that systems employing processor thread management in accordance with the present description may provide other features in addition to or instead of those described herein, depending upon the particular application.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: January 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 9721122
    Abstract: The present disclosure relates to a method and a system for performing secure read/write operations in the pluggable flash storage device. In one embodiment, a request for at least writing and reading of data in/from the pluggable flash storage device is received. Upon receiving the request for writing data, the storage device is authenticated based on a predetermined signature of the pluggable flash storage device. Upon authenticating the storage device, the at least one of user and the storage controller who made the request is also authenticated and write operation is performed based on successful authentication of the at least one of the user and the storage controller. By way of establishing secure communication between the storage device and the user or the storage controller during the read/write operation the hacking of the data in the storage device or use of the storage device with wrong intent is avoided.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: August 1, 2017
    Assignee: WIPRO LIMITED
    Inventor: Madhukar Gunjan Chakhaiyar
  • Patent number: 9671977
    Abstract: In one embodiment, a method for managing data includes receiving migration information that describes movement of data stored to a direct access storage device (DASD) during a data migration operation that causes at least one portion of the data to be moved from a first location in a first tier of a multi-tier file system to a second location in a second tier of the multi-tier file system, determining whether to swap data usage statistics for the second location with data usage statistics for the first location, and swapping the data usage statistics for the second location with the data usage statistics for the first location when the determination is to swap the data usage statistics. Other systems, methods, and computer program products for managing data in a multi-tier file system are described according to more embodiments.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: June 6, 2017
    Assignee: International Business Machines Corporation
    Inventors: John T. Olson, Sandeep R. Patil, Riyazahamad M. Shiraguppi, Gail A. Spear
  • Patent number: 9626317
    Abstract: An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: April 18, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Tommaso Bacigalupo, Torsten Hinz
  • Patent number: 9619303
    Abstract: A controller has a cache to store data associated with an address that is subject to conflict resolution. A conflict resolution queue stores information relating to plural transactions, and logic reprioritizes the plural transactions in the conflict resolution queue to change a priority of a first type of transaction with respect to a priority of second type of transaction.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: April 11, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Harvey Ray, Christopher Wesneski, Craig Warner
  • Patent number: 9471222
    Abstract: Embodiments relate to method and computer program products which prioritize the logical units in a subgroup. Thereafter, in case of abnormal operation of the process for copying the consistency group from primary storage to secondary storage, low priority logical units of the subgroups of the consistency group are not copied from primary storage to secondary storage.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael E. Browne, Nancy J. Finn, Christina A. Lara, Maria R. Ward
  • Patent number: 9471254
    Abstract: A storage module and method for adaptive burst mode are provided. In one embodiment, a storage module is provided comprising a memory and a controller. The controller is configured to receive a plurality of write commands from a host controller in communication with the storage module, store the plurality of write commands in a command queue in the storage module, and choose one of a plurality of burst modes in which to operate the memory based on how many write commands are stored in the command queue.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: October 18, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Amir Shaharabany, Tal Heller, Hadas Oshinsky, Enosh Levi, Einav Pnina Zilberstein, Judah Gamliel Hahn
  • Patent number: 9466048
    Abstract: Legal professionals often conduct online research as part of their efforts to produce documents, such as legal briefs. The present inventor recognized that online research tools and desktop applications, such as word processors, are functionally isolated from each other, forcing users to awkwardly switch between them as they work. Accordingly, the inventor devised, among other things, an exemplary toolbar that resides adjacent an active application window, such as a word processor. In operation, a user selects one or portions of text, such as a name or fact pattern, in the window, and activates the toolbar using a right-click command. Upon activation, a customizable menu is displayed, enabling the user to select from one or more listed workflow tasks and ultimately to cause an online research system to return search results based on the task and text selections.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: October 11, 2016
    Assignee: Thomson Reuters Global Resources
    Inventor: Trace Liggett
  • Patent number: 9459796
    Abstract: Embodiments relate to method and computer program products which prioritize the logical units in a subgroup. Thereafter, in case of abnormal operation of the process for copying the consistency group from primary storage to secondary storage, low priority logical units of the subgroups of the consistency group are not copied from primary storage to secondary storage.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: October 4, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael E. Browne, Nancy J. Finn, Christina A. Lara, Maria R. Ward
  • Patent number: 9461930
    Abstract: Described embodiments classify packets received by a network processor. A processing module of the network processor generates tasks corresponding to each received packet. A scheduler generates contexts corresponding to tasks received by the packet classification processor from corresponding processing modules, each context corresponding to a given flow, and stores each context in a corresponding per-flow first-in, first-out buffer of the scheduler. A packet modifier generates a modified packet based on threads of instructions, each thread of instructions corresponding to a context received from the scheduler. The modified packet is generated before queuing the packet for transmission as an output packet of the network processor, and the packet modifier processes instructions for generating the modified packet in the order in which the contexts were generated for each flow, without head-of-line blocking between flows.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Steven J. Pollock, Deepak Mital, James T. Clee
  • Patent number: 9405688
    Abstract: Method, apparatus and system for handling address conflicts in distributed memory fabrics. Memory access requests originating from caching agents and Input/Output (I/O) agents in a computer system are serviced concurrently through use of a distributed memory fabric architecture employing parallel pipelines while maintaining memory coherency for cachelines associated with the caching agents and enforcing memory access ordering for memory access requests originating from I/O agents.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: August 2, 2016
    Assignee: Intel Corporation
    Inventors: Ramadass Nagarajan, Robert G. Milstrey, Michael T. Klinglesmith
  • Patent number: 9406368
    Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method of managing memory includes determining a temperature associated with the memory and determining a level of write queue utilization associated with the memory. A write operation may be performed based on the level of write queue utilization and the temperature.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: August 2, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers, Vijayalakshmi Srinivasan
  • Patent number: 9351899
    Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method of managing memory includes determining a temperature associated with the memory and determining a level of write queue utilization associated with the memory. A write operation may be performed based on the level of write queue utilization and the temperature.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 31, 2016
    Assignee: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Jude A. Rivers, Vijayalakshmi Srinivasan
  • Patent number: 9319492
    Abstract: A method of controlling at least one message including at least one command and response is disclosed. The method includes transmitting a command from a sender to a receiver, transmitting an initial response indicating acknowledgement for receiving the command from the receiver to the sender, and transmitting a subsequent response being after the initial response as one of a plurality of responses the command from the receiver to the sender.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: April 19, 2016
    Assignee: LG ELECTRONICS INC.
    Inventors: Juhyung Son, Seunghyup Ryoo, Jaejoon Park
  • Patent number: 9317720
    Abstract: Provided is a method, system, and program for enabling access to data in a storage medium within one of a plurality of storage cartridges capable of being mounted into a interface device. An association is provided of at least one coding key to a plurality of storage cartridges. A determination is made of one coding key associated with one target storage cartridge, wherein the coding key is capable of being used to access data in the storage medium within the target storage cartridge. The determined coding key is encrypted. The coding key is subsequently decrypted to use to decode and code data stored in the storage medium.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: April 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Glen Alan Jaquette
  • Patent number: 9286363
    Abstract: A facility for navigating within a body of data using one of a number of distinct browse graphs is described. Initially, a navigation request is received. Based upon information contained in the received navigation request, the facility selects one of the plurality of browse graphs. In response to user input, the facility browses the body of data using the selected browse graph. The browse graphs may each correspond to a collection of the body of data, such as a website.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: March 15, 2016
    Assignee: A9.com, Inc.
    Inventors: Robert W. McDade, Anne K. Krook, Bonnie Bouman
  • Patent number: 9218467
    Abstract: A method of randomizing locations of variables in a stack includes: identifying a plurality of stack locations corresponding to a plurality of variables; shuffling the stack locations of the variables to produce shuffled stack locations; and updating the stack locations of the variables with the shuffled stack locations.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: December 22, 2015
    Assignee: RAYTHEON CYBER PRODUCTS, LLC
    Inventors: David Matthews, Robert Martz
  • Patent number: 9208116
    Abstract: Multiple variants of a data processing system, which maintains I/O priority from the time a process makes an I/O request until the hardware services that request, will be described. In one embodiment, a data processing system has one or more processors having one or more processor cores, which execute an operating system and one or more applications of the data processing system. The data processing system also can have one or more non-volatile memory device coupled to the one or more processors to store data of the data processing system, and one or more non-volatile memory controller coupled to the one or more processors. The one or more non-volatile memory controller enables a transfer of data to at least one non-volatile memory device, and the priority level assigned by the operating system is maintained throughout the logical data path of the data processing system.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: December 8, 2015
    Assignee: Apple Inc.
    Inventors: Joseph Sokol, Jr., Manoj Radhakrishnan, Matthew J. Byom, Robert Hoopes, Christopher Sarcone
  • Patent number: 9201804
    Abstract: A multi-queue cache is configured with an initial configuration, where the initial configuration includes one or more queues for storing data items. Each of the one or more queues has an initial size. Thereafter, the multi-queue cache is operated according to a multi-queue cache replacement algorithm. During operation, access patterns for the multi-queue cache are analyzed. Based on the access patterns, an updated configuration for the multi-queue cache is determined. Thereafter, the configuration of the multi-queue cache is modified during operation. The modifying includes adjusting the size of at least one of the one or more queues according to the determined updated configuration for the multi-queue cache.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: December 1, 2015
    Assignee: Google Inc.
    Inventor: Zoltan Egyed
  • Patent number: 9146690
    Abstract: System and methods are provided for dynamically managing a first-in/first-out (FIFO) command queue of a system controller. One or more commands are received into the command queue, a command being associated with a priority parameter. A current command first in line to be executed in the command queue is determined, the current command being associated with a first priority parameter. A second command associated with a second priority parameter is determined, the second priority parameter being largest among priority parameters associated with the one or more commands. A final priority parameter for the current command is computed based at least in part on the second priority parameter.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: September 29, 2015
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Jun Zhu, Joseph Jun Cao, Tsung-Ju Yang, Ruoyang Lu
  • Patent number: 9143351
    Abstract: Methods, systems and data structures for determining a token master on a ring network are provided. According to one embodiment, determining a token master on a ring network includes receiving a packet containing a network token at a first node on the network. If the network token does not arrive within a preselected timeout period, generating an arbitration token. If the packet contains an arbitration token, determining if the arbitration token was modified by a higher priority node of the network and if not, setting the first node as a token master and converting the arbitration token to a packet transmission token. Arbitration tokens are used to identify a token master that is responsible for generating a packet transmission token onto the network, whereas the packet transmission token authorizes a transmitting node that has most recently received the packet transmission token to transmit locally generated packets onto the network.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: September 22, 2015
    Assignee: Fortinet, Inc.
    Inventor: Tim Millet
  • Patent number: 9104317
    Abstract: An aspect of this invention is a computer system, including: a storage apparatus for allocating real storage areas of a plurality of tiers of a tiered real storage area pool to a volume, and migrating and relocating data within the volume between the plurality of tiers; and a host apparatus that accesses the volume provided by the storage apparatus. The host apparatus is configured to refer to tier information including information on a corresponding one of the plurality of tiers to which an access destination address within the volume belongs to identify the corresponding one of the plurality of tiers to which the access destination address belongs and refer to settings predetermined for the plurality of tiers to perform I/O control for the access destination address based on settings of the identified corresponding one of the plurality of tiers.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: August 11, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Akira Hayakawa, Takaki Nakamura, Keiichi Matsuzawa, Takayuki Fukatani