Physical Position Patents (Class 710/43)
  • Patent number: 9524778
    Abstract: Device selection schemes in multi-chip package NAND flash memory systems are provided. A memory system is provided that has a memory controller, and a number of memory devices connected to the controller via a common bus with a multi-drop connection. The memory controller performs device selection by command. A corresponding memory controller is provided which performs device selection by command. Alternatively, device selection is performed by address. A memory device is provided use in memory system comprising a memory controller, and a number of memory devices inclusive of the memory device connected to the controller via a common bus with a multi-drop connection. The memory device has a register containing a device identifier, and a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match. The memory device is selected if the device identifier comparator determines there is a match.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: December 20, 2016
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Jin-Ki Kim
  • Patent number: 9519532
    Abstract: A method, processor, and computer system for handling interrupts within a hierarchical register structure. The method includes receiving at a root-level register an indication of an interrupt occurring at a lower level register in the register structure, using a system interrupt handler to invoke an error handler assigned to a set of registers of the structure that includes the lower level register, and using the invoked error handler to handle the interrupt and return to the system interrupt handler.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: December 13, 2016
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
    Inventors: Jonathan L. Kaus, Adam C. Lange-Pearson, Gary R. Ricard, Jaimeson Saley
  • Patent number: 9253286
    Abstract: A system and method of data programming involves a computer generating a tabular storage structure that includes data and code. The code is defined by a column of the tabular storage structure. The computer can then execute a program using the tabular storage structure. The code of the tabular storage structure governs an operation of the program.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: February 2, 2016
    Inventors: Blaine A. Bell, Steven K. Feiner
  • Patent number: 8959256
    Abstract: Bus lines 20, 21 are connected to peripheral devices 1, 2 such that the polarities of the bus lines are replaced with each other according to an attachment position, and information acquisition units 16-1, 16-2 determine an attachment position P1 if the polarities of a connector terminal 10-1 (or 10-2) and a connector terminal 11-1 (or 11-2) are plus and minus, and determines an attachment position P2 if minus and plus.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: February 17, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Toshiyuki Yamashita, Yuji Hiraoka
  • Patent number: 8949567
    Abstract: A plurality of addressable memory tiles each comprise one or more cross-point arrays. Each array comprises a plurality of non-volatile resistance-change memory cells. A controller is configured to couple to the array and to a host system. The controller is configured to perform receiving, from the host system, one or more data objects each having a size equal to a predetermined logical block size, and storing the one or more data objects in a corresponding integer number of one or more of the memory tiles.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: February 3, 2015
    Assignee: Seagate Technology LLC
    Inventors: Antoine Khoueir, Jon D. Trantham, Kevin Gomez, Ara Patapoutian
  • Patent number: 8930593
    Abstract: A storage system and method for setting parameters and determining latency in a chained device system. Storage nodes store information and the storage nodes are organized in a daisy chained network. At least one of one of the storage nodes includes an upstream communication buffer. Flow of information to the storage nodes is based upon constraints of the communication buffer within the storage nodes. In one embodiment, communication between the master controller and the plurality storage nodes has a determined maximum latency.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: January 6, 2015
    Assignee: Spansion LLC
    Inventors: Seiji Miura, Roger Dwain Isaac
  • Patent number: 8918557
    Abstract: A SAS expander configured to operate as a SAS expander hub receives IO requests from a plurality of connected SAS expanders. Each SAS expander determines if it is capable of servicing a received IO request and sending such IO requests to the SAS expander hub if necessary. The SAS expander hub relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: December 23, 2014
    Assignee: LSI Corporation
    Inventor: Brett J. Henning
  • Patent number: 8904052
    Abstract: An input port for an electronic device for receiving different types of connectors, memory cards, or plugs. The input port includes an outer wall defining a receiving aperture, a substrate positioned within the receiving aperture. A first set of contacts is positioned on the substrate at a first depth into the receiving aperture and a second set of contacts is positioned on a first surface of the outer wall at a second depth into the receiving aperture. The first set of contacts is configured to communicate with a first connector and the second set of contacts is configured to communicate with a second connector.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: December 2, 2014
    Assignee: Apple Inc.
    Inventor: Changsoo Jang
  • Patent number: 8862904
    Abstract: An embodiment of the present invention provides an apparatus, comprising a network adapter configured for wireless communication using more than one technology using distributed management and wherein the network adapter is configured to share a plurality of shared hardware components by automatically turning all other comms to OFF when one comm is turned to ON.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: October 14, 2014
    Assignee: Intel Corporation
    Inventors: Boris Ginzburg, Sharon Ben-Porath, Oren Kaidar, Shlomo Avital, Avishay Sharaga, Max Fudim, Eran Friedlander
  • Patent number: 8843672
    Abstract: An access method includes: obtaining, by a computer, a result of monitoring a busy rate and a number of access operations per unit time of a storage device, the storage device having a first storage area and a second storage area; calculating a characteristic of correlation between the busy rate and the number of access operations per unit time based on the result; calculating a second number of access operations per unit time based on the characteristic of the correlation such that a sum of a first busy rate corresponding to a first number of access operations per unit time and a second busy rate corresponding to a second number of access operations per unit time becomes equal to or lower than a given busy rate; and controlling a number of operations to access the second storage area per unit time based on the second number of access operations.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: September 23, 2014
    Assignee: Fujitsu Limited
    Inventors: Kazuichi Oe, Kazutaka Ogihara, Yasuo Noguchi, Tatsuo Kumano, Masahisa Tamura, Yoshihiro Tsuchiya, Takashi Watanabe, Toshihiro Ozawa
  • Publication number: 20140229639
    Abstract: In an apparatus which includes a plurality of processing modules connected via a ring-shape bus, if a plurality pieces of pipeline processing to be processed in a different order is allocated to a plurality of processing modules, the transfer efficiency may decrease when an amount of data transferred from one of the processing modules to a post-stage module exceeds a processing capacity of the post-stage module. Accordingly, a module positioned on the preceding side in the pipeline processing controls a transmission interval of processed data so that the post-stage module can receive the data processed by the preceding module.
    Type: Application
    Filed: April 28, 2014
    Publication date: August 14, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hiroyasu Watanabe, Hirowo Inoue, Hisashi Ishikawa
  • Patent number: 8458374
    Abstract: A method and an arrangement for configuration of a mobile appliance in a communication arrangement, with a communication address that is linked to its location in each case being assigned to the mobile appliance are provided. For this purpose, the location of the mobile appliance is determined in a first step, a configuration which is linked to the determined location is checked in a second step from a database, and this determined configuration is assigned to the mobile appliance in a third step.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: June 4, 2013
    Assignee: Siemens Enterprise Communications GmbH & Co. KG
    Inventor: Jurgen Luers
  • Patent number: 8417849
    Abstract: A method to adjust a multi-path device reservation by supplying a computing device and a storage controller interconnected with a communication link. The method further reserves a data storage device in communication with the storage controller, where that data storage device reservation is held by a first communication path group comprising a first plurality of communication paths configured in the communication link. If the method detects a failed communication path configured in the first communication path group, the method configures a second communication path group by removing the failed communication path from the first communication path group, wherein the second communication path group maintains the data storage device reservation.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: April 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Clint Alan Hardy, Matthew Joseph Kalos, Richard Anthony Ripberger
  • Patent number: 8386655
    Abstract: A method and an arrangement for configuration of a mobile appliance in a communication arrangement, with a communication address that is linked to its location in each case being assigned to the mobile appliance are provided. For this purpose, the location of the mobile appliance is determined in a first step, a configuration which is linked to the determined location is checked in a second step from a database, and this determined configuration is assigned to the mobile appliance in a third step.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: February 26, 2013
    Assignee: Siemens Enterprise Communications GmbH & Co. KG
    Inventor: J├╝rgen Luers
  • Patent number: 8332549
    Abstract: A method for communication between an initiator system and a block storage cluster may include receiving a first input/output (I/O) request from the initiator system. The method may also include sending a referral response from a first storage system included in a plurality of storage systems of the block storage cluster to the initiator system when data associated with the first I/O request is stored in more than one storage system of the plurality of storage systems of the block storage cluster. Additionally, the method may include directing a referral I/O to the first storage system and the second storage system for transferring data to or transferring data from the first storage system and the second storage system, and transferring data associated with the referral I/O to or transferring data associated with the referral I/O from the first storage system and the second storage system.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: December 11, 2012
    Assignee: LSI Corporation
    Inventors: Andrew J. Spry, Ross Zwisler, Gerald J. Fredin, Kenneth J. Gibson
  • Patent number: 8315232
    Abstract: An apparatus and a method to display the availability of a wireless LAN, in which information about an area supporting a wireless local area network (LAN) is provided to a user carrying a mobile terminal, such as a mobile phone through a mobile phone network in the form of text, voice or images. The apparatus includes: an input unit to receive a command to request a search for a wireless LAN available in a designated location from a user; a packet generating unit to generate an information request packet according to the received command; a communicating unit to transmit the generated information request packet and to receive a result of the requested search for the available wireless LAN, in response to the transmitted information request packet; and a display unit to display the received result of the search.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: November 20, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Soo-hong Park
  • Patent number: 8234661
    Abstract: An interface system includes a first driver module that communicates through a bus with a first peripheral card when the bus is in a first mode. A second driver module communicates through the bus with a second peripheral card when the bus is in a second mode. A bus control module receives a communication notification signal from the second peripheral card when the first peripheral card is communicating with the first driver module. The communication notification signal does not interfere with the communication of the first peripheral card and the first driver module. The bus control module switches the bus between first and second modes in response to the communication notification signal.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: July 31, 2012
    Assignee: Marvell International Ltd.
    Inventors: Frank Huang, James Jan, Robert Lee, Bing Zhao, Yao Chen
  • Patent number: 8230066
    Abstract: The present invention relates to a computerized method and respective system for servicing a request for a networked data transfer from a client system, which is able to be serviced on a particular server system being a member of a plurality of server systems dedicated to service said client requests, in which the server systems are connected via a network and share information about a plurality of client systems, and in which the service is known to consume some non-negligible network bandwidth. In order to balance required bandwidth peaks and to improve user comfort, it is proposed to establish an inter-server communication, which determines the best suited server for providing the service, reflecting pre-collected client history data, favorite service provision times, etc. The method can be applied primarily for backup of data from distributed client systems, or for improving print services.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: July 24, 2012
    Assignee: International Business Machines Corporation
    Inventor: Jochen Heil
  • Patent number: 8219717
    Abstract: A port setting method of an application system comprises: requesting a naming server for object information corresponding to name information of the other components upon data transmission to the other components; determining whether there exists consistent information based on the object information of the other components received from the naming server; if there exists consistent information, selecting a first and certain protocol, and otherwise, selecting a second protocol; and establishing a connection with the other components by use of the selected protocol. The actual location of the components can be sensed based on Endpoint information of IOR without adding no particular information to the domain profile (xml profile), and a more efficient protocol can be selected depending on the position of each component, thereby enhancing data transmission performance and efficiency in SCA port communications between components.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: July 10, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Chul Oh, Nam Hoon Park
  • Patent number: 8205023
    Abstract: A device includes a group of resources, where each resource is to determine a priority rank position, among the group of resources, based on which other resources of the group of resources are available. The device also includes a group of requestors of the resources, where each requestor is to determine a priority rank position, among the group of requestors, based on which other requestors are active and based on each active requestor's priority. The device also includes a processing component to receive the priority rank position from each resource and the priority rank position from each requestor; assign pairs of the resources and the requestors based on the priority rank position of each resource and the priority rank position of each requestor; and assign work to resources of the group of resources based on the pairs.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: June 19, 2012
    Assignee: Juniper Networks, Inc.
    Inventor: Robert Rhoades
  • Patent number: 7953912
    Abstract: A method of guided attachment of hardware accelerators to slots of a computing system includes dividing a first group of hardware accelerators into a plurality of priority classes, dividing a first group of slots of the computing system into a plurality of hierarchical tiers, and attaching each hardware accelerator of the first group of hardware accelerators to a slot matched to the hardware accelerators based on comparison of a priority class of the hardware accelerator and a hierarchical tier of the slot.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: May 31, 2011
    Assignee: International Business Machines Corporation
    Inventors: Rajaram B. Krishnamurthy, Hong Deng, Tjomas A. Gregg, John P. Rankin
  • Patent number: 7797468
    Abstract: In certain, currently available data-storage systems, incoming commands from remote host computers are subject to several levels of command-queue-depth-fairness-related throttles to ensure that all host computers accessing the data-storage systems receive a reasonable fraction of data-storage-system command-processing bandwidth to avoid starvation of one or more host computers. Recently, certain host-computer-to-data-storage-system communication protocols have been enhanced to provide for association of priorities with commands. However, these new command-associated priorities may lead to starvation of priority levels and to a risk of deadlock due to priority-level starvation and priority inversion. In various embodiments of the present invention, at least one additional level of command-queue-depth-fairness-related throttling is introduced in order to avoid starvation of one or more priority levels, thereby eliminating or minimizing the risk of priority-level starvation and priority-related deadlock.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: September 14, 2010
    Assignee: Hewlett-Packard Development Company
    Inventors: George Shin, Rajiv K. Grover, Santosh Ananth Rao
  • Patent number: 7562185
    Abstract: A method and system for accessing a storage medium that factors in read statistics of previous reads of the storage medium is provided. An access system tracks read statistics generated from previous attempts to read data of the storage medium, which may be stored on a per-unit basis. When the access system receives a request to read data of the storage device, the access system may generate a read plan for the read based on analysis of the read statistics. A read plan may specify the initial speed of the attempt to read the data. The access system uses the read statistics to help reduce the time needed to read a unit of data from the storage medium.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: July 14, 2009
    Assignee: Microsoft Corporation
    Inventors: Hakuro Matsuda, John M. Harding
  • Patent number: 7366833
    Abstract: In information storage systems in which data retrieval requires movement of at least one physical element, a measurable amount of time is required to reposition that physical element in response to each data write or read request. After selecting one or more data requests for dispatch based solely on an approaching or past due time deadline, additional requests are identified for data to be read or written to locations which are in close proximity to previously scheduled requests, previously selected additional requests, or the present position of the moveable physical element, obviating the need to expend the full amount of time required to accelerate the physical element and then decelerate the physical element to position it over the desired area within the information storage system. In this manner, data may be transferred to or retrieved from an information storage system more efficiently with less expenditure of time.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: April 29, 2008
    Assignee: International Business Machines Corporation
    Inventors: Anupam Chanda, Ramakrishnan Rajamony, Freeman Leigh Rawson, III
  • Patent number: 7340542
    Abstract: A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: March 4, 2008
    Inventors: William C. Moyer, Brett W. Murdock
  • Patent number: 7254674
    Abstract: A method of respectively reading and writing data to and from a plurality of physical disk units in response to I/O requests from a host computing system includes establishing a logical disk group having a number of logical disk elements, mapping each of the logical disk elements to corresponding physical disk units, receiving from the host computing system an I/O request for data to select a one of the number of logical disk elements, accessing the physical disk unit corresponding to the selected one logical disk to access for the data, and transferring the accessed data to the host computing system.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: August 7, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Takao Satoh, Shigeo Honma, Yoshihiro Asaka, Yoshiaki Kuwahara, Hiroyuki Kitajima
  • Patent number: 7234005
    Abstract: A method of setting a parameter of a peripheral device, for controlling an operation of the peripheral device includes collecting and storing a command issued for the peripheral device by an external device, analyzing a command issue pattern for the peripheral device based on the stored command, and determining a most proper value of the parameter based on the command issue pattern. The most proper value of the parameter determined is set as a parameter for controlling the operation of the peripheral device.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: June 19, 2007
    Assignee: Fujitsu Limited
    Inventor: Nobuaki Yoshitake
  • Patent number: 7194656
    Abstract: Systems and methods for optimizing storage network functionality. The methods and systems of the present invention are particularly useful for optimizing storage network performance for cases in which some components of the network may be separated by significant distances and/or which include communication links with relatively limited bandwidth. In certain aspects, the present invention provides methods and systems for implementing access to and management of geographically distributed storage resources through multiple peer-to-peer storage network array management functions (AMFs) that may also be geographically distributed. The methods and systems of the present invention, in certain aspects, provide geographically aware cache sharing, cache replication, cache coherence, traffic routing, redundancy group structure, source and destination selection, pre-fetching of data, message gathering and other useful features.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: March 20, 2007
    Assignee: YottaYotta Inc.
    Inventor: Geoff Hayward
  • Patent number: 7181607
    Abstract: In response to requests for I/O processing sent from a computer, I/O which should be processed at a priority is enabled to be processed without being affected by other processing, by classifying I/O into those to be processed at a priority and those not to be processed at a priority. The storage control apparatus comprises an I/O processing controller with a memory that is common for the whole controller. The storage control apparatus manages information for dividing and controlling a plurality of I/O processes as priority and non-priority in that memory and operates while suppressing non-priority I/O processing on the basis of information in the memory.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: February 20, 2007
    Assignees: Hitachi, Ltd., Hitachi Software Engineering Co., Ltd.
    Inventors: Takeshi Ido, Youichi Gotoh, Shizuo Yokohata, Shigeo Honma, Toshiyuki Yoshino
  • Patent number: 7103783
    Abstract: A System for providing data security in a first device driver operably installed in a computer operating system having a layered plurality of device drivers (81, 82, 83, 84) for accessing data in a data storage device. The first device driver detects an I/O request, and determines whether the first device driver is functionally uppermost in the layered plurality of device drivers. If the first device driver is functionally uppermost in the layered plurality of device drivers, the method performs the I/O request (80) in the first device driver. If the device driver is not functionally uppermost in the layered plurality of device drivers, the method denies the I/O request in the first device driver, and allows the I/O request to be performed by the next lowest-level driver in the layered plurality of device drivers.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: September 5, 2006
    Assignee: Pinion Software, Inc.
    Inventors: George Friedman, Robert Phillip Starek, Carlos A. Murdock
  • Patent number: 7043605
    Abstract: Performance and reliability as a disk array system can be always kept optimal even when a group construction of disk drives is changed. The disk array system is connectable to a host and includes a plurality of drives, input/output control portions for controlling data input/output between the host and the drives, a plurality of paths for connecting the drives and the input/output control portions and modules each accommodating a predetermined number of drives. When the number of the drives is increased or decreased, other drives or modules connected to paths different from the paths connected to the drives to be increased or decreased are displayed. When the number of the drives is increased or decreased, other drives accommodated in modules different from the modules accommodating the drives to be increased or decreased are displayed.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: May 9, 2006
    Assignee: Hitachi, Ltd.
    Inventor: Katsuyoshi Suzuki
  • Patent number: 6928501
    Abstract: Methods and apparatus associated with a plurality of serial devices designed to communicate with a bus master in either a daisy chain or a normal configuration are provided. One method includes the step of serially providing a command sequence having a channel identifier to a given device of a plurality of daisy chained devices. The channel identifier is modified as it passes thru each daisy chained device. A specific device is identified or enabled when the channel identifier it receives matches a pre-determined value.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: August 9, 2005
    Assignee: Silicon Laboratories, Inc.
    Inventors: David C. Andreas, Christopher D. Eckhoff, Richard D. Loveman
  • Patent number: 6907499
    Abstract: Systems and methods in a disc drive improve data transfer performance by interrupting disc write operations to service read commands.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: June 14, 2005
    Assignee: Seagate Technology LLC
    Inventors: James Arthur Herbst, Steven Scott Williams, Bradley Ronald Brookes
  • Patent number: 6862640
    Abstract: A multiprocessor system includes a plurality of data processors. Each data processor includes: a data processing core; a memory forming a local portion of a unified memory; and a global memory arbitration logic. Each local portion of the unified memory is dual ported. The global memory arbitration logic arbitrates access to a first port among the corresponding data processing core and a close data processing core. The global memory arbitration logic arbitrates access to a second port of another data processor among data processing cores having a far connection to that local portion of unified memory. The dual port memory is preferably time multiplexed. The global memory arbitration logic grants a local peripheral bus priority access to both ports of the local portion of unified memory.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: March 1, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Patrick J. Smith
  • Patent number: 6807588
    Abstract: A sectioned ordered queue in an information handling system comprises a plurality of queue sections arranged in order from a first queue section to a last queue section. Each queue section contains one or more queue entries that correspond to available ranges of real storage locations and are arranged in order from a first queue entry to a last queue entry. Each queue section and each queue entry in the queue sections having a weight factor defined for it. Each queue entry has an effective weight factor formed by combining the weight factor defined for the queue section with the weight factor defined for the queue entry. A new entry is added to the last queue section to indicate a newly available corresponding storage location, and one or more queue entries are deleted from the first section of the queue to indicate that the corresponding storage locations are no longer available.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: October 19, 2004
    Assignee: International Business Machines Corporation
    Inventors: Tri M. Hoang, Tracy D. Butler, Danny R. Sutherland, David B. Emmes, Mariama Ndoye, Elpida Tzortzatos
  • Patent number: 6795878
    Abstract: A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further comprises selecting a first cache line out of a plurality of cache lines to be paired with one or more of the remaining of the plurality of cache lines. If a load memory instruction executed after the memory barrier instruction in the first cache line was identified, then the first cache line selected will be paired with a second cache line. If a load memory instruction executed before the memory barrier instruction in the second cache line was identified, then a pair of load memory instructions has been identified. Upon identifying the second load memory instruction, a first and second reload of the first and second cache lines are identified.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: September 21, 2004
    Assignee: International Business Machines Corporation
    Inventors: Aaron Ches Brown, Steven Robert Farago, Robert James Ramirez, Kenneth Lee Wright
  • Patent number: 6795389
    Abstract: An optical information recording medium is provided with a plurality of information layers (2, 3), each of which has a sector structure in which a data area (8, 12) is divided in the circumferential direction by a sector address (9, 13). The positions of the sector addresses (9, 13) of the respective information layers (2, 3) coincide in the circumferential direction. This can prevent errors during reproduction caused by the effect of other information layers and stabilize recording characteristics, resulting in an increased recording capacity of a rewritable recording medium having a plurality of information layers with a sector structure.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: September 21, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenichi Nishiuchi, Ken'ichi Nagata
  • Patent number: 6792485
    Abstract: The invention provides a data output control apparatus which is suitable for allowing detailed information on a network to be readily obtained. A data output control terminal selects one of printing apparatuses corresponding to a data-format-conversion terminal which allows conversion of data associated with a data print request; outputs the data associated with the data print request to the data-format-conversion terminal allowing conversion of the data and corresponding to the printing apparatus; by the data-format-conversion terminal, converts the data associated with the data print request into data which can be printed by the printing apparatus; and outputs the converted data to the printing apparatus. One or more of data-format-conversion terminals is selected in accordance with the transmission load of the Internet, and data-format-conversion processes are executed by the data-format-conversion terminal.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: September 14, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Mikio Aoki, Shinya Taniguchi
  • Patent number: 6782436
    Abstract: A method and apparatus for a communication system for facilitating communication on the network. Identification of a network device, preferably a controller or IO device, is based on a physical location of device. Accordingly, the physical location of the network device is determined by a device locator. The physical location of each network device is used to associate a network identifier, i.e., network address, with the network device to facilitate network communication with other devices. The network identifier is associated with the network device in response to a signal transmitted from the network device requesting the network identifier. A mapping method is used to convert a map of physical locations to one or more address tables so as to allow a controlling station to associate the network identifier with the network device for routing messages to and from the device based on the physical location.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: August 24, 2004
    Inventor: Richard A. Baker
  • Patent number: 6775725
    Abstract: To execute a program in a second chip card, inserted in a terminal in addition to a first chip card, containing data relating to the owner of the first card, the second card communicates with the terminal through exchanges of commands and responses between the two cards, relayed through exchanges of commands and responses, between first card and the terminal. For example, the terminal is a mobile radio telephone terminal with a SIM card as a first card, not requiring any SIM Toolkit protocol interface between the terminal and the second card. Compatibility and adaptation of the second card to the terminal is provided in the preparation for the execution of the program.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: August 10, 2004
    Assignee: Gemplus
    Inventors: Bruno Basquin, Marc Niccolini
  • Patent number: 6771556
    Abstract: The present relief module equipped random access memory avoids the need for enforced idle cycles for the processors, thereby enabling the State Machine to operate at its maximum speed. This relief module equipped random access memory also enables the Central Processing Unit to access the data in the single-port Random Access Memory as required to read and write the data contained therein. This is accomplished by the addition of a single-port Random Access Memory module to the plurality of Random Access Memory modules that are typically specified for a particular application. The extra Random Access Memory module alternates its output with each of the others of the plurality of Random Access Memory modules, on a sequential basis, thereby providing effectively extra clock cycles for each Random Access Memory module.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: August 3, 2004
    Assignee: Lucent Technologies Inc.
    Inventor: Charles Melvin Aden
  • Patent number: 6757751
    Abstract: The density for any generation of Standard In-Line Memory Module (SIMM), or Dual In-Line-Memory Module (DIMM), chipset used to provide computer Random Access Memory (RAM), can be multiplied by surface-mounting multiple banks of SIMMs or DIMMs, where each bank occupies one side of a printed-circuit board (PCB) and at least a second PCB is connected to a first PCB, which is in turn connected through the standard edge connectors to the bus, with the banks connected through shared and controlled input-and-output lines, and wherein a single standard controller directs address-oriented storage to the corresponding portion of the stacked and connected banks.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: June 29, 2004
    Inventor: Harrison Gene
  • Patent number: 6728832
    Abstract: A method of respectively reading and writing data to and from a plurality of physical disk units in response to I/O requests from a host computing system includes establishing a logical disk group having a number of logical disk elements, mapping each of the logical disk elements to corresponding physical disk units, receiving from the host computing system an I/O request for data to select a one of the number of logical disk elements, accessing the physical disk unit corresponding to the selected one logical disk to access for the data, and transferring the accessed data to the host computing system.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: April 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Takao Satoh, Shigeo Honma, Yoshihiro Asaka, Yoshiaki Kuwahara, Hiroyuki Kitajima
  • Patent number: 6697885
    Abstract: An automated direct memory access system is implemented as an advanced ATA host IC for mother board or adapter applications. The system transfers data from two independent ATA channels using the ATA Ultra-100 protocols. The ADMA implements a command chaining technique to de-couple the host command sequence from channel execution. Software builds a command chain for hardware execution. The ADMA hardware independently reads command chain requests from memory and executes the next task on the list. When the ADMA hardware completes a task, it interrupts the host in order to inform the host that the task is complete, but immediately proceeds to the next task without waiting for interrupt servicing by the host.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: February 24, 2004
    Inventor: Anthony E. B. Goodfellow
  • Patent number: 6684264
    Abstract: Apparatus and method for controlling a molding machine includes structure and function for a human machine interface control panel having: (i) a flat panel display screen; (ii) a pointing device; (iii) a plurality of pushbuttons overlaid with or without icons; (iv) a housing containing the above and the associated electronics; (v) structure to uniquely identify each users preferred configuration; (vi) structure to connect to a remote controller for both digital information and video signal communication; (vii) a connection for receiving external power to drive the panel's electronics and display; and (viii) software running in the remote controller to provide all the operating functions of the human machine interface.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: January 27, 2004
    Assignee: Husky Injection Molding Systems, Ltd.
    Inventor: Christopher Wai-Ming Choi
  • Patent number: 6681271
    Abstract: A computer system for multi-type DRAM support includes a first slot for receiving a first type DRAM, a second slot for receiving a second type DRAM, a north bridge chip, and a control circuit. The first slot includes a plurality of first slot pins, and each of them corresponds to a first pin assignment. The second slot includes a plurality of second slot pins, and each of them corresponds to a second pin assignment. The north bridge chip includes a plurality of chip pins, and each of them corresponds to a first and second pin assignment. When the control circuit generates a first control signal, the pin assignments of the chip pins are defined as the first pin assignments. When the control circuit generates a second control signal, the pin assignments of the chip pins are defined as the second pin assignments.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: January 20, 2004
    Assignee: Acer Laboratories, Inc.
    Inventors: Tsai Chih-Hung, Li-Te Cheng, Wu Shun-Cheng, Kun-Feng Cheng, An-Chung Chen, Horng-Sheng Chen
  • Patent number: 6598096
    Abstract: An IEEE 1394 compliant bus controller transfers data packets between connected nodes. The controller includes a processor which divides a series of data into blocks and then stores the blocks in multiple packets (one block per packet). The packets are then transferred over the bus from a source node to a destination node at equal intervals until the entire series of data has been transferred. An initialization prohibition unit prohibits initialization of the nodes during the data transfer which may be caused, for example, by hot plugging (connecting a new node to the bus) during the data transfer.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: July 22, 2003
    Assignee: Fujitsu Limited
    Inventors: Kenji Oi, Takashi Shimizu, Hirotaka Ueno, Hiroshi Takase
  • Patent number: 6542939
    Abstract: In an electrical system having a connector board with at least one electrical connector thereon for receiving an electrical device therein, volumetric vital product parametric data is stored in memory associated with the connector board. The stored volumetric vital product parametric data can be accessed with the electrical system to check for available space for a proposed electrical device, for example. The stored data may include information about dimensional characteristics of the connector board and the at least one electrical connector. This data can be compared with corresponding data for the electrical device to determine compatibility, for example.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: April 1, 2003
    Assignee: International Business Machines Corporation
    Inventors: Thomas James Osten, Paul Edward Movall, Neil Clair Berglund, Nancy Marie Uthke-Schmucki, Patrick Allen Buckland, David Lee Dosch, Stephen Peter Mroz, David G. Lund
  • Patent number: 6519544
    Abstract: IEEE 1394 bus interface circuit 15X comprises a physical layer LSI 37 connected to an IEEE 1394 bus 14, a data capture circuit 22X connected to the physical layer LSI 37 through signal lines to capture data on the signal lines for data analysis, and a coupler (a plug or a socket) 38 to be coupled to a coupler (a socket or a plug) 39 to which a physical layer LSI of an IEEE 1394 bus interface 10 is attached in actual use. With engaging the couplers 39 and 38 to each other, data transmitted between nodes 10 and 13 are captured by the data capture circuit 22X and analyzed in an IEEE 1394 bus analysis apparatus 16. In another IEEE 1394 bus interface circuit, a link power status signal provided to the physical layer circuit from the link layer circuit is fixedly set low, whereby the physical layer circuit is made to function as a repeater, and data received by the physical layer circuit are captured by the link layer circuit and analyzed in the IEEE 1394 bus analysis apparatus.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: February 11, 2003
    Assignee: Fujitsu Limited
    Inventors: Tomohiro Deguchi, Hiroyuki Miyazaki, Hiroyuki Yoshida, Minoru Wano
  • Publication number: 20030002078
    Abstract: A server computer searches for at least one printing-service proving store based on printing-condition information sent form an information terminal, and sends information representing the searched printing-service providing store to the information terminal. After a user selects one printer device based on the information representing the at least one printing-service providing store, the information terminal sends document data to be printed to the server computer. The server computer sends printing data to be printed to the user-selected printer device.
    Type: Application
    Filed: July 1, 2002
    Publication date: January 2, 2003
    Applicant: Ricoh Company, Ltd.
    Inventors: Naohiro Toda, Takashi Rokutanzono, Shinji Nousyo, Tatsuya Niimi