Abstract: A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.

Abstract: A data processing apparatus is provided with a plurality of processing units executing respective streams of program instructions corresponding to respective processing threads. Exception control circuitry controls exception processing for a group of the processing units in response to an exception triggering event. Each of the processing units moves only once and in sequence between normal, in-exception, and done-exception states in response to a given exception event. A group of processing units moves in sequence between states normal, triggering, and completing in response to the exception event. A counter value is used to track the number of processing units which have entered exception processing and then to track the number of processing units which have completed their exception processing.

Abstract: Systems and methods are provided for aligning status indicators on a terminal block of an I/O device by locating the status indicators directly adjacent to or integrated directly within their respective terminals on the terminal block. The status indicators are illuminated by LEDs or other light emitters disposed within a housing of the I/O device. Light from the LEDs are directed to the status indicators by light pipes disposed within the housing of the I/O device. LED activation circuitry disposed within the housing determines a manner in which to activate the LEDs to illuminate the status indicators based on inputs and outputs between the I/O device and a controlled process. In certain embodiments, the status indicators are disposed on a raised section of the I/O device, which may be part of a removable LED indication assembly including the LEDs, light pipes, and LED activation circuitry.

Abstract: The present disclosure relates to a polling method of communication system configured to reduce a polling time by receiving responses from a plurality of auxiliary devices using one time of response request signal by a main device during polling, the method including, requesting, by a main device, transmission of response request signals from a plurality of auxiliary devices connected to the main device (request step), determining whether each of the plurality of auxiliary devices is a response object after receiving the response request signal (response object determination step), determining a response order by each of the plurality of auxiliary devices that has determined itself as the response object (response order determination step), and responding, by itself, to the response request after lapse of waiting time in response to its response order (response step).

Abstract: A capability is provided for adaptive polling of a device based on a set of polling control regions configured to control polling of the device. The set of polling control regions is defined based on at least one of a set of control parameters and non-parametric control information. A transition within the set of polling control regions is determined based on a current polling control region and a target polling control region that is determined based on input information received while in the current polling control region. The input information may include at least one of values of one or more parameters in the set of parameters and non-parametric input information. The transition may include remaining in the current polling control region or transitioning to a new polling control region. The transition may be performed based on a rapid up controlled down (RUCD) transition scheme.

Abstract: A multi-chip memory device and a method of controlling the same are provided. The multi-chip memory device includes a first memory chip; and a second memory chip sharing an input/output signal line with the first memory chip, wherein each of the first memory chip and the second memory chip determines whether to execute a command unaccompanied by an address, by referring to a history of commands.

Abstract: A SAS expander configured to operate as a SAS expander hub receives IO requests from a plurality of connected SAS expanders. Each SAS expander determines if it is capable of servicing a received IO request and sending such IO requests to the SAS expander hub if necessary. The SAS expander hub relays the IO requests to SAS expanders connected to data storage devices capable of servicing such IO requests.

Abstract: An access method includes: obtaining, by a computer, a result of monitoring a busy rate and a number of access operations per unit time of a storage device, the storage device having a first storage area and a second storage area; calculating a characteristic of correlation between the busy rate and the number of access operations per unit time based on the result; calculating a second number of access operations per unit time based on the characteristic of the correlation such that a sum of a first busy rate corresponding to a first number of access operations per unit time and a second busy rate corresponding to a second number of access operations per unit time becomes equal to or lower than a given busy rate; and controlling a number of operations to access the second storage area per unit time based on the second number of access operations.

Abstract: In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.

Abstract: A first thread enters a polling loop to wait for a signal from a second thread before processing instructions dependent on the polling loop. When entering the polling loop, the first thread sets a reservation for a predetermined memory address. The first thread then executes a reservation-based instruction that can change the execution state of the first thread. Reservation circuitry of the processing device that was executing the first thread monitors the reservation. In the event that the reservation cleared, such as by the second thread modifying data at the predetermined memory address, the first thread is reinstated to its prior execution state. By using a hardware reservation mechanism to monitor for clearing of a set reservation, repeated memory accesses to the memory address by the first thread can be minimized or avoided while in the polling loop and other threads can be allowed to execute at the processing device with reduced interference from the waiting thread.

Abstract: In a disclosed example of a method, a requested value of a target register may be specified as a precondition to performing a requested read or write operation. The requested read or write operation may be generated by a requesting device, such as a processor, and sent over a bus to a peripheral device containing the target register. The target register may be polled internally to the peripheral device without generating additional bus traffic between the requesting device and the peripheral device. A ring topology may be used to internally poll the target register and to perform the requested read or write operation when the polled value of the target register equals the requested value.

Abstract: There is provided an apparatus including a plurality of modules. Each module includes a storage unit configured to store a waiting ID and a specific ID of the module, a communication unit configured to transmit and receive packets to and from a bus, and a processing unit configured to process data of a packet which includes a valid flag indicating that the packet is valid, wherein the communication unit takes in data held by a packet which has an ID that coincides with the waiting ID, and stores the processed data in a packet which includes the valid flag indicating invalid and an ID coincident with the specific ID, and transmits the packet.

Abstract: A method to adjust a multi-path device reservation by supplying a computing device and a storage controller interconnected with a communication link. The method further reserves a data storage device in communication with the storage controller, where that data storage device reservation is held by a first communication path group comprising a first plurality of communication paths configured in the communication link. If the method detects a failed communication path configured in the first communication path group, the method configures a second communication path group by removing the failed communication path from the first communication path group, wherein the second communication path group maintains the data storage device reservation.

Abstract: Systems and methods for scanning ports for work are provided. One system includes one or more processors, multiple ports, a first tracking mechanism, and a second tracking mechanism for tracking high priority work and low priority work, respectively. The processor(s) is/are configured to perform the below method. One method includes scanning the ports, finding high priority work on a port, and accepting or declining the high priority work. The method further includes changing a designation of the processor to TRUE in the first tracking mechanism if the processor accepts the high priority work such that the processor is allowed to perform the high priority work on the port. Also provided are computer storage mediums including computer code for performing the above method.

Abstract: In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.

Abstract: A method for communication between an initiator system and a block storage cluster may include receiving a first input/output (I/O) request from the initiator system. The method may also include sending a referral response from a first storage system included in a plurality of storage systems of the block storage cluster to the initiator system when data associated with the first I/O request is stored in more than one storage system of the plurality of storage systems of the block storage cluster. Additionally, the method may include directing a referral I/O to the first storage system and the second storage system for transferring data to or transferring data from the first storage system and the second storage system, and transferring data associated with the referral I/O to or transferring data associated with the referral I/O from the first storage system and the second storage system.

Abstract: A method of deciding to release communication resources used for a network access server session in a communication network is provided, wherein the method involves receiving an Accounting Stop Request for a PDP context associated to the network access server session, deciding whether a Session Stop Indicator is included in the Accounting Stop Request, in case no Session Stop Indicator is included deciding whether further PDP contexts are associated with the network access server session, in case no further PDP context is associated with the network access server session, starting an IDLE Timer to determine a point in time for releasing the communication resources.

Abstract: Methods, system and computer products for user-managed multi-path performance in balanced or unbalanced fabric configurations. Exemplary embodiments include a path priority selection method, including selecting a first I/O data path to be a highest priority path in a storage area network system, selecting a second I/O data path to be a low priority path, selecting an I/O threshold value, the I/O threshold value indicating that I/O data load is excessive, directing the load balance of I/O traffic to the first I/O data path, thereby placing the second I/O data path in a standby state, monitoring the first I/O data path, determining if the first I/O data path has reached the threshold value and performing a controlled failover of the first I/O data path to the second I/O data path when an I/O data load on the first data path has reached the threshold value.

Abstract: Architecture that allows programmatic association of devices to sessions and redirects input to the desired session. When the solution is active, input from the devices is not realized by the standard operating system input stack, thereby allowing even reserved key sequences such as Ctrl-Alt-Del to be intercepted and redirected to a desired session. Moreover, in addition to redirecting input to a specific session, the architecture facilitates the filtering of input from unwanted/unmapped devices, the interception and filtering or redirection of reserved key sequences such as Ctrl-Alt-Del, and the maintenance of input state for each session.

Abstract: The present invention provides a polling method in a radio digital communication system making it possible to shorten time required for polling without causing increase in an error rate and to efficiently manage and administrate communications. In a digital radio communication system for collecting information from a plurality of terminal stations by polling, a polling response signal to be transmitted from each terminal station to a base station has a frame format constructed of a one-frame in which a cyclic bit pattern is placed at a leading end of the frame format.

Abstract: There is described a method, a bus protocol, a peripheral module, a processing unit, a hub and also to a system consisting of said components, for event signaling between at least one peripheral module and a processing unit by means of a system bus. In this case the data to be transmitted data is encoded into a larger symbol space, from which a standard idle symbol is used in telegram pauses for synchronizing a connection between transmitter and receiver. A message present at the peripheral modules is enabled to be signaled to the processing unit independently of the telegram traffic initiated by the processing unit.

Abstract: A method and system suitable for grouping a plurality of multifunction devices (MFDs), the system including a storage station for storing information gathered from the plurality of MFDs by selectively polling the plurality of MFDs; wherein the information is selectively processed based on static performance data and dynamic performance data relating to the plurality of MFDs.

Abstract: A USB port transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one USB transmission from among multiple scheduled USB transmissions based on their types. A selector selects one of the arbiters to select the one USB transmission from among the multiple scheduled USB transmissions. A programmable storage element controls the selector to select the one arbiter. In one embodiment, at least a first arbiter prioritizes header/data packets higher than link commands, and at least a second arbiter prioritizes link commands higher than header/data packets. In one embodiment, at least one arbiter prioritizes flow control and power management link commands higher than header/data packets. In one embodiment, at least a first of the arbiters prioritizes USB LGO_Ux link commands higher than USB LAU/LXU link commands, and at least a second arbiter prioritizes USB LAU/LXU link commands higher than USB LGO_Ux link commands.

Abstract: Methods, systems, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA on an origin node in an origin injection FIFO, a data descriptor for an application message; inserting, by the origin DMA, a reflection descriptor in the origin injection FIFO, the reflection descriptor specifying a remote get operation for injecting a completion notification descriptor in a reflection injection FIFO on a reflection node; transferring, by the origin DMA to a target node, the message in dependence upon the data descriptor; in response to completing the message transfer, transferring, by the origin DMA to the reflection node, the completion notification descriptor in dependence upon the reflection descriptor; receiving, by the origin DMA from the reflection node, a completion packet; and notifying, by the origin DMA in response to receiving the completion packet, the origin node's processing core that the message transfer is complete.

Abstract: A computer system includes a receiver configured to pair with a set of peripheral devices and have active connections with a first subset of the peripheral devices and inactive connections with a second subset of the peripheral devices. The first and the second subsets of peripheral devices are subsets of the set of peripheral devices. If a select one of the peripheral devices in the inactive set of peripheral devices is operated, the receiver is configured to activate a connection with the select one of the peripheral devices in a latency period that is below human perception levels of the latency period.

Abstract: A data processing apparatus and method are provided for managing polling loops. The data processing apparatus comprises a main processing unit and a subsidiary processing unit operable to perform a task on behalf of the main processing unit. The subsidiary processing unit is operable to set a completion field when the task has been completed and the main processing unit is operable to poll the completion field in order to determine whether the task has been completed. If on polling the completion field a threshold number of times the main processing unit determines that the task has not been completed, the main processing unit is operable to enter a power saving mode. The subsidiary processing unit is operable, when the task has been completed, to cause a notification to be issued on a path interconnecting the main processing unit and the subsidiary processing unit. The main processing unit is arranged, upon receipt of the notification to exit the power saving mode.

Abstract: A system for activating an appliance responsive to one of many transmission schemes includes a transmitter, memory holding data describing the transmission schemes, and a controller in communication with the transmitter and the memory. The controller is operable to store a fixed code. If a fixed code is stored, then the controller transmits a sequence of fixed code activation schemes, based on the fixed code and data held in the memory, until input indicating activation of the appliance is received. If no fixed code is stored, then the controller transmits a sequence of rolling code activation schemes, based on data held in the memory, until input indicating activation of the appliance is received. The controller stores in the memory an indication as to which activation scheme activated the appliance based on the received input. The controller generates an activation signal based on the stored indication and a received activation input.

Abstract: An effective method for securing the release of the transmission, rendering, and outputting of an imaging/print job at an imaging device, for imaging/print jobs that originate in traditional print/spooling subsystems include the following steps. A print job header is associated with an imaging/print job to form a headed imaging/print job. A secured release input (that may be input at a secured release input apparatus of the client host device) is associated with the print job header by including a secured release indicative command/code in the print job header. The headed imaging/print job is divided into data packets. Initial data packet(s) are transmitted to the imaging device. It is determined whether the secured release indicative command/code is present in the initial data packet(s). Acceptance of subsequent data packets of the headed imaging/print job are prevented if the secured release indicative command/code is present in the initial data packet(s).

Abstract: An apparatus, program product and method of processing access requests for a direct access storage device utilize a “fair elevator” algorithm to schedule access requests from a plurality of requesters desiring access to a direct access storage device (DASD). In particular, a fair elevator algorithm arbitrates requests by taking into account both the requesters with which various requests are associated, as well as the relative positions of the data to be accessed on the DASD. By sorting access requests based upon both requester identity and DASD position, both multitasking performance and DASD throughput are improved in a balanced manner, thus improving overall system performance.

Abstract: A processor prioritizes data traffic by limiting a number of data buffers that can be retrieved. By limiting the number of data buffers that can be retrieved, some packets are dropped on a receive side to save processing cycles that would be spent processing packets that may be dropped on the transmit side after processing.

Abstract: A system and method harvest data from at least one device, by canvassing the devices and tracking which canvassed devices yielded harvested data and then repeating such canvassing and tracking until either data has been obtained from all of the devices, or a certain time has passed since the beginning of the canvassing period. In a further embodiment, when data has been obtained from all the devices or the time has passed, whichever comes first, the harvested data is sent to a central processing center.

Abstract: A circuit. The circuit includes a first selection module having first data input, second data input, first validation input, second validation input, selected data output, marker output, and presence output. A first validation signal received at the first validation input identifies whether or not a first data signal received at the first data input is valid; a second validation signal received at the second validation input identifies whether or not a second data signal received at the second data input is valid; a presence signal outputted at the presence output identifies whether or not at least one data signal is valid; and the first data input has an assigned selection priority higher than that assigned to the second data input. If at least one data signal is identified as valid, the valid data signal having the higher assigned priority is transferred to the selected data output.

Abstract: A data packet queue handling method and system is proposed, which is designed for use with a computer system having a data packet generating unit, a data packet transfer interface, a data packet processing unit, and a memory unit, wherein the data packet generating unit is capable of generating a sequence of data packets which are transferred via the data packet transfer interface to the data packet processing unit. The proposed method and system is capable of providing a novel data packet queue handling capability that can help prevent the occurrence of a deadlock condition in the computer system due to a memory-sufficient condition in the memory unit, so that the overall throughput of the computer system can be ensured.

Abstract: A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one processor changes the system state. Architected designs where latencies between nodes are made known and predictable greatly simplify the task of coordinating quiesce responses within the system. When latencies are not fixed and topologies such as open or closed bus architectures are be used a more dynamic approach is required to ensure system serialization. Adaptive quiesce logic on each node's SCE can dynamically identify the role of the node within the system and automatically configure itself to guarantee that no enabled processor within the entire system receives a quiesce indication before all processors have reached the stopped state. This is also true for systems where nodes are being concurrently added or removed during system operation. Bus states process quiesce requests.

Abstract: Disclosed is serial communication control system including: a first microcomputer; and a second microcomputer connected to the first microcomputer through a serial line, wherein the second microcomputer includes an R/B signal sending section to send one of a READY signal and a BUSY signal, the first microcomputer includes an R/B signal receiving section to receive the signal, and a first sending section to send first serial data to the second microcomputer when the R/B signal receiving section receives the READY signal, the second microcomputer includes a first receiving section to receive the first serial data, and a second sending section to send second serial data after the receiving operation of the first serial data by the first receiving section is completed and the R/B signal sending section thereafter sends the BUSY signal, and the first microcomputer includes a second receiving section to receive the second serial data.

Abstract: A processor is used to evaluate information regarding the number, size, and priority level of data transfer requests sent to a plurality of communication ports. Additional information regarding the number, size, and priority level of data requests received by the communication ports from this and other processors is evaluated as well. This information is applied to a control algorithm that, in turn, determines which of the communication ports will receive subsequent data transfer requests. The behavior of the control algorithm varies based on the current utilization rate of communication port bandwidths, the size of data transfer requests, and the priority level of the these transfer requests.

Abstract: A polling device of the present invention performs communication control such that frame synchronous transfer modes and frame asynchronous transfer modes are used so as to perform a communication operation, and includes: a polling counter section for reading all communication channels for each address number; a state circuit for changing the order of priority in transfer each time the polling counter section counts one round of values after initializing the state circuit for each frame period; a latch section for latching a value of the polling counter section; and a matching detection section for comparing the value latched by the latch section with a value of the polling counter section, in which a polling operation is started from the value latched by the latch section at the time of initializing the state circuit for each frame period.

Abstract: In response to requests for I/O processing sent from a computer, I/O which should be processed at a priority is enabled to be processed without being affected by other processing, by classifying I/O into those to be processed at a priority and those not to be processed at a priority. The storage control apparatus comprises an I/O processing controller with a memory that is common for the whole controller. The storage control apparatus manages information for dividing and controlling a plurality of I/O processes as priority and non-priority in that memory and operates while suppressing non-priority I/O processing on the basis of information in the memory.

Abstract: I/O measurement data associated with the performance of an I/O operation process is gathered during the I/O process. The I/O measurement data is saved in an IRB memory location specified by a test subchannel instruction. An I/O interrupt signals the completion of the I/O operation process.

Abstract: A method and system for providing priority to a station in a congested half duplex Ethernet network. Specifically, one embodiment of the present invention includes a method for providing priority to a peripheral component (e.g., half duplex Network Interface Card) in a congested network. The method includes the step of detecting a collision of a data packet during transmission of the data packet by a peripheral component coupled to a network. Furthermore, the method includes the step of determining a restricted back off time. It should be appreciated that the restricted back off time is substantially equal to or less than a restricted time value. Additionally, the method includes the step of causing the peripheral component to wait the restricted back off time before trying to retransmit the data packet over the network.

Abstract: An apparatus comprising a shared memory and a multiprocessor logic circuit. The shared memory may be configured to store data. The multiprocessor logic circuit may comprise a plurality of processors and a message circuit. The message circuit may be configured to pass messages between the processors.

Abstract: Provided is a method, system, and program for managing Input/Output (I/O) requests generated by an application program. The I/O requests are transmitted to an output device. A determination is made of a priority associated with the I/O request, wherein the priority is capable of being at least one of a first priority and a second priority. The I/O request is transmitted if the determined priority is the first priority. Transmittal of the I/O request is deferred if the determined priority is the second priority.

Abstract: A data transmission method in which a transmission request is forwarded from a host apparatus to a terminal apparatus. When receiving the transmission request, the terminal apparatus forwards as communication request to the host apparatus. In this communication request, a timer value of a system timer included in the terminal apparatus is incorporated. Having received the communication request including the timer value, the host apparatus establishes an ID for the terminal apparatus according to the timer value. Then, the host apparatus conducts polling for collecting data from the terminal apparatus using the established ID.

Abstract: A method and system for scheduling multiple frames and packets that are queued for transmission over a link, and queued from a link for storing into main memory. It recognizes priorities, provides fairness, and guarantees forward progress of all users. This method and system provides a mechanism that achieves the objectives with a very small state machine. It takes advantage of the nature of the traffic to calculate priorities in parallel to frame transmission.

Abstract: A Bus Driver implements an arbitration mechanism to allow both the system management interrupt (SMI) and the Bus Driver to cooperatively use a Bus host controller hardware. This mechanism employs a hardware-based semaphore (status bit) to allow either the SMI or the driver to claim ownership of the Bus host controller for an arbitrary period of time. While either the SMI or the driver may own the status bit, the other party must poll the bit until ownership is achieved. For the SMI, this involves scheduling a periodic SMI interrupt. The driver performs self arbitration of claiming the status bit to provide the periodic SMI interrupt the opportunity to claim the bit. The mechanism allows the SMI access to the Bus host controller in a “timely” manner, while minimizing impact to driver access to the Bus host controller, which could impact driver Bus transaction throughput.

Abstract: An invention is provided for hiding an input/output device from an operating system. A window of time is provided wherein a specific input/output processor (IOP) has exclusive access to a bus. An IOC memory map register, which is utilized by an input/output chip (IOC), is configured during the window of time using the IOP. In addition, a hide indicator is configured to indicate the IOC should be hidden. In this manner, data is communicated between the IOP and the IOC using the IOC memory map register. In one aspect, the hide indicator can be configured, before the window of time, to indicate the IOC should be hidden. In addition, the hide indicator can be configured during the window of time to indicate the IOC should be exposed.

Abstract: An improved hibernation method and system, including the use of a modified DMA (Direct Memory Access) mode of transferring data to and from the disk. The use of DMA increases data transfer speed, while freeing the system processor to perform other tasks, including compressing/decompressing the data transferred to and from the disk. An improved decoder is also provided that reduces the number of bounds checks needed on average for typical compressed data by first guaranteeing that there is sufficient room to decode literals and small substrings, whereby bounds checking is not needed. A combination hibernation mode and a suspend mode is also provided that essentially maintains power to the RAM while transparently backing the RAM with the hibernation file, such that if power to the RAM is interrupted, the RAM contents are automatically restored from the hibernation file when power is restored.

Abstract: Described is an improved decoder that reduces the number of bounds checks needed for typical compressed data by first guaranteeing that there is sufficient room to decode small symbol substrings and literal symbols, whereby bounds checking need not be performed on each symbol. Because literal symbols and small substrings of symbols form the majority of compressed data, the reduced checking significantly speeds up decoding on average. In one implementation, a fast LZ77 decoder that operates without bounds checking is used in a first phase until the end of the output buffer is neared at which time a second phase standard decoder, which performs bounds checks on each to ensure that the buffer does not overflow, is used. Normally the standard decoder decompresses only a small amount of data relative to the amount of data decompressed with the fast decoder, greatly improving decompression speed while not compromising safety.

Abstract: A functional system comprises a set of functions (F) requiring access to a collective resource (RSRC). Such a system can be, for example, a data processing system comprising a plurality of processors requiring access to a collective memory. For reasons of cost it is desirable to guarantee a certain minimum access for one or more functions while a certain degree of flexibility as regards the access is maintained. For this purpose, the system comprises an interface (INT) adapted to implement an access scheme (AS) characterized by a plurality of states (S) passed through in a predetermined manner. A state (S) forms a possibility of access of a given length and defines an order of priority in accordance with which a function (F) can access the collective resource (RSRC).

Abstract: A mechanism for maintaining the first-in first-out order of commands in a multiple-input and multiple-output buffer structure includes a command number generator for generating and assigning a command number to each command entering the buffer structure, and a command number comparator for comparing the command number of the outgoing command at each buffer in the buffer structure to determine which command should exit. Both command number generator and command comparator have a cyclic counter that has a period greater than or equal to the total number of allowable buffer entries in the buffer structure. For maintaining order of posted and non-posted command queues, a pending posted write counter is used in the posted command queue to record the number of pending posted write command and each entry in the non-posted command queue is associated with a dependency counter.