Abstract: In one embodiment a storage controller comprises a processor, a computer readable storage medium coupled to the processor, and logic instructions in the memory module which, when executed by the processor, configure the processor to receive, in a quality of service module, a first command request from a host initiator port, associate a time-out threshold with the first command request, determine, in the quality of service module, whether an available priority queue can release the first command request for execution by a scheduling module within the time-out threshold; and in response to a determination that an available priority queue can release the first command request for execution within the time-out threshold, assign the first command request to the available priority queue.

Abstract: A memory device includes an interface controller for communication with a semiconductor device over a communication link. A clock signal is transmitted from the semiconductor device over the link to the memory device. A frequency of the clock signal may be any within a given range of frequencies. A frequency value signal conveying the value of the frequency of the clock signal is also transmitted. The interface controller includes circuitry for deriving from the clock signal and from the frequency value signal at least one timing signal for any operation in the memory device.

Abstract: A method for facilitating input/output (I/O) communication for a processing operation is provided. An interrogate command is obtained by an I/O communications adapter. The interrogate command queries for status information of the processing operation to be provided in an interrogate response. A fixed number of resources and a time allocated to the interrogate command is throttled by pre-allocating the fixed number of resources needed for the interrogate command, and maintaining a timestamp for a interrogate message. The interrogate message is forwarded from the I/O communications adapter to a control unit. If the interrogate response is not received by the I/O communications adapter within a limited timeout period as measured by the timestamp, or if the interrogate message is received while the fixed number of pre-allocated resources are in use, the I/O communications adapter returns a busy response indicating the control unit is busy to prevent overrunning the control unit.

Abstract: Methods and apparatus are disclosed for managing device reservation. In one embodiment, upon receiving a device command from a first host, a device targeted by the device command is reserved for the first host and a reservation time period for expiration of the reservation status is set.

Abstract: One embodiment of the present invention performs peripheral operations in a multi-thread processor. A peripheral bus is coupled to a peripheral unit to transfer peripheral information including a command message specifying a peripheral operation. A processing slice is coupled to the peripheral bus to execute a plurality of threads. The plurality of threads includes a first thread sending the command message to the peripheral unit.

Abstract: A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted. The time point at which the particular request is accepted is always within the validity duration interval in which the particular access request is made.

Abstract: A system and method harvest data from at least one device, by canvassing the devices and tracking which canvassed devices yielded harvested data and then repeating such canvassing and tracking until either data has been obtained from all of the devices, or a certain time has passed since the beginning of the canvassing period. In a further embodiment, when data has been obtained from all the devices or the time has passed, whichever comes first, the harvested data is sent to a central processing center.

Abstract: When a device in a WUSB system is ready for transmission data upon reception of a data transmission request (WdtCTA) from a host device, the device outputs the transmission data at a time specified by the WdtCTA. Meanwhile, when the transmission data is not ready, the device estimates a preparation completion time for the transmission data, and when the estimated preparation completion time is before an earliest time at which the host device can retransmit the WdtCTA, the device sends an error response instead of a NAK response, to thereby request the host device to retransmit the WdtCTA. As a result, a data transmission efficiency between the host device and the device is improved.

Abstract: A method and device of synchronizing interrupts of a processor with, for example, signals from a synchronization unit such as, for example, a slot timer. In advance of the start of a slot as may, for example, be indicated by a signal from, for example, a slot timer, a state machine may schedule the function that will be permitted to interrupt a processor. Only the scheduled function may interrupt the processor during the slot. Time dependent functions that may be waiting to be processed may have to wait until the start of a next slot. Background functions that are too large to be processed within the time available in a slot may, for example, be divided into segments, each of such segments capable of being processed within the time available in a slot.

Abstract: A mechanism for reprioritizing high-latency input/output operations in a file system is provided. The mechanism expands a file access protocol, such as the direct access file system protocol, by including a hurry up command that adjusts the latency of a given input/output operation. The hurry up command can be employed in the Direct Access File System.

Abstract: There is provided a distributed peer-to-peer communication system for interconnect busses of a computer system. More specifically, there is provided a method comprising transmitting a request to establish an isochronous channel between a first device and a second device, establishing the isochronous channel between the first device and the second device, and generating an isochronous transaction across the isochronous channel between the first device and the second device, wherein the isochronous transaction is a message type transaction.

Abstract: An electronic control unit has two microcomputers. Each microcomputer has a data buffer storing data first to be transmitted in every 8 ms, a second data buffer storing data to be transmitted in every 16 ms, and a third data buffer storing data to be transmitted in every 16 ms and being different from the first and second data buffers. The microcomputer transfers at the transmission timing of every 8 ms data in the first data buffer to the transmitting buffer, while it transfers alternately the data in the second data buffer and the data in the third data buffer to the transmitting buffer. The microcomputer also transfers an ID that indicates content of the present transmitting data to the transmitting buffer.

Abstract: In a wireless USB data transfers over UWB, software configures hardware thresholds to control data transfer in a manner that uses bandwidth for good connections over bad connections, given the high error rate experienced with wireless USB. Periodic transfers are first attempted before asynchronous transfers, as long as the periodic transfers are successful. When failures are occurring, the hardware includes a mechanism having a software-configurable threshold specifying the number of errors a given endpoint can tolerate before it is paused in the schedule. By pausing transfer attempts that are likely to again fail, endpoints with successful transfers are favored over those experiencing errors. When the number of active transfers pending exceeds a software-configurable notification threshold for isochronous endpoints, the hardware notifies the software of this state, corresponding to a low-buffer condition at the receiver.

Abstract: The present invention is directed to a method and apparatus for scheduling a resource to meet quality of service guarantees. In one embodiment of three levels of priority, if a channel of a first priority level is within its bandwidth allocation, then a request is issued from that channel. If there are no requests in channels at the first priority level that are within the allocation, requests from channels at the second priority level that are within their bandwidth allocation are chosen. If there are no requests of this type, requests from channels at the third priority level or requests from channels at the first and second levels that are outside of their bandwidth allocation are issued. The system may be implemented using rate-based scheduling.

Abstract: A processing system and method of communicating within the processing system is disclosed. The processing system may include a bus having a transmit channel, a receiving component, and a sending component configured to broadcast a payload to the receiving component over the transmit channel, interrupt the broadcast of the payload to signal a new bus operation to the receiving component over the transmit channel, and resume the broadcast of the payload over the transmit channel. The processing system may include an algorithm that prevents small payloads from being interrupted to initiate a new bus operation. The algorithm may also be used to limit the number of times a single write operation may be interrupted to initiate a new bus operation.

Abstract: In response to requests for I/O processing sent from a computer, I/O which should be processed at a priority is enabled to be processed without being affected by other processing, by classifying I/O into those to be processed at a priority and those not to be processed at a priority. The storage control apparatus comprises an I/O processing controller with a memory that is common for the whole controller. The storage control apparatus manages information for dividing and controlling a plurality of I/O processes as priority and non-priority in that memory and operates while suppressing non-priority I/O processing on the basis of information in the memory.

Abstract: A scheduling method and apparatus for use by a processor that controls storage devices of a data storage system is presented. The method allocates processing time between I/O operations and background operations for predetermined time slots based on an indicator of processor workload.

Abstract: An OCN with independent logical and physical layers for enabling communication among integrated processing elements, including ports, bus gaskets and a physical layer interface. Each bus gasket includes a processor element interface and a port interface. Each processor element interface of at least two bus gaskets operates according to a first logical layer protocol. Each port interface operates according to a consistent port interface protocol by sending transaction requests and receiving acknowledgements and by sending and receiving packet datums via the corresponding port. The physical layer interface transfers packets between the ports and includes an arbiter and an interconnect coupled to each port. Additional bus gaskets may be added that operate according to a second logical layer protocol which may or may not be compatible with the first. Any bus gasket may be added that is configured to communicate using multiple logical layer protocols.

Abstract: A transceiver device comprises a transmitter to transmit signals over a plurality of conductors to a memory device. An interface receives control information from a serial communication path coupled to a controller device. The control information is provided to the memory device as the signals using the transmitter. A register stores a control parameter that specifies a drive strength adjustment to the signals to transmit over the plurality of conductors to the memory device using the transmitter.

Abstract: A method and apparatus are provided in a computing environment for scheduling access to a resource. The method grants access to the resource by a non-real-time request when the non-real-time request can be completed before the latest possible start time at which a first real-time request must start service to timely complete all actual and anticipated real-time requests, otherwise granting the first real real-time request access to the resource.

Abstract: An error detection mechanism is provided for detecting sequential and distributed errors in a device I/O stream. The sensitivity of the errors is user definable. The result of the error detection is fed back into the path management software, which may use the error information to decide whether a device path should be disabled. The error detection mechanism sets a time span for a time window and counts the number of errors that occur during the time window. Each time a time window ends with at least one error, the sequential error count and the distributed error count are incremented. However, if an I/O returns without an error, the sequential error count is cleared. If the sequential error count reaches a predetermined limit, the path is disabled. After a predetermined number of time windows, if the distributed error count reaches a predetermined limit, the path is disabled.

Abstract: A flexible input/output (I/O) interface allows a processing core to communicate high-speed data with a several different types of interfaces including a Direct Memory Access (DMA) interface and a streaming interface. The I/O interface includes a streaming interface for transferring streamed data from the streaming data bus to the core-processing engine, a DMA interface for transferring DMA data from the DMA data bus to the core-processing engine, and an arbiter for coordinating data transfer with the core-processing engine between the streaming interface and DMA interface. The arbiter may operate in a split-bus-mode wherein the arbiter performs the address phase for more than one channel prior to entering into the data phase. The flexible I/O interface may include a common address bus and data bus between the processing engine and the interfaces. Alternatively, a switching fabric may couple separate address and data buss of the interfaces with the processing engine.

Abstract: A transceiver comprises a first interface to receive a first signal, through a first channel, from a memory device. A transmitter transmits a second signal that represents the first signal, through a second channel, to a master device. A plurality of registers stores a plurality of values provided by the master device. The plurality of values includes a first value that specifies a transmit timing adjustment to the second signal to transmit to the master device by the transmitter.

Abstract: Various methods and apparatuses to deactivating the mechanism to resolve instruction starvation if an agent which issued a first transaction does not reissue the first transaction within a predefined time period.

Abstract: In digital signal processors serial data is passed in out and of the chip in a time division multiplexed (TDM) fashion. The TDM stream consists of many independent channels of serial data. The complexity of generating interleaved TDM serial data from multiple sources particularly in the case of multi-processor systems. This process is normally driven by a program resident on each processor. The proper sequencing of the TDM serial stream must be tested prior to making the multi-processor device ready for its application. This invention describes the use of minimal added hardware and a single output pin allowing the test and debug of program errors or device malfunctions in output serial data.

Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Abstract: An invention is provided for hiding an input/output device from an operating system. A window of time is provided wherein a specific input/output processor (IOP) has exclusive access to a bus. An IOC memory map register, which is utilized by an input/output chip (IOC), is configured during the window of time using the IOP. In addition, a hide indicator is configured to indicate the IOC should be hidden. In this manner, data is communicated between the IOP and the IOC using the IOC memory map register. In one aspect, the hide indicator can be configured, before the window of time, to indicate the IOC should be hidden. In addition, the hide indicator can be configured during the window of time to indicate the IOC should be exposed.

Abstract: A queue-based spin lock with timeout allows a thread to obtain contention-free mutual exclusion in fair, FIFO order, or to abandon its attempt and time out. A thread may handshake with other threads to reclaim its queue node immediately (in the absence of preemption), or mark its queue node to allow reclamation by a successor thread.

Abstract: A disk drive is disclosed which pre-computes first seek parameters to seek to a continuation track storing read-ahead data, and second seek parameters to seek to a target track of a next command. An abort window is also computed for aborting a read-ahead operation early in order to seek to the target track of the next command. If the head enters the abort window, the disk drive is programmed with the second seek parameters to seek to the target track of the next command. If the read-ahead operation requires a seek to the continuation track prior to the head entering the abort window, the disk drive is programmed with the first seek parameters to seek to the continuation track.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in response to one or more control signals. The second circuit may be configured to generate the one or more control signals, wherein the memory is time shared among the second port and the plurality of first ports.

Abstract: An arbiter (7) is provided for a QMS having multiple queue users (5A to 5D), each having real time requirements for mastership of a bus (31). The arbiter (7) is arranged so that the amount of time that each queue user (5A to 5D) can gain bus access is a percentage of the total bus time.

Abstract: A system comprises a plurality of memory controllers connected to a memory bus. Each memory controller is able to generate memory requests on the memory bus according to a predetermined priority scheme. One priority scheme is a time slot priority scheme, and another priority scheme is a request-select priority scheme. The plurality of memory controllers are able to monitor memory requests generated by another memory controller in performing memory-related actions, such as memory requests (read or write), read-modify-write transaction, and cache coherency actions. In one arrangement, the memory bus is a Rambus channel.

Abstract: Provided is a method, system, and program for managing Input/Output (I/O) requests generated by an application program. The I/O requests are transmitted to an output device. A determination is made of a priority associated with the I/O request, wherein the priority is capable of being at least one of a first priority and a second priority. The I/O request is transmitted if the determined priority is the first priority. Transmittal of the I/O request is deferred if the determined priority is the second priority.

Abstract: A packet communication apparatus processes consecutively transmitted fixed-length packets. The apparatus includes a storage circuit, a first processing circuit which accesses the storage circuit for processing data obtained from each of the packets, and a second processing circuit which accesses the storage circuit for processing data stored in the storage circuit. The apparatus further includes an allocation circuit for executing access time allocation with respect to a packet processing time allowed for processing each of the packets. Specifically, the allocation circuit allocates a first time of the packet processing time to the first processing circuit for accessing the storage circuit and a second time of the packet processing time to the second processing circuit for accessing the storage circuit. The first time and the second time are prevented from overlapping with each other.

Abstract: Two transfer modes of a band-guaranteed cycle and an event-driven type asynchronous cycle are defined for a multimedia bus. In the band-guaranteed cycle, stream data is transferred between nodes, to which the same channel number is assigned, in peer-to-peer mode using a reserved band for each cycle time. If the same channel number is assigned to a plurality of receiver nodes, a multi-cast transfer can be achieved by the band-guaranteed cycle. The multi-cast transfer using the band-guaranteed cycle can be stopped even in response to an instruction from any receiver node, and a buffer of each receiver node can be prevented from overflowing.

Abstract: In a method and system for transferring data between a plurality of bus devices, a bus interface unit includes a first bus device interface (FBDI), a second bus device interface (SBDI), and an arbitration circuit. Each of the FBDI and SBDI includes a corresponding incoming and outgoing request bus for receiving and transmitting request packets from a corresponding one of the plurality of bus devices. Similarly, each of the EBDI and SBDI also includes a corresponding incoming and outgoing data bus for receiving and transmitting data packets from the corresponding one of the plurality of bus devices. The arbitration circuit is capable of determining priority level associated with corresponding request packets received from the FBDI and the SBDI respectively.

Abstract: The present invention is directed to a method and apparatus for scheduling a resource to meet quality of service guarantees. In one embodiment of three levels of priority, if a channel of a first priority level is within its bandwidth allocation, then a request is issued from that channel. If there are no requests in channels at the first priority level that are within the allocation, requests from channels at the second priority level that are within their bandwidth allocation are chosen. If there are no requests of this type, requests from channels at the third priority level or requests from channels at the first and second levels that are outside of their bandwidth allocation are issued. The system may be implemented using rate-based scheduling.

Abstract: A wearable computer system includes a processing unit (102) and a number of peripherals. The processing unit and peripherals are coupled in a daisy-chain fashion utilizing a serial bus (120). The processing unit has a single connector for implementing the serial bus, and peripherals each have two connectors for propagating the serial bus. The wearable computer system has only one unused connector at any one time, thereby reducing excess bulk and weight due to excessive unused connectors. When a peripheral interrupts the processing unit, the processing unit relinquishes the serial bus to the interrupting peripheral. Alternatively, peripherals are assigned time slots within which the peripherals can utilize the serial bus.

Abstract: A system is configured to prioritize streaming disk I/O over non-streaming disk I/O by providing high priority queuing to streaming disk I/O and/or to throttle non-streaming disk I/O when the total disk I/O (streaming+non-streaming) exceeds a threshold amount for a given time quantum. When disk throttling is utilized, streaming disk I/O is processed in a first time quantum. Non-streaming disk I/O is processed, as much as possible, in the remainder of the first time quantum. Other non-streaming disk I/O remaining to be processed is deferred to a subsequent time quantum.

Abstract: A data transfer unit is provided which reliably receives the expedited command when the expedited command has arrived, and changes over the reception to receiving a general purpose command when no expedited command is arriving. The data transfer unit contains a data module having at least a command module, and first and second interfaces and first and second host control units. An expedited command output at an indefinite period from the first host control unit is fed to the data module through the first interface. The first interface is turned off and the second interface is turned on at all times when a general purpose command output at a predetermined period from the second host control unit is fed to the command module through the second interface. The first interface is turned on and the second interface is turned off by interface change-over signals of an active level fed to the data module just before the first host control unit produces the expedited command.

Abstract: A semiconductor memory enabling a read modify write operation of data, comprising: a memory cell array including a plurality of memory cells arranged in a matrix and able to be written with and read out data; a read address decoding means for independently decoding an address of a read memory cell in response to a read address; a write address decoding means for independently decoding an address of a write memory cell in response to a write address; a data reading means for reading data of a memory cell addressed by the read address decoding means; a data writing means for writing data to a memory cell addressed by the write address decoding means; and an address delay means by which a write address decoded by the write address decoding means is delayed by a predetermined time from a read address decoded by the read address decoding means, wherein the predetermined time is set as a predetermined plurality of times of basic synchronization pulse periods so that the data read modify write operation is accomplis

Abstract: A method for dispatching input/output access requests to a direct access storage device (DASD) is disclosed. Each of a group of I/O access requests to DASD is assigned into one of at least two I/O access request categories, namely, high priority I/O access requests and low priority I/O access requests. Each of a group of I/O slots within DASD is assigned into one of at least two I/O slot categories, namely, high priority I/O slots and low priority I/O slots. An I/O access request from a first one of the two I/O access request categories is sent to any one of the I/O slots. An I/O access request from a second one of the two I/O access request categories is sent to only a slot belonging to a subset of the two I/O slot categories.

Abstract: A computer system is presented which implements a system and method for tracking the progress of posted write transactions. In one embodiment, the computer system includes a processing subsystem and an input/output (I/O) subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor preferably executing software instructions. The I/O subsystem includes one or more I/O nodes. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). The multiple processing nodes may include a first processing node and a second processing node, wherein the first processing node includes a host bridge, and wherein a memory is coupled to the second processing node. An I/O node may generate a non-coherent write transaction to store data within the second processing node's memory, wherein the non-coherent write transaction is a posted write transaction.

Abstract: An input/output scheduling unit forms input/output groups obtained by grouping inputs/outputs to/from a disk apparatus. The input/output scheduling unit defines a ratio of the time during which each input/output group uses the disk apparatus and defines quanta &tgr;1 to &tgr;3 during which each input/output group can continuously use the disk apparatus on the basis of the defined time ratios. When input/output requests are received from a plurality of input/output groups to the disk apparatus, the input/output scheduling unit performs the time-sharing for sequentially switching the allocating times &tgr;1 to &tgr;3 between the input/output groups which competed and using the disk apparatus. Further, an allocating time of the remaining quanta is distributed to the quanta on the shortage side by an allocating time control unit in accordance with a degree of jam of each input/output group.

Abstract: In a storage environment or storage area network having multiple host devices and at least one storage array, the host devices access logical data volumes stored on the storage array through array controllers disposed in the storage array. Multiple host devices can request access to shared ones of the logical data volumes through multiple paths to multiple array controllers, but each logical data volume is controlled or owned by only one array controller at a time. Thus, ownership of shared logical data volumes is transferred between the array controllers as necessary on behalf of the requesting host devices. To prevent ownership transfers from occurring too often, however, ownership of the logical data volumes is made exclusive, or “sticky,” for a period of time after each transfer. During the exclusive ownership period of time, the ownership cannot be transferred.

Abstract: Mechanical data transfer and signal processing systems are described, as internal parts of a complete stand-alone computer. These components for a Mechanical Computer operate under a unifying BUS methodology using a single moving path-differentiated particle for each signal. A binary wheel flip-flop component family and an advanced multi-state component family allows both conventional and highly unconventional uses, including natural decimal BUS operations. At present, all necessary supporting components are anticipated, if not detailed. Some system details are incomplete, such as for exact component interconnection lists, sequencer lists, and host system development software, although use of such internal sequencer lists is taught. A modular or plug-in compatible packaging method is also detailed, which frees the user or experimenter from having to design individual connections.

Abstract: A method for transferring variable isochronous data and an apparatus therefor are provided. The method for transferring variable isochronous data includes the steps of (a) determining isochronous transfer to be terminated when the bus is in an idle state for a time interval which is larger than an isochronous gap period, (b) detecting a residual gap having a time interval which is larger than the time interval of an isochronous gap and smaller than the time interval of a subaction gap, (c) checking whether bandwidth for the transfer of isochronous data remains when the residual gap is detected in the step (b), and (d) transferring the isochronous data when it is determined that the bandwidth for the transfer remains in the step (c).

Abstract: The present invention provides fibre channel networks the ability to use extended link service commands, previously confined to networks including a fabric controller, in a direct attach, point-to-point configuration.

Abstract: A microprocessor 1 is described which includes a multi-channel serial port (MCSP) 120. MCSP 120 includes clock generation and frame sync generation circuitry 300, multi-channel selection circuitry 310, and companding circuitry 320. The clock generation and frame sync generation circuitry is configurable by means of a Serial Port Control Register SPCR, and Receive Control Register RCR, a Transmit Control Register XCR, a Sample Rate Generator Register SRGR, and Pin Control Register PCR. The multi-channel selection circuitry is configurable by means of a Multi-Channel Register MCR, a Receive Channel Enable Register RCER and a Transmit Channel Enable Register XCER. Companding circuitry 320 performs optional expansion or compression of received or transmitted data using &mgr;-LAW or A-LAW, as selected by the Receive Control Register or the Transmit Control Register.

Abstract: A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data items to be transferred while the first device is occupying the bus; determining if the first predetermined number of data items have been transferred; determining if the first device should release the bus based on whether or not there is a request from a second device after it is determined that the first predetermined number of data items have been transferred; and releasing the bus by the first deice when it is determined that the first device should release the bus.