Abstract: A method for auto-addressing a device in communication with a controller is disclosed. The method includes communicating a pulse from a first contact of a controller, receiving the pulse at a second contact of a device in communication with the controller, communicating a number of pulses from a first contact of the device, and receiving the number of pulses at a second contact of the controller, wherein the number of pulses indicates a number of devices in communication with the controller.

Abstract: When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the transfer bus width and a transfer address. Thus, it becomes possible to perform burst transfer in the access destination. Accordingly, in the case where burst transfer to an access destination in a different endian format is performed with a smaller data width than a transfer bus width, an inconvenience where burst transfer can not be performed because an address is converted and data access is no longer an ascending order access can be prevented.

Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.

Abstract: An infrastructure element can receive a first DMA request including a first address and the data, generate a meta request that comprises a resource key value and a doorbell address, and transmit the meta request via the infrastructure using the doorbell address. A remote DMA adapter can receive the meta request at the doorbell address and generate a remote direct memory access request message using the resource key, the first address and the data from the received meta request.

Abstract: In various embodiments, a plurality of non-volatile memory devices, such as NAND flash memory device, may be connected to a host controller device in a fanned out configuration that allows each of the plurality of memory devices to perform read and/or write operations simultaneously. Each non-volatile memory device may include high speed input circuitry and high speed output circuitry so that transfers to and from memory are not limited by the speed of the flash memory read/write interface.

Abstract: PCI Express transactions can be transmitted via a shared PCI Express infrastructure. At an infrastructure ingress point an additional header comprising at least a source identifier and a target identifier is generated for a transaction packet that comprises a header portion, a data portion and an end-to-end CRC portion. The transaction packet is then transmitted with the additional header from the ingress point to an egress point. At the egress point the additional header is removed. The additional header can further include a resource key. It can further include protection information such as a CRC.

Abstract: A control machine which uses a data amount stored in an FIFO as a trigger and allows a DMA transfer to be started according to a capacity of the FIFO allows a control machine for preparing for the DMA transfer to start to prepare a command and the like for the DMA transfer. The control machine for preparing for the DMA transfer issues the prepared command to a control machine for transferring DMA data, so that a process according to the command is started. At the time of the DMA transfer, a burden on a host CPU is reduced.

Abstract: A process is proposed for the automatic assignment of at least one client device address in a DP network, where the DP network comprises a server device and at least one client device and where the client devices exhibit a unique property, which for each client device has a different value taken from a finite group of values.

Abstract: The present invention provides methods and apparatus that utilize a portable apparatus to operate a host computer. The portable apparatus including an operating system and a list of software applications is installed in a removable data storage medium. The basic input/output system (BIOS) of the host computer will directly or indirectly identify the portable apparatus as its boot drive. The host computer will further load the operating system in the portable apparatus into its random access semiconductor memory (RAM). A hardware profile is stored in the host computer, which contains information about the host computer and its peripheral devices. During the loading, the operating system will incorporate information in the hardware profile in order to fully operate the host computer and the hardware devices defined in the profile.

Abstract: A device and a method for simulating a hard disk are disclosed. The device has a core logic chip, a main memory module and a setting module. The setting module is used to set the main memory module to have a memory access area and a hard disk access area. The core logic chip has a memory controller and a conversion interface controller for controlling data reading of the memory access area and the hard disk access area, respectively. When the core logic chip receives a read/write signal sent to the main memory module from a computer system, it determines whether this read/write signal is a memory read/write signal or a hard disk read/write signal. If the read/write signal is for memory, it is sent to the memory controller; if the read/write signal is for hard disk, it is sent to the conversion interface controller.

Abstract: The invention provides a control device and a controlled device capable of reducing a management burden on a manufacturer by means of an easy-to-use method. A TV is a control device which controls a DVD recorder, including: a device ID acquisition unit which requests the DVD recorder to transmit a device ID, and receives the device ID from the DVD recorder; a device ID determination unit which determines whether or not the device ID is an initial value; a device ID generation unit which generates a new device ID in the case where the device ID is determined to be the initial value; a device ID update unit which requests the DVD recorder to update to the new device ID; a device ID/attribute information storing unit which stores the new device ID as the device ID of the DVD recorder; and a connected device control unit which controls the DVD recorder by using the device ID stored in the device ID/attribute information storing unit.

Abstract: Semiconductor memory device with high-speed data transmission capability, system having the same includes a plurality of address input circuits and a plurality of data output circuits and a training driver configured to distribute address information input through the plurality of address input circuits together with a data loading signal for a read training, and generate data training patterns to be output through the plurality of data output circuits.

Abstract: A transmitter LSI 1 transmits a source clock, transmission data, and a transmission sync signal indicating the timing of the transmission data to a receiver LSI for establishing transmission synchronization between LSIs. The transmitter LSI 1 includes: a data transmission section that transmits, as the source clock, a transmitter LSI system clock input from outside to the receiver LSI and, at the same time, transmits the transmission data according to the transmitter LSI system clock to the receiver LSI; and one or more transmission sync signal generation sections 11 that generate the transmission sync signal based on the timing of the transmitter LSI system clock and an inter-LSI sync signal input from outside.

Abstract: An I/O interface, compatible with industry standards, for interfacing a host to a peripheral device. The interface includes a clock signal, a bus, an address latch enable signal, a peripheral device ready signal, a command signal, a device selected backoff signal, and a reset signal, resulting in an I/O interface capable of ISA-compatible operation with only 22 pins. Address, data, command, interrupt request, and DMA request information are communicated between the host and the peripheral device via a single bus by multiplexing the information on the bus using phasing techniques.

Abstract: An auxiliary computing device normally used for remotely controlling a primary device may change its functionality and extend its usefulness based on a usage context. An auxiliary device may change its usage context by connecting differently to a primary device depending on any number of parameters including distance from the device, battery life, connection method, and proximity to other devices. The device may change its usage context by interfacing with a primary device service that communicates with various applications to feed the auxiliary device different information in different usage contexts. Further, the device may control different functions of the primary device based on the usage context.

Abstract: One embodiment is directed to a method and apparatus for modifying a configuration of a computer system including a host computer and at least one computer system resource accessible to at least one application program executing on the host computer. The computer system is dynamically reconfigured, without reinitializing the host computer or the application program, to alter a manner in which the at least one application program accesses the at least one computer system resource. Another embodiment is directed to a method and apparatus for responding to changes in a configuration of the computer system impacting a manner in which the at least one computer system resource is accessed by the host computer. Information relating to a first configuration of the computer system at a first point in time is stored, the first configuration relating to a first manner of accessing the at least one computer system resource by the host computer.

Abstract: Methods and apparatus for reconnecting a host computer with a networked printer having a dynamic network address without manually entering the printer's network address. In a first method, when a user presses a reconnect button on the printer, the printer broadcasts a reconnection event containing the printer's network address over the network. The host receives the event, extracts the network address and reconnects the printer accordingly. In a second method, the host obtains the network addresses of candidate printers, displays a list of them on a UI, and sends a flash signal to the candidate printers to cause them to generate an alarm one by one. The user observes the desired printer and correlates its alarm with the timing of the flash signals sent by the host. Based on the observation, the user selects one of the candidate printers on the UI and the host reconnects it.

Abstract: An address list updating apparatus includes: a memory that stores an address list that indicates correspondence between a physical address and a logical address of each of HDMI-CEC-compliant equipments; a reception unit that receives notification regarding the logical address and the physical address from each of the HDMI-CEC-compliant equipments; a transmission unit that, when the reception unit receives the notification containing a physical address that is registered in the address list, issues an inquiry to a target HDMI-CEC-compliant equipment having a logical address corresponding to the registered physical address; and an update unit that updates the address list by adding information included in the notification received from the target HDMI-CEC-compliant equipment when a response to the inquiry is received, and by deleting information regarding the target HDMI-CEC-compliant equipment when no response is received.

Abstract: A background memory manager (BMM) for managing a memory in a data processing system has circuitry for transferring data to and from an outside device and to and from a memory, a memory state map associated with the memory, and a communication link to a processor. The BMM manages the memory, determining if each data structure fits into the memory, deciding exactly where to place the data structure in memory, performing all data transfers between the outside device and the memory, and maintaining the memory state map according to memory transactions made, and informing the processor of new data and its location. In preferred embodiments the BMM, in the process of storing data structures into the memory, provides an identifier for each structure to the processor. The system is particularly applicable to Internet packet processing in packet routers.

Abstract: Disclosed is a KVM switch identifying a peripheral for at least one computer coupled thereto. The KVM switch comprises a memory and a KVM control module. The memory stores identification data responded by the peripheral while the peripheral is being initialized by the KVM switch and stores an initializing command generated by the computer when the computer requests the identification data. The KVM control module sends the initializing command stored in the memory to the peripheral to request the identification data when the peripheral is connected to the KVM switch and replies to the computer with the identification data stored in the memory when the computer requests the identification data for identifying the peripheral. The KVM control module also updates the initializing command stored in the memory if a new initializing command is generated by the computer.

Abstract: A display apparatus includes: a plurality of external device interfaces which is connectable with an external device; an address setting unit which sets a logical address corresponding to the external device, if the external device interface is connected with the external device; a UI (user interface) generator which generates UI information to control the external device; and a controller which controls the UI generator to display an external device menu window showing a type of the external device according to the logical address corresponding to the external device, on the display unit.

Abstract: An access network system connected to an ISP network including a subscriber authentication server comprised of a plurality of packet forwarding apparatuses each for connecting user terminals to an Internet network via the ISP network and an address pool management server having an address pool management table for holding, as a sub-address pool, a plurality of IP addresses usable over the ISP network. Each of the packet forwarding apparatuses acquires from the address pool management server an IP address to be allocated to the user terminal having requested connection to the Internet when the subscriber authentication server has succeeded in authentication of the user terminal.

Abstract: A method and system for performing serial data communication between a main device and an external module connected to the main device. The data communication system and method include a main device, and an external module connected to the main device and communicating data with the main device. The external module transmits its identification information to the main device before the external module and the main device communicate the data between each other, and the main device receives the identification information from the external module, confirms its connection to the external module, and transmits an identification information confirmation signal to the external module.

Abstract: Method and system for address routing in a distributed computing system, such as a distributed computing system that uses PCI Express protocol to communicate over an I/O fabric. A destination identifier is provided to identify a physical or virtual host or end point. When a physical or virtual host or end point receives a PCI data packet it compares a list of source identifiers with destination identifiers to determine if a source identifier included in the transaction packet is associated with a destination identifier included in the transaction packet to determine if the transaction packet has a valid association. If the transaction packet has a valid association, it is routed to the target device. The present invention enables each host that attaches to PCI bridges or switches and shares a set of common PCI devices to have its own PCI 64-bit address space and enables the routing of PCI transaction packets between multiple hosts and adapters, through a PCI switched-fabric bus using a destination identifier.

Abstract: Commands transmitted and received among a plurality of processing units are efficiently controlled. A command receiver 210 receives from an external command transmitting entity a command that has assigned a memory address. An address range of memory is divided into a plurality of areas, and an assignment information storage unit 228 stores an assignment table in which a channel is assigned to each area. A command storage unit 230 contains a queue provided in accordance with each channel wherein the each queue stores received commands temporarily. A distribution destination specifying unit 224 specifies an area that corresponds to a memory address by referring to the assignment table, and an execution unit 222 transfers the received command to a command storage unit that corresponds to said area.

Abstract: Techniques for synchronizing use of buffer descriptors for data, such as packets transmitted over a network, include receiving private index data that indicates a particular buffer descriptor owned by a DMA controller, for moving data between a data port and a corresponding memory buffer. A write command is placed on a memory exchange queue to change the owner to a different processor and the private index data is incremented. A public index is determined, which indicates a different buffer descriptor in which the owner is most recently changed to the processor and is known to be visible to the processor. In response to receiving a request from the processor for the most recent buffer descriptor changed to processor ownership, the public index data is sent to the processor. Based on the public index data, the processor exchanges data with buffer descriptors guaranteed to be owned by the processor.

Abstract: In one embodiment, the present invention includes a method for providing a command from a keyboard, video and mouse (KVM) system of a first system to a graphics card of the first system via an existing system interface, sampling data from a frame buffer of the graphics card and providing the sampled data to a sample buffer of the KVM system, and processing the sampled data in the KVM system. Also, data to be displayed at a graphics card may be sent as out-of-band (OOB) data from the KVM system. Other embodiments are described and claimed.

Abstract: An identification address of a sensor interface device is configured in response to the order of connection of first (DXP1) and second (DXN1) package pins to electrodes of a sensor (Q0). A sensor signal processing circuit (23) has first and second inputs coupled through the first and second pins to the sensor for converting a parameter sensed by the sensor to a different representation. A current is forced through the first pin to produce either a high or low voltage on the first pin depending on the order of connection of the first and second pins to the electrodes of the sensor. A voltage on the first pin is compared with a reference voltage to produce a comparison signal which is mapped to produce the identification address.

Abstract: A method and apparatus are provided for controlling access to logical units, a logical unit being an addressable entity that accept commands. A plurality of logical units are accessible by one or more ports, a port being an addressable entity that sends commands. A communication means which may be a storage area network (SAN) (102, 202) provides access to the plurality of logical units by the one or more ports. One or more ports that require access to the same logical units are grouped in a named set (301, 302, 303) in a first location. The named set (301, 302, 303) is associated (300) in a subsequent location with selected logical units (304) thereby controlling the access to the logical units. Identification information for the ports in a named set is extracted at the subsequent location by referencing the named set. The sets can be physically defined, for example, by switch zoning, or logically defined by logically grouping port names.

Abstract: A method for detecting the order of attached devices and a storage device for storing a program executing the same are provided. The method includes following steps. An inquiry is issued to obtain the device information of a plurality of attached devices, and one of the device information is selected. Whether the selected device information contains an attached device address is determined. If the selected device information contains an attached device address, the next device information is selected according to the attached device address. The order in which the device information is selected is recorded as the order of these attached devices.

Abstract: The present invention relates generally to devices and methods for communicating between a host computer and a peripheral device, such as a monitor or printer, and, more particularly, to enable efficient communication between a host and a plurality of such USB peripheral devices without substantial bandwidth degradation. In one embodiment, a device driver, in data communication with a configuration application executing on a host computer, instructs a secondary USB device to accept data packets related to not only its own unique address but also of at least one other primary USB device whose address was additionally caused to be stored with the USB device.

Abstract: An address management method and a device thereof are provided. The address management method includes checking by a device whether logical addresses are currently being used by external devices; and setting by the device a non-use logical address as a logical address of the device regardless of the type of the device, if the device determines that the non-use logical address exists. Therefore, a device may use all logical addresses regardless of its device type, and may also have a logical address even though all logical addresses corresponding to its device type are currently being used.

Abstract: An input/output device and a method of setting up identification information for an input/output device, to confirm which slot of which device enclosure each unit is mounted in, within a short time, from a map, and execute quick access to the unit. A unit mounted on a device enclosure is assigned a slot identification information that does not overlap with that for another unit in the device enclosure, each device enclosure is assigned device enclosure identification information that does not overlap with that for another device enclosure, and a table is formed using unit identification information, which consists of the slot identification and the device enclosure identification information, and which does not overlap with that for another unit in the device, thus allowing a unit in the device to be specified.

Abstract: An improved high performance scheme is provided with a serial peripheral interface (SPI) to enable microcontroller-based products and other components and devices to achieve a higher serial transmit and receive data rate.

Abstract: A first reception section is operable to receive an input to designate thumbnails of printing images from an image storage server. A first transmitter is operable to transmit an image transmission request for requesting the thumbnails to the image storage server when the input to designate the thumbnails is received by the first reception section. A first receiver is operable to receive the thumbnails from the image storage server. A second reception section is operable to receive a designation of the printing images based on the thumbnails received by the first receiver. A local area transceiver is operable to transmit an identification information request for requesting identification information of a printing device to the printing device using a local area radio communication and receives the identification information from the printing device.

Abstract: A random access memory system has a memory controller, a first memory device, a second memory device, and a memory bus. The memory controller is configured to control access to a plurality of memory devices. The memory bus is configured to alternatively couple the memory controller to the first memory device and to couple the memory controller to the second memory.

Abstract: A controller which exists between a client apparatus and an image processing apparatus and which controls access from the client apparatus such that the client apparatus can use a network server function of the image processing apparatus, its control method and control program and storage medium. To accomplish this, the controller which exists between a client terminal and an image processing apparatus and which controls data transmitted from the client terminal to the image processing apparatus comprises an information providing unit which provides setup information of the controller to the client terminal and a transfer unit which transfers setup information of the image processing apparatus to the client terminal.

Abstract: A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.

Abstract: In a multiprocessor-system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a locking mechanism specific to the resources required for assignment.

Abstract: An electronic device (120) includes: an input connector (121), including at least three address pins and plural data pins; a function chip (123), including address pins and data pins corresponding to those of the input connector, and directly connected to the input connector by the data pins thereof; an adder disposed between the input connector and the function chip, and including at least three input pins and at least three output pins, the input pins being connected to the address pins of the input connector of the electronic device in one-to-one correspondence, the output pins being connected to the address pins of the function chip; and an output connector (124), including at least three address pins and plural data pins, the address pins being connected to the output pins of the adder in one-to-one correspondence, the data pins being respectively connected to the data pins of the input connector.

Abstract: The transmission of data is distributed evenly and predictably over a given number of communication channels using a hash function.

Abstract: Provided are a method, system, and program for managing data read operations of a read command such as a read command packaged in an Internet Small Computer System Interface packet. In one embodiment, a network adapter has a microengine which obtains read target data from a cache coupled to the network adapter to respond to a read command packaged in a packet sent by an initiator over a network. If the network adapter cache does not have the target data addressed by the read command, the read command is forwarded to a target controller coupled to a storage unit to process the read command.

Abstract: A method for managing an address and a video apparatus using the same are provided. The method for managing an address includes acquiring an address of the apparatus, and determining whether or not the acquired address and an address of one of the external apparatuses collide if a command for resetting an address is received from another one of external apparatuses. As a result, collision of addresses between apparatuses may be prevented.

Abstract: A semiconductor memory device includes a plurality of address pins for receiving a plurality of address signals from a chipset, and an address strobe pin for receiving an address strobe signal from the chipset.

Abstract: An integrated device is provided that includes a non-volatile memory having an addressing parallelism and a data parallelism, and a communication interface for interfacing the memory with an external bus. The external bus has a transfer parallelism lower than the addressing parallelism and the data parallelism. The communication interface includes control means for executing multiple reading operations and/or multiple writing operations on the memory according to different modalities in response to corresponding command codes received from the external bus. Also provided is a method of operating such an integrated device.

Abstract: An MXF parser thread 43 parses data MXF_D, being, mixed together, a plurality of video data PIC, a plurality of audio data SOU, and system data SYS. Then, it generates video file attribute data VFPD concerning the video based on the parsed system data and metadata META and generates video file data VF including the video file attribute data VFPD and the parsed plurality of video data PIC (VIDEO). Further, the audio file data AF is generated too in the same way.

Abstract: A circuit for buffering data is disclosed. The circuit comprises a first circuit which is coupled to receive a stream of data blocks using a first clock signal. The first circuit removes data blocks, such as idle data blocks or a sequence ordered set of a pair of consecutive sequence ordered sets, from the stream of data blocks to create a first modified data stream which is coupled to a memory device. Finally, a second circuit coupled to the memory device generates a second modified data stream using a second clock signal. The second modified data stream preferably comprises the data blocks of the first modified data stream and idle data blocks inserted among the data blocks of the first modified data stream. Methods of buffering data received in a first clock domain and output in a second clock domain are also disclosed.

Abstract: A computer system may include a system memory, an active device configured to access data stored in the system memory, where the active device includes a cache configured to store data accessed by the active device, an address network for conveying address packets between the active device and the system memory, and a data network for conveying data packets between the active device and the system memory. An access right corresponding to a given block allocated in the cache transitions in response to a corresponding data packet being received by the cache. An ownership responsibility for the given block transitions in response to a corresponding address packet being received by the cache. The access right transitions at a different time than the ownership responsibility transitions. The cache is configured to inhibit receipt of the corresponding data packet based on a value of a timestamp associated with the corresponding data packet.

Abstract: A system and method for dynamically accessing memory under normal operating conditions without interrupting computer system clocks that are otherwise executing. At least a memory access mode and a memory address(es) are scanned into a control scan chain from a maintenance system. When the scan is complete, the information is collectively transferred to an access register bank. Based on the control signals, a selection multiplexer selects the information from the control scan chain provided by the maintenance system as opposed to standard signals generated by the computer system. Memory control input signals are generated in response to a clock trigger signal, and the read or write data transfer is initiated.

Abstract: A data handling device capable of operating in a system in which two or more devices are connected by a data bus for the transmission of communications therebetween, the data bus having two or more data lines and the device having: two or more data bus connectors, each for connection to a respective data line of the data bus; an identity acquisition unit capable of functioning in a first mode of operation of the device to receive data transmitted over the data bus and in response to the order in which the bits of one or more data words of a predetermined form are received on the data bus connectors during the first mode of operation determine an identity for the device and store the identity in an identity store of the device; and a data handling unit capable of functioning in a second mode of operation of the device to handle communications transmitted over the bus and that specify the identity stored in the data store as a destination.