Abstract: An operation method of a host device configured to control a storage device includes receiving initial mapping information from the storage device, performing initial migration based on the initial mapping information such that source data present in a first region of the storage device migrate to a second region, receiving first dirty information about first dirty data of the source data from the storage device, performing first migration on the first dirty data based on the first dirty information, receiving second dirty information about second dirty data of the source data from the storage device, and performing second migration on the second dirty data based on the second dirty information, and a size of the first dirty information is different from a size of the second dirty information.

Abstract: A method of a memory device is provided. The method includes generating, by a controller of the memory device, a hashed index by hashing a source index comprising a namespace identification (NSID) and a keytag with a hash function; accessing, by the controller, a first storage address corresponding to the hashed index; comparing, by the controller, a tag portion corresponding to the first storage address with the source index to identify whether a conflict exists; and in response to identifying whether the conflict exists, obtaining, by the controller, information from the first storage address.

Abstract: A method includes detecting a voltage at a configuration terminal of a mobile industry processor interface (MIPI) radio frequency front end (RFFE) device with a timing based on a MIPI RFFE signal received by the MIPI RFFE device, and setting an address for the MIPI RFFE device based on the detected voltage.

Abstract: An apparatus supports single root input/output virtualization (SR-IOV) capable devices. The apparatus includes input/output ports, and SR-IOV capable PCIe devices. Each SR-IOV capable PCIe device has one or more namespaces or controller memory buffers. The SR-IOV capable PCIe device provides one or more physical functions and virtual functions that can access the one or more namespaces or controller memory buffers. A PCIe switch controller communicates with host servers coupled to the input/output ports, and assigns one or more virtual functions to each host device, and enables the host devices to access one or more namespaces or controller memory buffers through the assigned virtual functions.

Abstract: Providing an isolation system that allows analysts to analyze suspicious information in a way that aids in preventing harmful information from spreading to other applications and systems on a network. A plurality of virtual containers may be used by analysts to analyze suspicious information. The analyst may set the virtual environment configurations (e.g., applications, programs, settings, etc.) of the virtual container. The analyst may determine how the suspicious information effects the virtual environment configuration and/or use tools to analyze the suspicious information. When harmful information is identified the virtual container may be discarded (e.g., folded up and deleted), and a new virtual container may be provided to the analyst to continue to analyze the suspicious information and/or new suspicious information.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating signed addresses. One of the methods includes receiving, by a component from a device, a plurality of first requests, each first request for a physical address and including a virtual address, determining, by the component, a first physical address using the virtual address, generating a first signature for the first physical address, and providing, to the device, a response that includes the first signature, receiving, from the device, a plurality of second requests, each second request for access to a second physical address and including a second signature, determining, by the component for each of the plurality of second requests, whether the second physical address is valid using the second signature, and for each second request for which the second physical address is determined to be valid, servicing the corresponding second request.

Abstract: A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.

Abstract: A system for supporting a dual role controller in an information handling systems configurable as a device or a host. When the information handling system is connected to another information handling system and configured for operating in a device mode, a proxy service and an agent service execute on the information handling system. Communications from the other information handling system are received by the proxy service and sent to the agent service, which translates generic requests into application specific requests and commands. Device functions like MTP (storage), Webcam (streaming) and generic-USB commands are enabled in device mode for virtual desktop interface (VDI) or hardware isolated applications.

Abstract: A method is provided, comprising: receiving, from a host device, a request to create a token that represents one or more data items that are stored in a first volume, the first volume being stored in a source system; estimating an I/O latency limit for the first volume; estimating a token creation time for the token; comparing the token creation time to the I/O latency limit; when the token creation time matches the I/O latency limit: creating the token, creating a snapshot pair, mapping the token to the snapshot pair, and returning the token to the host device; when the token creation time does not match the I/O latency limit: creating the token, creating a first snapshot of the first volume at the source system, mapping the first snapshot to the token, and returning the token to the host device.

Abstract: A first virtual parity group management table that associates first virtual parity group management information with second virtual parity group management information using physical disk management information is created and memorized in a first sharable memory section, a second virtual parity group management table that associates logical device information, third virtual parity group management information that sets the second virtual parity group management information to virtual parity group management information regarding its own storage system, and fourth virtual parity group management information that sets the first virtual parity group management information to virtual parity group management information regarding the non-own storage system with one another is created and memorized in a second sharable memory section, and migration of a physical disk is accepted on the condition that these tables are memorized.

Abstract: An apparatus supports single root input/output virtualization (SR-IOV) capable devices. The apparatus includes input/output ports, and SR-IOV capable PCIe devices. Each SR-IOV capable PCIe device has one or more namespaces or controller memory buffers. The SR-IOV capable PCIe device provides one or more physical functions and virtual functions that can access the one or more namespaces or controller memory buffers. A PCIe switch controller communicates with host servers coupled to the input/output ports, and assigns one or more virtual functions to each host device, and enables the host devices to access one or more namespaces or controller memory buffers through the assigned virtual functions.

Abstract: Facilitating monitoring of service processors associated with a data storage system is provided herein. A system can include a monitoring component and an interpretation component. The monitoring component monitors a service processor that controls one or more functions for a data storage system. The monitoring component also generates trend data indicative of trend information for the service processor. The interpretation component performs one or more actions associated with the data storage system in response to a determination that the trend data satisfies a set of defined criteria associated with monitored conditions for the data storage system.

Abstract: Disclosed herein is a method and device for identifying a service entity in an Machine-to-Machine (M2M) system. The method for an M2M device for requesting a service includes transmitting a message requesting information on a service entity to a registry, obtaining the information on the service entity and using the service through the service entity.

Abstract: A semiconductor memory device is provided. The device includes a memory cell array including a plurality of dynamic memory cells; an error correction code (ECC) engine; an input/output (I/O) gating circuit connected between the ECC engine and the memory cell array; an error information register configured to store an error address and a first syndrome, the error address and the first syndrome being associated with a first error bit in a first codeword stored in a first page of the memory cell array; and a control logic configured to, based on the first codeword being read again and including a second error bit which is different from the first error bit, recover a second syndrome associated with the second error bit by using the first syndrome stored in the error information register and sequentially correct the first error bit and the second error bit.

Abstract: A system includes a data interface that receives data associated with a plurality of wells; an inference engine that receives and analyzes at least a portion of the data to generate results; and a communication engine that outputs information based at least in part on the results.

Abstract: A network processor includes a memory subsystem serving a plurality of processor cores. The memory subsystem includes a hierarchy of caches. A mid-level instruction cache provides for caching instructions for multiple processor cores. Likewise, a mid-level data cache provides for caching data for multiple cores, and can optionally serve as a point of serialization of the memory subsystem. A low-level cache is partitionable into partitions that are subsets of both ways and sets, and each partition can serve an independent process and/or processor core.

Abstract: The invention introduces a method for performing operations to namespaces of a flash memory device, at least including the steps: receiving a namespace setting-update command from a host, requesting to update a namespace size of a namespace; determining whether the updated namespace size of the namespace can be supported; and when the updated namespace size of the namespace can be supported, updating a logical-physical mapping table of the namespace to enable the namespace to store user data of the updated namespace size.

Abstract: A storage device includes: one or more logical blocks to store host data received from a host device, the logical blocks having a logical block address (LBA); an LBA range table to store one or more LBA ranges associated with one or more commands received from the host device over a storage interface; and an overlap check circuit to compare an LBA range associated with an active request with the one or more LBA ranges associated with the one or more commands, and to determine an overlap between the LBA range associated with the active request and any of the one or more LBA ranges associated with the one or more commands

Abstract: Multiple power management integrated circuits (PMICs) may perform communication and power sequence operation coordination between the multiple PMICs through a communication interface connected to two signal lines using a dual pin interface. The multiple PMICs include a main PMIC configured to communicate with at least one application processor through a system interface and at least one sub-PMIC configured to communicate with the main PMIC through the communication interface. A first signal line uses a single bidirectional signaling scheme, and a power status signal PSTATUS is exchanged between the main PMIC and the at least one sub-PMIC through the first signal line. A second signal line uses a single unidirectional signaling scheme, and a power sequence control signal PIF is transmitted from the main PMIC to the at least one sub-PMIC through the second signal line.

Abstract: In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.

Abstract: The technology described in this document can be embodied in a computer-implemented method that includes receiving, at one or more servers from a first computing device, (i) first identification information identifying the first computing device or an application executing on the first computing device, and (ii) second identification information identifying a second computing device. The second identification information is obtained by the first computing device by detecting changes to one or more parameters of a magnetic field generated by the second computing device. The method also includes determining, by the server based on the first information, identity information of a user associated with the first computing device, and transmitting, from the one or more servers to the second computing device, the identity information, such that the identity information is usable by the second computing device to verify an access attempt by the user.

Abstract: A data transmission method and apparatus are disclosed, and applied to a daemon process on a host machine. The method includes: obtaining information required for performing an acceleration operation in a virtual input/output ring of a target virtual accelerator, where the information required for performing the acceleration operation uses a predefined data structure, and the data structure occupies one entry of the virtual input/output ring of the target virtual accelerator; determining, according to the information required for performing the acceleration operation, information that can be recognized by the hardware accelerator; and sending the information that can be recognized by the hardware accelerator to the hardware accelerator, where the hardware accelerator is configured to obtain to-be-accelerated data according to the information that can be recognized by the hardware accelerator and perform the acceleration operation on the to-be-accelerated data.

Abstract: A technique is provided which can facilitate management of data in a memory device in a semiconductor device including the memory device and a data processing device. The semiconductor device includes a first external terminal, a second external terminal, a data processing device, and a memory device. The semiconductor device further includes a first bus coupled between the data processing device and the memory device, a second bus coupled between the data processing device and the second external terminal, a third bus coupled to the first external terminal, and a control circuit coupled to the first bus and the third bus. The control circuit has a management function of the memory device using the third bus.

Abstract: Described is an apparatus comprising a semiconductor interconnect substrate and an interface. The semiconductor interconnect substrate may be electrically coupled to one or more components mounted thereon. The interface may be operable to carry a configuration command set to the one or more components in a normal operation mode subsequent to a power-up mode.

Abstract: The present document describes systems and methods that monitor the health of a number of network-connected databases. In various embodiments, a health management subsystem measures one or more health parameters of a database and determines whether the database is operating properly. When the database is operating properly, a heartbeat associated with the database is generated. Heartbeat information is exchanged with other health management subsystems using a gossip-style protocol. Using the received and generated heartbeats, a health state table is provided that includes a health state for each database.

Abstract: A system controller, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, wherein each of the plurality of virtual memory controllers is associated with a different portion of the one or more memory devices, and provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The system controller further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, the host computing system to assign each of the plurality of physical functions to a different virtual machine running on the host computing system.

Abstract: The subject technology provides for managing a data storage system. Commands are identified into as a first command type or a second command type. The commands identified as the first command type are assigned to a first queue, and the commands identified as the second command type are assigned to a second queue. After the commands from the first queue and the commands from the second queue are processed based on a scheduling ratio over a predetermined period of time, a write amplification factor, number of host read commands, and number of host write commands during the predetermined period of time are determined. The scheduling ratio is updated based on the write amplification, the number of host read commands, the number of host write commands, and a predetermined scheduling ratio factor. Subsequent commands are processed from the first queue and the second queue based on the updated scheduling ratio.

Abstract: A control apparatus externally connected with a display apparatus having a touch panel, the control apparatus includes: a first receiving unit configured to receive panel information related to a touch detection method used in the touch panel from the display apparatus; a second receiving unit configured to receive a predetermined operation to the touch panel from the display apparatus; and a user interface (UI) control unit configured to control a UI used for (1) displaying an item on the display device, (2) detecting the predetermined operation to the item, and (3) accepting a predetermined instruction corresponding to the detection result, wherein the UI control unit is further configured to carry out display control for the item or detection control for the predetermined operation to the item on the basis of the panel information.

Abstract: Some examples described herein provide for dynamically reconfiguring a base address register (BAR) of a Peripheral Component Interconnect Express (PCIe) configuration space. In an example, information relating to a BAR of a PCIe configuration space is written to a PCIe extended configuration space of the PCIe configuration space, which is read, by a dynamic BAR module. Respective values are written, by the dynamic BAR module, to bits of the BAR based on the information. After writing by the dynamic BAR module, a set value is attempted to be written to each of address bits of the BAR. Writing the set value to an address bit of the BAR is prevented when the address bit is set to a predefined value. After attempting to write, a read value is read from the bits of the BAR. A base address of memory is written to the BAR based on the read value.

Abstract: A method of dynamic binding and unbinding thin logical storage volumes to data volumes stored in a storage array includes creating a snapshot copy of a user file system, storing the snapshot copy of the user file system in a data volume in the storage array, and binding a logical storage volume to the data volume. The logical storage volume is then used, by a snapshot file system, to access the data volume. If the data volume is not accessed for a period of time, the logical storage volume is unbound from the data volume while maintaining the snapshot copy of the user file system in the data volume. If an access event later occurs on the data volume, a second logical storage volume is bound to the data volume and used by the snapshot file system to access the data volume in connection with the access event.

Abstract: A method for writing multiple copies into a storage device includes receiving a first write data request that includes an identity (ID) of a first logical storage unit, target data, and a logical block address (LBA) of the first logical storage unit, determining that data stored in storage space corresponding to the LBA of the first logical storage unit is not accessed by another data access request, writing the target data into the storage space corresponding to the LBA of the first logical storage unit, generating a second write data request that includes an ID of a second logical storage unit, the target data, and an LBA of the second logical storage unit, and writing the target data into storage space corresponding to the LBA of the second logical storage unit.

Abstract: Bulk store and load operations of configuration state registers. An instruction to perform a bulk operation for a group of configuration state registers having a common characteristic is executed. To perform the bulk operation for the group of configuration state registers, a plurality of operations is performed, and based on performing the plurality of operations, the instruction is completed.

Abstract: Disclosed are puzzle devices for production of one or more puzzles. The puzzle devices can include a body and at least one input device. The body can include a plurality of panels, each panel configured to display one or more visual indicators. The at least one input device can include a plurality of panels, each panel configured to display a visual indicator. The at least one input device can move relative to the body to align one or more panels of the input device with one or more panels of the body. The body can further include a plurality of visual output devices configured to generate visual indicators on the plurality of panels of the body.

Abstract: A computer-implemented method according to one embodiment includes establishing, by an initiator, a discovery session type. A request is sent by the initiator for identifying a target. The request includes an identity key value pair that specifies at least one target identity, and a target characteristic key value pair that specifies a target characteristic. A response is received by the initiator from a target matching the key value pairs. The response includes path information of the target. In response to receiving the response the target is connected to by the initiator using the path information. A computer program product for establishing a connection between an initiator and a target according to one embodiment includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and/or executable by an initiator to cause the initiator to perform the foregoing method.

Abstract: An example method for facilitating remote memory access with memory mapped addressing among multiple compute nodes is executed at an input/output (IO) adapter in communication with the compute nodes over a Peripheral Component Interconnect Express (PCIE) bus, the method including: receiving a memory request from a first compute node to permit access by a second compute node to a local memory region of the first compute node; generating a remap window region in a memory element of the IO adapter, the remap window region corresponding to a base address register (BAR) of the second compute node; and configuring the remap window region to point to the local memory region of the first compute node, wherein access by the second compute node to the BAR corresponding with the remap window region results in direct access of the local memory region of the first compute node by the second compute node.

Abstract: Techniques related to graphics processor workload acceleration are discussed. Such techniques may include combining multiple media tasks into one function call, providing a single batched media command set for the media tasks based on the one function call and a batched media command template, and performing the media tasks based on the single batched media command set to generate output media data.

Abstract: Embodiments of the present disclosure relate to methods and apparatus for peripheral device discovery, the detection of orientation of a connector having multiple degrees of rotational symmetry, and the provision of appropriate signal paths between a host device and a peripheral device. Some embodiments provide a characteristic impedance within the peripheral device that is coupled between rotationally symmetric contacts of the connector and thus enables detection of the connector orientation. The value of the characteristic impedance may be used in some embodiments to determine the type or model of peripheral device. Some embodiments are concerned with the enablement of appropriate signal paths to a peripheral device having a transducer (e.g. a loudspeaker) coupled only to rotationally symmetric contacts of the connector, such as headphones implemented in a “balanced” configuration.

Abstract: A method of controlling a data processor to perform data processing operations is disclosed in which a host processor prepares one or more queue(s) of operations for execution by the data processor. When an error is encountered in the processing of an operation for one of the one or more queue(s), a queue can be set into an error state in which instructions that may have a data dependency on another operation are not executed. The host processor includes in the queues error barrier instructions that divide the respective queues into sets of operations between which there are no data processing dependencies. An error state for a queue can thus be cleared when its processing reaches the next error barrier instruction in the queue.

Abstract: A collision detection system has one or more sensors for determining an instantaneous velocity of a vehicle. A computer is interfaced to the one or more sensors. The computer obtains the instantaneous velocity of the vehicle from the one or more sensors. The computer is operatively configured to execute software that operates the computer to iteratively calculate an acceleration of the vehicle as a rate of change of the instantaneous velocity over a period of time. The software declares a collision when the acceleration is greater than a predetermined value (e.g. 1.1 g) or the acceleration is less than a predetermined negative value (e.g. ?1.1 g). In another embodiment, the microprocessor declares a collision when the acceleration/deceleration or the turning angle or the turning radius values exceed factory setting for the vehicle. The software determines the severity of collision based on the magnitude of deviation from the predetermined values.

Abstract: Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. That is, the I/O device can benefit from a traditional I/O model where the I/O device driver manages some of the compute resources in the I/O device as well as the benefits of adding other compute resources in the I/O device to the same coherent domain used by the hardware in the host computing system. As result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as, e.g., CPU-to-CPU communication in the host. At the same time, the compute resources in the I/O domain can benefit from the advantages of the traditional I/O device model which provides efficiencies when doing large memory transfers between the host and the I/O device (e.g., DMA).

Abstract: An external device includes: an arrangement unit for arranging an operation terminal in which at least a part of a display area of the operation terminal is covered; an arrangement detector for detecting that an operation terminal is arranged on the arrangement unit; an external communicator for transmitting, to the operation terminal, a pairing request signal for wireless communication; and a pairing command input unit provided in an area covering a display area of a touch panel and for receiving input of a command that instructs execution of pairing with the operation terminal, wherein the external communicator is configured to transmit the pairing request signal when the arrangement detector detects that an operation terminal is arranged on the arrangement unit, and pairing with the operation terminal is executed when the command is input and an input operation to a predetermined area of a touch panel is detected.

Abstract: An industrial device communication system comprising: industrial devices that function as communication masters; industrial devices that function as communication slaves that receive control data from the industrial devices that function as communication masters; communication lines that communicably connect the industrial devices to one another; one or more switches for causing a communication group including the industrial devices that function as communication masters and the industrial devices that function as communication slaves to communicate independently from one or more other communication groups; and one or more switch controllers that control the one or more switches, causing the switches to switch between a state in which an inter-group communication line present between the communication group and the one or more other communication groups is disconnected, and a state in which the disconnected inter-group communication line is connected, according to the communication group that independently co

Abstract: Described herein are techniques related to one or more systems, apparatuses, methods, etc. for implementing a location-based power saving solution for docking station products. A wireless docking station communicates with a docking wireless device. The docking station is activated when the docking wireless device when the docking wireless device is within a pre-configured coverage area of the docking station. The docking station is deactivated when the docking wireless device when the docking wireless device is outside the pre-configured coverage area.

Abstract: Disclosed embodiments relate to look up table operations implemented in a digital data processor. A look up table read instruction recalls data elements of a specified data size from table(s) and stores recalled data elements in successive slots in a destination register. Disclosed embodiments promote data elements to a larger size with selected sign or zero extension. A source operand register stores vector offsets from a table start address. A destination operand stores the results of the look up table read. The look up table instruction implies a base address register and a configuration register. The base address register stores a table base address. The configuration register sets various look up table read operation parameters.

Abstract: This disclosure describes systems, methods, and devices related to Wi-Fi based wireless docking Wi-Fi based wireless docking. A device may coordinate with one or more docking stations on a Wi-Fi network to determine a first docking channel to be used for wireless docking of a first station device. The device may adjust a transmit (TX) power of a beacon frame during a discovery mode associated with the wireless docking. The device may determine a discovery channel configured to be different from the first docking channel used for the wireless docking. The device may identify a request from a first station device requesting wireless docking, wherein the request is received on the discovery channel. The device may initiate a wireless docking session with the first station device using the first docking channel.

Abstract: Systems and methods for use in a media playback system comprising one or more playback devices are disclosed, where a playback device has a corresponding first set of device attributes used by a first controller application. The methods include: (i) identifying a second set of device attributes used by a second controller application to control the playback device, (ii) selecting a second device attribute for the playback device from the second set of device attributes based at least in part on a first device attribute; (iii) storing the selected second device attribute in the first set of device attributes; and (iv) controlling at least one function of the playback device using the selected second device attribute.

Abstract: Systems and techniques for trustworthy peripheral transfer of ownership are described herein. A unique peripheral identifier may be received from an ownership manifest of the peripheral device. The unique peripheral identifier may be transferred to a bus controller for a bus between the computing device and the peripheral device. A measurement may be received from the peripheral device by the basic input and output system of the computing device. A measurement of a computing platform of the computing device may be generated. The measurement may indicate peripheral devices interconnected to the computing device. Data transfer between the peripheral device and the computing device may be allowed via the bus based on validation of the measurement of the computing platform against a platform configuration register of the computing device.

Abstract: An arrangement that includes a bus subscriber with two power supply terminals, at least one bus line terminal and a bus interface circuit for controlling a data flow via the at least one bus line terminal, wherein a controllable switch is located between the bus interface circuit and the at least one bus line terminal and the bus subscriber contains a sensor circuit which records the voltage between the power supply terminals or a voltage derived therefrom and closes the controllable switch if the recorded voltage exceeds a threshold value and opens the same if the recorded voltage fails to reach the threshold value, where with an arrangement including at least two bus subscribers, these bus subscribers are connected with their bus line terminals to a bus having at least one bus line and with their power supply terminals via two current lines to a shared voltage source.

Abstract: The nonvolatile memory module includes at least one nonvolatile memory device and a device controller configured to receive a storage command from an external device and to perform an operation corresponding to the received storage command. The device controller includes a random access memory (RAM). After completing the corresponding operation, the device controller stores status information in the RAM and then transmits an alert signal to the external device.

Abstract: Systems and methods of configuring process control systems for operating process plants including multi-variable devices are disclosed herein. Multi-variable devices generate data associated with primary parameters and subsequent parameters. To facilitate configuration and use of subsequent parameters within process control systems, new device objects may be generated to represent the subsequent parameters. The new device objects may be generated as child device objects of parent device objects representing the multi-variable devices. Each child device object may also have a unique tag to identify the new device object within the process control system. The subsequent parameters of the multi-variable devices may thus be used within the process control system by reference to the tags of the corresponding child device objects.