Input/output Addressing Patents (Class 710/3)
  • Patent number: 10055248
    Abstract: Systems and methods for scheduling virtual processors via memory monitoring are disclosed. In one implementation, a hypervisor running on a host computer system may detect a task switch event associated with a virtual processor running on a physical processor of the host computer system. The hypervisor may test a polling flag residing in a memory accessible by the guest software running on the virtual processor and set the polling flag to a non-polling state. The hypervisor may then process the task switch event.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: August 21, 2018
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 10045387
    Abstract: Disclosed are a method for constructing a docking protocol for using a docking service in a direct communication system, and an apparatus therefor. To this end, a method by which a first wireless device constructs a docking protocol with a second wireless device comprises: a step for searching for a probe; a step for searching for a service; a step for enabling the first wireless device to construct an application service platform (ASP) session with the second wireless device; and a step for enabling the first wireless device to construct a docking protocol with the second wireless device. At this point, the step for constructing the ASP session can be selectively performed according to the capability or the device type of the first wireless device or the second wireless device.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: August 7, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Dongcheol Kim, Jaeho Lee, Byungjoo Lee
  • Patent number: 9990056
    Abstract: An input device includes a detection unit, a first acquisition unit, a second acquisition unit, and a compensation unit. The detection unit is configured to detect an operation by a user for controlling an electronic device and output an operation signal corresponding to the operation. The first acquisition unit is configured to acquire the detected operation signal and a differential value of the operation signal. The second acquisition unit is configured to acquire a function defined by the differential value to compensate for a delay in response of the operation signal with respect to the operation by the user. The compensation unit is configured to compensate the operation signal with the acquired function.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: June 5, 2018
    Assignee: Sony Corporation
    Inventor: Kazuyuki Yamamoto
  • Patent number: 9959237
    Abstract: A system-on-chip including non-hopping bus interfaces and a hopping bus. The non-hopping bus interfaces include a first non-hopping bus interface and a second non-hopping bus interface. The first non-hopping bus interface is configured to, based on a first protocol, receive information. The hopping bus includes intra-chip adaptors. The intra-chip adaptors are connected in series and respectively to the non-hopping bus interfaces. The intra-chip adaptors are configured to (i) according to a second protocol, convert the information into a first format for transmission over the hopping bus, and (ii) transfer the information in the first format over the hopping bus and between the intra-chip adaptors. The second protocol is different than the first protocol. The second non-hopping bus interface is configured to receive the information from the hopping bus based on the transmission of the information over the hopping bus.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: May 1, 2018
    Assignee: Marvell World Trade Ltd.
    Inventor: Hongming Zheng
  • Patent number: 9933976
    Abstract: A storage apparatus has a plurality of hardware engines which send and receive information to and from a controller, which, on the condition of acquiring a request command from a host, determines identifying information of the request command, executes data I/O processing to the storage device according to the request command when first identifying information has been added to the request command and when second identifying information has been added to the acquired request command, transfers the request command to the hardware engine, acquires the data requested by the hardware engine from the storage device and transfers the acquired data to the hardware engine. The hardware engine acquires and analyzes an add-on command from the host and according to the request command, requests the controller to transfer the data based on the analysis result, and thereafter executes processing to the data transferred by the controller according to the add-on command.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: April 3, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Tsujimoto, Satoru Watanabe, Yoshiki Kurokawa, Mitsuhiro Okada, Akifumi Suzuki
  • Patent number: 9921763
    Abstract: Providing for a memory apparatus comprising multiple banks of non-volatile memory and a high-speed data bus is described herein. By way of example, the memory apparatus can employ a standard or near-standard DRAM bus as an interface to high-performance two-terminal memory arrays. Interleaved operation can facilitate throughputs over 2gigabytes/second, in various embodiments, and larger throughputs in at least some embodiments, by interleaving multiple memory banks that are separately addressed via one or more mode registers, referred to as an index register(s). Further, the memory apparatus can have one or two terabytes of total storage, with capacity to increase storage volume. According to various embodiments, the memory apparatus can operate with a standard DRAM controller, or a memory controller configured with a DRAM communication protocol, modified in software or firmware to match configurations of the non-volatile memory employed for the multiple banks of memory.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: March 20, 2018
    Assignee: CROSSBAR, INC.
    Inventor: Cliff Zitlaw
  • Patent number: 9892024
    Abstract: A device may be run in a timing testing mode in which the device is configured to disrupt timing of processing that takes place on the one or more processors while running an application with the one or more processors. The application may be tested for errors while the device is running in the timing testing mode.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: February 13, 2018
    Assignee: SONY INTERACTIVE ENTERTAINMENT AMERICA LLC
    Inventors: Mark Evan Cerny, David Simpson
  • Patent number: 9841902
    Abstract: Systems and methods presented herein provide for SSD data storage via PCIe controllers configured with NVMe interfaces. In one embodiment, a PCIe controller includes a plurality of buffers, a Dynamic Random Access Memory (DRAM) device, and an I/O processor operable to partition the DRAM device into a plurality of logical blocks. The controller also includes virtual function logic communicatively coupled to the logical blocks of the DRAM device and to the buffers. The virtual function logic is coupled to a host system through the I/O processor to process an I/O request from the host system to a logical block of the DRAM device, to retrieve data from the logical block to at least one of the buffers, and to transfer the data from the buffer to the host system.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: December 12, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Anant Baderdinni, Horia Cristian Simionescu
  • Patent number: 9841527
    Abstract: A method of processing electromagnetic signal data includes: disposing a downhole tool in a borehole in an earth formation, the downhole tool including at least one electromagnetic transmitter; performing a downhole electromagnetic operation, the operation including transmitting an electromagnetic pulse from the transmitter into the formation and measuring a time domain transient electromagnetic (TEM) signal over a selected time interval following a transmitter turn-off time; transforming the measured time domain TEM signal into a frequency domain TEM signal measured; and applying an inversion technique to the transformed frequency domain TEM signal to estimate one or more formation parameters.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: December 12, 2017
    Assignee: BAKER HUGHES, A GE COMPANY, LLC
    Inventor: Marina N. Nikitenko
  • Patent number: 9817730
    Abstract: The following description is directed to storing properties of requests to potentially block future requests having similar properties. In one example, a request can be received. A property of the request can be stored so that the property persists across an initialization sequence of a computer system. At least the property can be used to determine whether to block any future requests having similar properties.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: November 14, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Craig Wesley Howard, Matthew Graham Baldwin, Donavan Miller
  • Patent number: 9817647
    Abstract: Disclosed is a method and apparatus for mobile media with both dedicated readable and writeable user data space and dedicated readable and writeable drive device space. The mobile data storage media adapted for operatively working with a drive device comprises a data space accessible by an end user and a drive software space accessible by the drive device and inaccessible by an end user. The drive software space is adapted to accommodate firmware for use by the drive device in addition to the reading and writing of software by the drive device. The media is adapted to receive and store software from the drive device or, alternatively, is adapted to transmit software to the drive device.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: November 14, 2017
    Assignee: Spectra Logic Corporation
    Inventors: Matthew Thomas Starr, Mark Lorin Lantry
  • Patent number: 9792245
    Abstract: Embodiments herein provide for efficient memory mapping in a PCIe device when a host changes memory allocations in the device. One PCIe device comprises a plurality of Base Address Registers (BARs) defined by the host. The device also includes a processor with an address space. The processor maps addresses of the address space to the BARs for routing PCIe packets from the host. The processor can determine that the host is reconfiguring the BARs, and, based on the determination, mark packets existing in the computer memory as old, change the BARs in the computer memory as directed by the host, mark packets received after the BAR change as new, process the old packets from the computer memory based on their addresses of the address space until a new packet is reached, and to remap the BARs to the addresses of the address space after the new packet is reached.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: October 17, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Ramprasad Raghavan, Eugene Saghi
  • Patent number: 9784097
    Abstract: A method for transmitting data from a downhole location to a location at the surface of the earth includes determining a minimum value and a maximum value of M-samples of data values, determining a keycode for the M-samples of data values that provides an indication of the maximum and minimum values of the M-samples, and encoding the keycode and the data values into one or more encoded words. The one or more encoded words are then transmitted as an acoustic signal in drilling fluid by modulating a mud-pulser. The acoustic signal is received by a transducer uphole from the mud-pulser and converted into an electrical signal. The electrical signal is demodulated into a received encoded word, which is decompressed into the M-samples in accordance with the keycode. The M-samples are then received by a computer processing system disposed as the surface of the earth.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: October 10, 2017
    Assignee: BAKER HUGHES INCORPORATED
    Inventor: Bryan C. Dugas
  • Patent number: 9753879
    Abstract: A switching apparatus to adapt an interface for multi-functional use includes a signal source, a display unit, a control unit, and a connector. The signal source includes a first power output and a data output. The display unit includes a power input and a data input. The control unit includes a switching chip having a control signal input, a first data pin, a second data pin, and a third data pin. The connector includes a second power input, a second power output, and a data output. The control signal input receives a switching signal. When the second data pin communicates with the first data pin according to the switching signal, the first power output is electrically coupled to the second power input, the signal source provides power for an electronic device connected with the connector.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: September 5, 2017
    Assignees: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Xi-Huai He, Chun-Sheng Chen
  • Patent number: 9742475
    Abstract: A system and method are provided in which a radio-frequency channel is used in combination with a second validation channel to verify the proximity of two devices to each other. An RF channel is used to detect whether two devices are within a first, larger distance from one another and to enable communication between the two devices, whilst a second, validation channel is used to accurately verify that the two devices are within second, smaller distance from one another. In some embodiments, the second verification channel is a magnetic channel.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: August 22, 2017
    Assignee: Sensor Labs Limited
    Inventors: Edward Pellew, William Neep
  • Patent number: 9678678
    Abstract: According to an aspect of an embodiment, a method of retrieving data in a storage network may include determining a list of storage blocks of a storage network for potential retrieval of a data file for storage on a first storage block of the storage network. The determining may be based on two or more of: assignment information of the data file as assigned by a storage network manager, location information, device types, peer-to-peer reachability, network information, and presence information. The method may also include attempting to retrieve the data file from a second storage block included in the list of storage blocks for storage on the first storage block. Further, the method may include attempting to retrieve the data file from a third storage block included in the list of storage blocks for storage on the first storage block when retrieval from the second storage block fails.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: June 13, 2017
    Assignee: LYVE MINDS, INC.
    Inventors: Randeep Singh Gakhal, Tapani Otala, Stanley Ho
  • Patent number: 9665443
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for providing filtered backups of a distributed database. One of the methods includes receiving a user request to generate an incremental backup to be added to a user specified backup sequence for a distributed database, wherein the user specified backup sequence specifies a subset of one or more database tables to be included in backups in the user specified backup sequence. Dirty partitions of the one or more tables covered by the user specified backup sequence are identified, wherein a dirty partition is a table partition that was created or modified after generation of a most recent backup in the user specified backup sequence. An incremental backup to be added to the user specified backup sequence is generated, the incremental backup comprising contents of the dirty partitions of the tables covered by the user specified backup sequence.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: May 30, 2017
    Assignee: Pivotal Software, Inc.
    Inventors: Swetha Devarayasamudram Nagendran, Ivan D. Novick, James Bryan McAtamney, Abhijit B. Subramanya, Richa Sharma
  • Patent number: 9667007
    Abstract: Systems and methods for configuring contacts of a first connector includes detecting mating of a second connector with the first connector and in response to the detection, sending a command over one of the contacts and waiting for a response to the command. If a valid response to the command is received, the system determines the orientation of the second connector. The response also includes configuration information for contacts in the second connector. The system then configures some of the other contacts of the first connector based on the determined orientation and configuration information of the contacts of the second connector.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: May 30, 2017
    Assignee: APPLE INC.
    Inventors: Jeffrey J. Terlizzi, Scott Mullins, Alexei Kosut, Jahan Minoo
  • Patent number: 9661022
    Abstract: A control unit that is configured to instruct a device to implement a limitation on a port and broadcast a controller address. The control unit is further configured to receive first identification information associated with a second device connected to the port from the device, the first identification information being addressed to the controller address. Additionally, the control unit is configured to establish a communication link with the second device through the device and the port, receive second identification information associated with the second device over the communication link, determine whether the second device is authorized based on a policy, determine whether the first identification information and second identification information match, and instruct the first device to remove the limitation on the port in response to determining that the second device is authorized and that the first identification information matches the second identification information.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: May 23, 2017
    Assignee: DELL PRODUCTS L.P.
    Inventors: Sudhir Vittal Shetty, Arun Sarat Yerra, Harish R. Gajulapalle
  • Patent number: 9612991
    Abstract: Methods and apparatus, including computer program products, are provided for connector interface mapping. In one aspect there is provided a method. The method may include detecting, at a first device, an orientation of a data connector connectable to a data interface, the data interface having a first portion and a second portion, the first portion coupled to a single port of a first type at the first device; sending, by the first device, the detected orientation information to a second device; and receiving, at the first device including the single port, data sent by the second device to the single port. Related apparatus, systems, methods, and articles are also described.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: April 4, 2017
    Assignee: Nokia Technologies Oy
    Inventors: Pekka E. Leinonen, Kai Inha, Timo T. Toivola, Pekka Talmola, Rune Lindholm, Timo J. Toivanen
  • Patent number: 9602464
    Abstract: Techniques and mechanisms to enable addressing of components accessed via a control interface. In an embodiment, a plurality of identifiers is logically split into first and second pools. The first pool is available for assigning to allow addressing of components while such components are active with respect to some functionality. The second pool is available for assigning to allow addressing of components while such components are passive with respect to some functionality. In another embodiment, different respective identifiers of the first pool pool are assigned each of first one or more of the plurality of components, and a respective identifier of the second pool is assigned to each of second one or more of the plurality of components. Any two of the second one or more components that have the same address default are assigned different respective identifiers of the second pool.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Werner Hein, Martin Polak, David Loesch
  • Patent number: 9569391
    Abstract: Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Clinton E. Bubb, Daniel F. Casper, John R. Flanagan, Raymond M. Higgs, George P. Kuch, Jeffrey M. Turner
  • Patent number: 9471234
    Abstract: A method may include, in a chassis configured to receive a plurality of modular information handling systems and a plurality of modular information handling resources, exposing a first virtual function instantiated on a management processor disposed in the chassis to a switch interfaced between a modular information handling system and the management processor. The method may also include communicating, by the management processor, an input/output request from the modular information handling system received by the first virtual function to at least one of a second virtual function instantiated on a first storage controller communicatively coupled to the management processor and a third virtual function instantiated on a second storage controller communicatively coupled to the management processor. The method may further include receiving, by the management processor, an acknowledgment of completion of the input/output request from at least one of the second virtual function and the third virtual function.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: October 18, 2016
    Assignee: Dell Products L.P.
    Inventors: Kiran Kumar Devarappalli, Krishnaprasad Koladi
  • Patent number: 9471526
    Abstract: A system including a controller and a bridge module. The controller is configured to (i) communicate with a host via a first interface, and (ii) communicate with a storage device via a second interface. The second interface is separate from the first interface. The bridge module is configured to allow the controller to transfer data between the storage device and the host without buffering the data, and to access a memory of the host via the first interface during the transfer.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 18, 2016
    Assignee: Marvell World Trade LTD.
    Inventors: Chun-Lun Lin, Kanting Tsai, Dishi Lai, Hsi-Cheng Chu
  • Patent number: 9465852
    Abstract: A method and a system are provided for encoding and processing digital information. The digital information is encoded according to binary encoding formats corresponding to primitive data types. The primitive data types comprise scalar data types including Boolean, integer, float, decimal, time stamp, string, symbol, binary large object, and character large object data types. The primitive data types also comprise composite data types including structure, list, and S-expression data types. The binary-encoded digital information is stored in a message with a predetermined format for transmission. No metadata is included in the message.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: October 11, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Andrew J. Lusk, Todd V. Jonker, Chris A. Suver
  • Patent number: 9436823
    Abstract: A method and apparatus are provided to detect malicious code in a computing system, where the malicious code is obscured by manipulation of an input/output memory management unit. A peripheral component interconnect express (PCIe) device requests a translation of a bus address for a given device in the system and determines whether the requested translation was received. If the requested translation was received, the PCIe device further determines whether the bus address for the given device corresponds to a physical address for the given device. If the bus address for the given device does not correspond to the physical address for the given device, the PCIe device sends a notification that the computing system is potentially compromised.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: September 6, 2016
    Assignee: Google Inc.
    Inventors: Benjamin Charles Serebrin, Brandon S. Baker
  • Patent number: 9436272
    Abstract: A computer program product for processing input/output (I/O) data is provided for performing a method, which includes receiving a control word having an indirect data address including a starting location of a list of storage addresses, gathering the data and transmitting gathered data to a control unit in the I/O processing system. Gathering includes accessing an entry of the list, the entry located at an entry storage location and including an address. Based on the entry of the list indicating that the address is a data address, data is gathered from a data storage location, and a next entry of the list is accessed. Based on the entry of the list indicating that the address is an address of a next entry of the list, the next entry of the list is obtained from another storage location that is located non-contiguously to the entry storage location.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: September 6, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel F. Casper, Mark P. Bendyk, John R. Flanagan, Catherine C. Huang, Matthew J. Kalos, Ugochukwu C. Njoku, Dale F. Riedy, Gustav E. Sittmann, III, Harry M. Yudenfriend
  • Patent number: 9418223
    Abstract: An information handling system includes a processor operable to provide a branch trace message, and an embedded controller coupled to the processor via a primary interface and via a management interface. The embedded controller receives a management transaction from the processor via the primary interface. In response to receiving the management transaction, the embedded controller requests the branch trace message via the management interface and determines if the processor is operating in a system management mode based upon the branch trace message.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: August 16, 2016
    Assignee: Dell Products, LP
    Inventors: Matthew G. Page, Richard M. Tonry
  • Patent number: 9386449
    Abstract: A management server includes a user management database in which mobile terminal identification information on the mobile terminal and working machine identification information on a sold working machine are registered in association with each other, a user registration determination unit adapted to determine whether or not the mobile terminal and the working machine are registered in association with each other on the basis of the mobile terminal identification information and the working machine identification information outputted from the mobile terminal and the mobile terminal identification information and the working machine identification information stored in the user management database, and an authorization information output unit adapted to output an authorization key necessary for wireless communication between the mobile terminal and the working machine in the case where the user registration determination unit determines that the mobile terminal and the working machine are registered in associa
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: July 5, 2016
    Assignee: KUBOTA CORPORATION
    Inventors: Keisuke Miura, Isao Tanaka, Yasuhisa Uoya, Takafumi Morishita
  • Patent number: 9372799
    Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: June 21, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Daniel B Wu, Matthew D Pierson, Kai Chirca, Timothy D Anderson
  • Patent number: 9361292
    Abstract: Systems and methods for intelligent language models that can be used across multiple devices are provided. Some embodiments provide for a client-server system for integrating change events from each device running a local language processing system into a master language model. The change events can be integrated, not only into the master model, but also into each of the other local language models. As a result, some embodiments enable restoration to new devices as well as synchronization of usage across multiple devices. In addition, real-time messaging can be used on selected messages to ensure that high priority change events are updated quickly across all active devices. Using a subscription model driven by a server infrastructure, utilization logic on the client side can also drive selective language model updates.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: June 7, 2016
    Assignee: Nuance Communications, Inc.
    Inventors: Andrew Phillips, David J. Kay, Erland Unruh, Eric Jun Fu
  • Patent number: 9256551
    Abstract: In an embodiment, a peripheral interface controller may include an inline cryptographic engine which may encrypt data being sent over a peripheral interface and decrypt data received from the peripheral interface. The encryption may be transparent to the device connected to the peripheral interface that is receiving/supplying the data. In an embodiment, the peripheral interface controller is included in a system on a chip (SOC) that also includes a memory controller configured to couple to a memory. The memory may be mounted on the SOC in a chip-on-chip or package-on-package configuration. The unencrypted data may be stored in the memory for use by other parts of the SOC (e.g. processors, on-chip peripherals, etc.). The keys used for the encryption/decryption of data may remain within the SOC.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: February 9, 2016
    Assignee: Apple Inc.
    Inventors: Timothy R. Paaske, David S. Warren, Michael J. Smith, Diarmuid P. Ross, Weihua Mao
  • Patent number: 9256568
    Abstract: A PCI-based interfacing device with mappable port addresses to legacy I/O port addresses has an addressing circuit, a PCI controller connected to the addressing circuit and a PCI port, and an equipment controller connected to the PCI controller and an equipment port. The addressing circuit sets up a legacy I/O port address. The PCI controller transmit and receive data packets having data and one of the set of legacy I/O port addresses encapsulated therein to be processed to and from the PCI port, and output the received data packets to the equipment controller. The equipment controller converts the data packets into equipment data corresponding to the equipment port, and transmits the equipment data to the equipment port. Accordingly, the PCI-based interfacing device can perform data communication with legacy I/O port addresses.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: February 9, 2016
    Assignee: SUNIX CO., LTD.
    Inventors: Ming-Cheng Lin, Chieh-Tung Chien
  • Patent number: 9239799
    Abstract: A memory management unit (MMU) for servicing transaction requests from one or more processor threads is described. The MMU can include a translation lookaside buffer (TLB). The TLB can include a storage module and a logic circuit. The storage module can store a bit indicating one of a plurality of interfaces. The bit can be associated with a physical address range. The logic circuit can route a physical address within the physical address range to the one of the plurality of interfaces.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: January 19, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Ajay Anant Ingle, Christopher Edward Koob
  • Patent number: 9215210
    Abstract: For a host that executes one or more guest virtual machines (GVMs), some embodiments provide a novel virtualization architecture for utilizing a firewall service virtual machine (SVM) on the host to check the packets sent by and/or received for the GVMs. In some embodiments, the GVMs connect to a software forwarding element (e.g., a software switch) that executes on the host to connect to each other and to other devices operating outside of the host. Instead of connecting the firewall SVM to the host's software forwarding element that connects its GVMs, the virtualization architecture of some embodiments provides an SVM interface (SVMI) through which the firewall SVM can be accessed to check the packets sent by and/or received for the GVMs.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: December 15, 2015
    Assignee: NICIRA, INC.
    Inventors: Chids Raman, Subrahmanyam Manuguri, Todd Sabin
  • Patent number: 9200508
    Abstract: A apparatus for monitoring a downhole component is disclosed. The apparatus includes: an optical fiber sensor including a plurality of sensing locations distributed along a length of the optical fiber sensor; an interrogation assembly configured to transmit an electromagnetic interrogation signal into the optical fiber sensor and receive reflected signals from each of the plurality of sensing locations; and a processing unit configured to receive the reflected signals, select a measurement location along the optical fiber sensor, select a first reflected signal associated with a first sensing location in the optical fiber sensor, the first sensing location corresponding with the measurement location, select a second reflected signal associated with a second sensing location in the optical fiber sensor, estimate a phase difference between the first signal and the second signal, and estimate a parameter of the downhole component at the measurement location based on the phase difference.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: December 1, 2015
    Assignee: Baker Hughes Incorporated
    Inventors: Roger G. Duncan, Brooks A. Childers, Robert M. Harman, Ajit Balagopal
  • Patent number: 9190141
    Abstract: Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations are disclosed. Related systems and methods are also disclosed. To reset a plurality of SRAM bitcells in a single reset operation, a biasing circuit is provided and coupled to the plurality of SRAM bitcells. The biasing circuit is configured to apply a voltage or current bias to the SRAM bitcells during a reset operation after power provided to the SRAM bitcells is collapsed to a collapsed power level below an operational power level. The bias is applied as the power to the SRAM bitcells is restored to an operational power level, thus forcing the SRAM bitcells into a desired state. In this manner, the SRAM bitcells can be reset in a single reset operation without need for an increased drive strength from a reset circuit and without need to provide specialized SRAM bitcells.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: November 17, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Chiaming Chai, Satendra Kumar Maurya
  • Patent number: 9164927
    Abstract: A memory data protection apparatus including a storage device, a cipher, and a validator is provided. The storage device is embedded in a chip electrically coupled to an external memory for storing an offset value, a signature and a key. The cipher electrically coupled to the storage device and the external memory to receive the key includes an encrypter and a decrypter. The encrypter is capable of executing an encryption to output an encrypted data and an encrypted certified data. The decrypter is capable of executing a decryption to output a decrypted data. The validator electrically coupled to the storage device receives the signature, the offset value and the certified data and determines an access limit of the external memory by validating the certified data with the signature and the offset value. The memory data protection apparatus accesses an original data in the external memory according to the access limit.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: October 20, 2015
    Assignee: Nuvoton Technology Corporation
    Inventor: Morgan Du
  • Patent number: 9146846
    Abstract: A memory implements a programmable physical address mapping that can change to reflect changing memory access patterns, observed or anticipated, to the memory. The memory employs address decode logic that can implement any of a variety of physical address mappings between physical addresses and corresponding memory locations. The physical address mappings may locate the data within one or more banks and rows of the memory so as to facilitate more efficient memory accesses for a given access pattern. The programmable physical address mapping employed by the hardware of the memory can include, but is not limited to, hardwired logic gates, programmable look-up tables or other mapping tables, reconfigurable logic, or combinations thereof. The physical address mapping may be programmed for the entire memory or on a per-memory region basis.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 29, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. Loh, Mauricio Breternitz, Jr.
  • Patent number: 9128924
    Abstract: Apparatus and method for direct data transfer in a wireless broadband system having an operating system, the apparatus including a central processing unit (CPU), at least one dedicated Direct Memory Access unit (DMA) local to the CPU, coupled directly to the CPU, and a commands FIFO (First In First Out) receiving commands from the CPU and automatically transferring the commands in sequence to the DMA for implementation by the DMA, in the absence of intervention by the operating system.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: September 8, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Meir Tsadik, Moshe Tanach, Assaf Touboul
  • Patent number: 9104557
    Abstract: Method and systems are disclosed for increasing the number of ranks supported in a memory system. In one embodiment, a plurality of predefined subsets of memory chips on a memory module is selected. A chip select signal uniquely identifying the selected subset of memory chips is generated. The chip select signal is encoded as a multi-bit word having a bit width that is less than the number of predefined subsets of memory chips. Each bit of the encoded chip select signal is transmitted along a separate chip select line. The transmitted chip select signal is decoded to determine the identity of the selected subset of memory chips. The selected subset of memory chips identified by the decoded chip select signal are read or written.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: August 11, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Jonathan Randall Hinkle, Justin Potok Bandholz
  • Patent number: 9092326
    Abstract: A process for creates a virtual address for a software entity called a “daughter” belonging to the context of a software entity called the “mother.” This virtual address includes a series of fields allowing retrieval of the series of fields of the virtual address of the mother software entity and a field unique in the context of the mother software entity. Each series of fields is associated with a single software entity which it defines completely.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: July 28, 2015
    Assignee: ALVEOL TECHNOLOGY SARL
    Inventor: Frédéric Jachiet
  • Patent number: 9081818
    Abstract: An example method includes (i) creating, by a first serial attached SCSI (SAS) switch, a first topology map describing a portion of a SAS fabric associated with the first SAS switch; (ii) receiving, at the first SAS switch and from a second SAS switch, a second topology map describing a portion of the SAS fabric associated with the second SAS switch; and (iii) merging, by the first SAS switch, the first topology map and the second topology map to produce a consolidated topology map of the SAS fabric.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: July 14, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Balaji Natrajan, Michael G Myrah, Pruthviraj Herur Puttaiah
  • Patent number: 9053347
    Abstract: A memory device includes: a storage unit that stores public key information of a certificate authority for verifying a certificate and includes a secret area storing data of which secrecy is assured; and a control unit that controls access to the storage unit depending on reception information, wherein the reception information includes information where access control information is added to certificate information authenticated by the certificate authority, and the control unit verifies the certificate using the public key, identifies the access control information, and limits the accessible secret area in the storage unit.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: June 9, 2015
    Assignee: SONY CORPORATION
    Inventors: Takamichi Hayashi, Hiroshi Kuno, Munetake Ebihara
  • Patent number: 9046931
    Abstract: Provided are an apparatus and method for adapting an input/output interface. According to the exemplary method, a host system adapts an input/output interface of the guestsystem a to an input/output unit capability of a host system so as to support a service supported by an input/output unit supporting the input/output unit capability of the guest system using the at least one input/output unit of the host system.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: June 2, 2015
    Assignees: Samsung Electronics Co., Ltd., Georgia Tech Research Corporation
    Inventors: Sang-bum Suh, Xiang Song, Kishore Ramachandran, Joo-young Hwang, Jung-hyun Yoo, Dushmanta Mohapatra
  • Publication number: 20150149660
    Abstract: A server and an identifier synchronization method are provided, and the server includes a network card, hardware peripherals and a basic input output system. The network card stores at least one identifier. The basic input output system starts operating to acquire the at least one identifier of the network card and write the at least one identifier into each hardware peripheral after the server is booted.
    Type: Application
    Filed: January 20, 2014
    Publication date: May 28, 2015
    Applicants: Inventec Corporation, Inventec (Pudong) Technology Corporation
    Inventors: Wei Huang, Quan-Yuan Chen
  • Patent number: 9043494
    Abstract: A method includes configuring a processing circuit to perform: receiving a control word for an I/O operation, forwarding a transport command control block (TCCB) from the channel subsystem to a control unit, gathering data associated with the I/O operation, and transmitting the gathered data to the control unit in the I/O processing system. Gathering the data includes accessing entries of a list of storage addresses that collectively specifying the data. Based on an entry of the list comprising a not-set first flag and a corresponding first storage address, gathering data from a corresponding storage location, and based on an entry of the list comprising a set first flag and a corresponding second storage address, obtaining a next entry of the list from a second storage location.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Daniel F. Casper, Mark P. Bendyk, John R. Flanagan, Catherine C. Huang, Matthew J. Kalos, Ugochukwu C. Njoku, Dale F. Riedy, Gustav E. Sittmann, III, Harry M. Yudenfriend
  • Patent number: 9043513
    Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: May 26, 2015
    Assignee: Rambus Inc.
    Inventors: Richard E. Perego, Pradeep Batra, Steven Woo, Lawrence Lai, Chi-Ming Yeung
  • Patent number: 9043495
    Abstract: Embodiments of the present invention relate to a method and an apparatus for obtaining equipment identification information, where the method includes: detecting, by using a first GPIO port, a first discharging duration for a capacitor to discharge through a resistor to be tested; detecting, by using a second GPIO port, a second discharging duration for the capacitor to discharge through a fixed value resistor; and obtaining a resistance of the resistor to be tested according to the first discharging duration, the second discharging duration, and a resistance of the fixed value resistor. The embodiments of the present invention are capable of increasing identification efficiency of the GPIO port.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: May 26, 2015
    Assignee: HUAWEI DEVICE CO., LTD.
    Inventor: Jianhui Jiang
  • Publication number: 20150134854
    Abstract: A method of providing one or more computing devices with access to a plurality of resources. The plurality of resources are provided by at least one physical device. The method comprises, at a first control element receiving a data packet transmitted by one of said one or more computing devices, and determining whether said data packet comprises a command including a first logical identifier identifying one of said resources. If it is determined that said data packet comprises a command including a first logical identifier a second logical identifier is obtained, the second logical identifier being associated with said first logical identifier and identifying said one of said resources. A request including said second logical identifier is transmitted to a second control element, the second control element being arranged to identify a physical device associated with said second logical identifier and to forward said request to the identified physical device.
    Type: Application
    Filed: January 23, 2015
    Publication date: May 14, 2015
    Inventor: Yves Constantin Tchapda