Abstract: This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided.

Abstract: One embodiment of the present invention sets forth a technique that allows multiple producers and/or consumers to access a first-in first-out sub-system (FIFO) using a “lock-free” mechanism. When two or more producers attempt to push data onto the FIFO simultaneously, only one of the producers succeeds. Similarly, when two or more consumers attempt to pop data from the FIFO simultaneously, only one of the consumers succeeds. However, each producer and consumer is provided with an indication of whether their respective access was successful. Unsuccessful accesses may be retried in the following clock cycle, so that simultaneous accesses are serialized.

Abstract: Embodiments of the present invention provide a buffer manager and a buffer management method based on an address pointer linked list. In the embodiments, address pointers of all buffer blocks in a buffer are divided into several groups, lower bits of address pointers in each group are used to record a linked list between the address pointers in the same group, and an address pointer which is pointed by one predetermined address pointer of each group and is in a different group is further recorded to upbuild a linked list between the groups. Thereby, an address linked list can still be stored without a RAM with a width equal to a pointer depth and with a depth equal to the total number of buffer blocks in the buffer as required by the conventional art, which greatly reduces hardware resources required.

Abstract: A method for sending buffer status information includes checking if a quality of service (QoS) parameter is defined for a first logical channel and at least one condition of the set of predetermined conditions associated with a logical channel group is fulfilled. If the QoS parameter is defined and at least one condition of the set is fulfilled, the method includes setting a number of bits in a media access control header according to a first semantic. The bits carry buffer status information, and the first semantic—is based on the QoS parameter of the first logical channel. Otherwise, the method includes setting the number of bits carrying the buffer status information according to a second semantic that is based on an amount of data available for transmission across the logical channel group.

Abstract: Disclosed is an electronic device featuring a multi buffer scheme for processing incoming signals. For example, two buffers can be used. A processor can read and process stored signals from a first buffer while an incoming data module can concurrently store signals in a second buffer. Once, the processor is done, it can move on to the second buffer and process signals stored therein while the incoming data module stores signals in the first buffer. Also provided is a flagging scheme for allowing the processor and the incoming data module to control their respective access to the various buffers, so that only one of them accesses a single buffer at any time.

Abstract: A messaging system and method which allows parallel execution of related requests according their context-based sequence. A serialization processor receives each incoming message request from a messaging client, extracts a transaction identifier (TI), searches a state table for the TI, and, if the TI is found active in the state table, stores the request in a serialization queue and makes an entry for that TI with the state “queued” in the state table. After execution of the active request, its entry in the state table is cleared, and the queued request with the same TI is executed, whereupon its entry is changed from queued to active.

Abstract: In an information processor system including a memory device (MEM0), a memory control device (SL0) capable of controlling an operation of the memory device, and a plurality of bus masters (MS0 to MS3) capable of giving access to the memory device through the memory control device, the memory control device includes a control circuit (SDCON) capable of giving a notice of information about a time that a data transfer from the memory device can be started to the bus master related to an access request. The bus master can cause the time information thus given to be a judgment factor as to whether an access request is given to the memory device or not. Consequently, each of the bus masters can avoid the generation of a useless access request and a data transfer to the masters to be accessed can be carried out smoothly.

Abstract: A method for operating a peripheral device includes receiving at the peripheral device service orders, which are identified with respective service instances and are submitted to the peripheral device over the bus by software applications running on a host processor, which write copies of the service orders to a memory. The received service orders are queued for execution by the peripheral device. When one or more of the service orders have been dropped from the queue prior to execution, a recovery of a selected service instance is initiated by submitting a read request from the peripheral device to the memory over the bus to receive a copy of any unexecuted service order associated with the service instance.

Abstract: Various embodiments include fault tolerant memory apparatus, methods, and systems, including a memory manager for supplying read and write requests to a memory device having a plurality of addressable memory locations. The memory manager includes a plurality of banks. Each bank includes a bank queue for storing read and write requests. The memory manager also includes a request arbiter connected to the plurality of banks. The request arbiter removes read and write requests from the bank queues for presentation to the memory device. The request arbiter includes a read phase of operation and a write phase of operation, wherein the request arbiter preferentially selects read requests for servicing during the read phase of operation and preferentially selects write requests for servicing during the write phase of operation.

Abstract: A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash.

Abstract: Systems and techniques include, in some implementations, a computer implemented method storing a portion of data elements present in a first buffer in a second buffer in response to detecting an overflow condition of the first buffer, wherein the data elements in the first buffer are sorted according to a predetermined order, and inserting a proxy data element in the first buffer to represent the portion of data elements stored to the second buffer.

Abstract: An load balanced interconnect between a master device and slave devices, having a buffer coupling the master to the slave devices, and queuing access requests from the master to respective ones of the slaves. A load condition of the buffer is detected, a bypass buffer coupling the master to one or more of the slave devices is established, and access requests are moved from the buffer to the bypass buffer to change the load condition. Optionally a condition of slave devices is detected, and optionally the condition of the slave devices is changed by moving or reordering access requests in and among the buffer and the bypass buffer.

Abstract: A method and system is disclosed for selecting a work queue associated with a processor within a multiple processor architecture to assign a new task. A local and a remote queue availability flag is maintained to indicate a relative size of work queues, in relationship to a mean queue size, for each processor in a multiple processor architecture. In determining to which processor to assign a task, the processor evaluates its own queue size by examining its local queue availability flag and evaluates other processor's queue sizes by examining their remote queue availability flags. The local queue availability flags are maintained asynchronously from task assignment. Remote flags are maintained at time of task assignment. The presented algorithm provides improved local processor queue size determinations in systems where task distribution processes execute with lower priorities that other tasks.

Abstract: A method and apparatus for processing data by a pipeline of a virtual multiple instance extended finite state machine (VMI EFSM). An input token is selected to enter the pipeline. The input token includes a reference to an EFSM instance, an extended command, and an operation code. The EFSM instance requires the resource to be available to generate an output token from the input token. In response to receiving an indication that the resource is unavailable, the input token is sent to a wait room or an initiative token containing the reference and the operation code is sent to a wait queue, and the output token is not generated. Without stalling and restarting the pipeline, another input token is processed in the pipeline while the resource is unavailable and while the input token is in the wait room or the initiative token is in the wait queue.

Abstract: A queue descriptor including a head pointer pointing to the first element in a queue and a tail pointer pointing to the last element in the queue is stored in memory. In response to a command to perform an enqueue or dequeue operation with respect to the queue, fetching from the memory to a cache only one of either the head pointer or tail pointer and returning to the memory from the cache portions of the queue descriptor modified by the operation.

Abstract: A system and method for providing a memory region/memory window (MR/MW) access notification on a system area network are provided. Whenever a previously allocated MR/MW is accessed, such as via a remote direct memory access (RDMA) read/write operation, a notification of the access is generated and written to a queue data structure associated with the MR/MW. In one illustrative embodiment, this queue data structure may be a MR/MW event queue (EQ) data structure that is created and used for all consumer processes and all MR/MWs. In other illustrative embodiments, the EQ is associated with a protection domain. In yet another illustrative embodiment, an event record may be posted to an asynchronous event handler in response to the accessing of the MR/MW. In another illustrative embodiment, a previously posted queue element may be used to generate a completion queue element in response to the accessing of the MR/MW.

Abstract: A network device includes a main storage memory and a queue handling component. The main storage memory includes multiple memory banks which store a plurality of packets for multiple output queues. The queue handling component controls write operations to the multiple memory banks and controls read operations from the multiple memory banks, where the read operations for at least one of the multiple output queues alternates sequentially between the each of the multiple memory banks, and where the read operations and the write operations occur during a same clock period on different ones of the multiple memory banks.

Abstract: Disclosed is a computer implemented method, computer program product, and apparatus to enqueue one or more packets in a device driver for an I/O adapter. A device driver receives, by a processor executing the device driver, a reference to a list of transmit packets. The device driver may then atomically fetch and set a transmit active flag, wherein atomically setting comprises determining a former status of the transmit active flag. Responsive to a determination that a former status of the transmit active flag is different than a current status of the transmit active flag, the device driver atomically removes, by a processor executing the device driver, any packets referenced by a host machine transmit queue reference. The device driver pre-pends transmit packets referenced by the host machine transmit queue reference to the list of transmit packets to form an augmented list of transmit packets. The device driver builds a work request based on the augmented list of transmit packets.

Abstract: Provided is a serial control device that makes the length of data transferred as one frame variable. The serial control device transfers serial data having an arbitrary length, and uses end information indicating inclusion or non-inclusion of end data of the serial data. The serial control device transfers data having a transfer unit length in the serial data when the end information indicates non-inclusion of the end data, and transfers an untransferred part of the serial data when the end information indicates inclusion of the end data.

Abstract: A system selectively drops data from queues. The system includes a drop table that stores drop probabilities. The system selects one of the queues to examine and generates an index into the drop table to identify one of the drop probabilities for the examined queue. The system then determines whether to drop data from the examined queue based on the identified drop probability.

Abstract: Some of the embodiments of the present disclosure provide a method comprising managing a plurality of buffer addresses in a system-on-chip (SOC); and if a number of available buffer addresses in the SOC falls below a low threshold value, obtaining one or more buffer addresses from a memory, which is external to the SOC, to the SOC. Other embodiments are also described and claimed.

Abstract: A tape drive, tape drive recording system, and method are provided for improving tape speed selection during data transfer. The tape drive comprises a buffer, a tape for recording the data to be temporarily stored in the buffer, and a read head. The tape drive further comprises a reading controller that initially sets a tape speed such that a drive transfer rate matches a host transfer rate as closely as possible and that drives the tape at the tape speed. To address backhitching caused by one or more host transfer halts, the reading controller subsequently adjusts the tape speed such that the drive transfer rate is lower than the host transfer rate by recalculating the host transfer rate in consideration of the host transfer and the host transfer halt and setting the tape speed such that the drive transfer rate matches the recalculated host transfer rate as closely as possible.

Abstract: A computer implemented method for writing to a software bound ring buffer. A network adapter may determine that data is available to write to the software bound ring buffer. The network adapter determines that a read index is not equal to a write index, responsive to a determination that data is available to write to the software bound ring buffer. The network adapter writes the data to memory referenced by the hardware write index, wherein memory referenced by the write index is offset according to an offset, and the memory contents comprise a data portion and a valid bit. The network adapter writes an epoch value of the write index to the valid bit. The network adapter increments the write index, responsive to writing the data to memory referenced by the write index. Further disclosed is method to access a hardware bound ring buffer.

Abstract: An MFP which holds resources stores resource information about the held resources. Whether or not a resource holding request has been added to a resource downloading request from an SFP is discriminated. If a resource holding request has been added, a holding priority to decide a holding state of the held resources is set. The holding state of the held resources is controlled based on the holding priority.

Abstract: Performing data management operations on replicated data in a computer network. Log entries are generated for data management operations of an application executing on a source system. Consistency point entries are used to indicate a time of a known good, or recoverable, state of the application. A destination system is configured to process a copy of the log and consistency point entries to replicate data in a replication volume, the replicated data being a copy of the application data on the source system. When the replicated data represents a known good state of the application, as determined by the consistency point entries, the destination system(s) may perform a storage operation (e.g., snapshot, backup) to copy the replicated data and to logically associate the copied data with a time information (e.g., time stamp) indicative of the source system time when the application was in the known good state.

Abstract: A buffer management method operates by receiving a read command, wherein the read command comprises a read destination address for designating an associated area of a storage media; receiving write commands, wherein each of the write command comprises a data block and a write destination address for designating an associated location of the storage media to store the data block; buffering the data blocks of the write commands in a buffer; generating a latest list, wherein the latest list comprises a plurality of buffer indexes indicating buffer areas for storing the data blocks associated with the latest certain amount of received write commands; and determining whether the read destination address of the read command is associate with the latest list.

Abstract: A network device may include an off-chip memory to store a free-list of buffer pointers. The network device may further include an on-chip controller that includes a prefetch buffer. The prefetch buffer may store unallocated buffer pointers that point to available memory locations in a different off-chip memory. The on-chip controller may receive an unallocated buffer pointer, determine, in response to receiving the unallocated buffer pointer, whether the prefetch buffer is full, store the unallocated buffer pointer in the prefetch buffer when the prefetch buffer is determined not to be full, and store the unallocated buffer pointer in the free-list, in the off-chip memory, when the prefetch buffer is determined to be full.

Abstract: An ordered storage structure implemented based on a content addressable memory (CAM). In an embodiment, a set of identifiers are formed with an order matching a desired access order for items. Each item is stored with a corresponding identifier in an entry of the CAM, with the identifiers being stored in the searchable fields/columns of the CAM. Thus, the items can be retrieved in the desired access order by providing the identifiers as search key inputs to the CAM in the desired access order.

Abstract: A method for exchanging message data in a distributed computer system between a sending and a receiving hardware system. The sending hardware system includes a first memory system and a receiving hardware system which includes a second memory system with a second data buffer and a second memory region. The sending hardware system and the receiving hardware system are coupled via a non-transparent bridge unit. The method includes allocating empty memory, writing information about the empty memory, copying payload data directly from the sending hardware system to the empty memory locations, and writing information about the copied payload data to the second data buffer of the second memory system inside the receiving hardware system. A system and computer program product for carrying out the method are also provided.

Abstract: One or more computer-readable media that enable a method of recording object configurations at and after an incident occurs in the object. The present invention captures object configurations surrounding an incident that allows changes to be made in response to the incident to be analyzed. The present invention also may generate an incident classification based on a comparison of the configuration when the incident occurs and after it is resolved.

Abstract: Provided is a serial control device that makes the length of data transferred as one frame variable. The serial control device transfers serial data having an arbitrary length, and uses end information indicating inclusion or non-inclusion of end data of the serial data. The serial control device transfers data having a transfer unit length in the serial data when the end information indicates non-inclusion of the end data, and transfers an untransferred part of the serial data when the end information indicates inclusion of the end data.

Abstract: An audio system communicates with an aggregate device that includes multiple audio devices. When providing audio data for playback, the system compensates for presentation latency differences between the various audio devices. In addition, the system adjusts for device clock drift by selecting a master device and resampling the audio data provided to the other devices based on the difference between the device clock of the master device and the device clocks of the other devices.

Abstract: Embodiments of the present invention are directed to computationally efficient methods and systems for managing connection-associated and exchange-associated resources within network proxies. In one embodiment of the present invention, a circular connection-switch queue is employed for allocating, de-allocating, and maintaining connection-based or exchange-based data resources within a proxy. The connection-switch queue includes a free pointer that identifies a next connection-switch queue entry for allocation, and an idle pointer that is incremented continuously or at fixed intervals as timers associated with connection-switch entries expire. In an alternate embodiment, the connection-switch queue includes a free pointer, an idle pointer, and a clear pointer.

Abstract: Method and system for efficient buffer management for layer 2 through layer 5 network interface controller applications are provided. Aspects of the method may comprise determining whether an active NIC connection is an L2 type, an L4 type, or an L5 type. At least one buffer descriptor may be cached locally on a network interface controller (NIC) managed by a NIC application. The buffer descriptor is associated with the determined type of the active NIC connection. If the at least one active NIC connection is of the L2 or L4 type, the buffer descriptor may comprise at least one of a receive (RX) buffer descriptor and a transmit (TX) buffer descriptor. If the NIC connection is of the L5 type, the buffer descriptor may comprise at least one of a upper translation page table (TPT) entry and a lower TPT entry.

Abstract: A data processor includes a single-token-record memory, a sequence circuit, and a memory controller. The single-token-record memory has a plurality of first storage locations. The sequencer circuit is coupled to the single-token-record memory. The sequencer circuit, responsive to a request to place a token in a tail-end of a queue, either stores said token into one of the plurality of first storage locations if the single-token-record memory stores no greater than a predetermined number of tokens associated with the tail-end of the queue, or stores the token with at least one additional token and a pointer to a next storage location into one of a plurality of second storage locations otherwise. The memory controller is coupled to the sequencer circuit to store the token with the at least one additional token and the pointer in a location of a multi-token-record memory having the plurality of second storage locations.

Abstract: Disclosed is a technique for flow control. It is detected that a work request is being transferred to an in-memory structure. A maximum limit is compared with a number of work requests stored in the in-memory structure. If the number of work requests stored in the in-memory structure equals the maximum limit, a notification is sent that indicates that additional work requests are not to be sent.

Abstract: The exemplary embodiment of the present invention provides a storage buffer management scheme for I/O store buffers. Specifically, the storage buffer management system as described within the exemplary embodiment of the present invention is configured to comprise storage buffers that have the capability to efficiently support 128 byte or 256 byte I/O data transmission lines. The presently implemented storage buffer management scheme enables for a limited number of store buffers to be associated with a fixed number of storage state machines (i.e., queue positions) and thereafter the allowing for the matched pairs to be allocated in order to achieve maximum store throughput for varying combinations of store sizes of 128 and 256 bytes.

Abstract: In a pipelined computer architecture in which instructions may be removed from the instruction queue out of sequence, instruction queue status at a cycle K is determined by adding together the number of invalid instructions or free rows in the queue during cycle K?2, the number of instructions issued for cycle K?1 and the number of instructions speculatively issued in cycle K?1 that have produced a cache hit, and subtracting from the sum the number of instructions enqueued for cycle K?1. The result indicates the number of invalid instructions in the queue cycle K. The number of invalid entries instructions, the number of issued instructions, and the number of enqueued instructions are preferably represented as flat vectors, so that adding is performed by shifting in one direction, while subtracting is performed by shifting in the opposite direction. The result is compared with either the number of instructions to be enqueued in the present cycle, which number is encoded, or with a predetermined value.

Abstract: An A/D converter that is attached to a programmable controller (PLC) and sequentially converts an analog value inputted from outside into a digital value. The A/D converter includes: a shared memory that can read-access from a CPU unit that controls the entire PLC and includes a log storage area with a ring buffer configuration for sequentially logging the digital value and a parameter storage area for storing a head pointer serving as a parameter indicating a position where a next log data is stored; and a logging executing unit that writes a digital value in an address indicated by the head pointer in the log storage area as log data and updates the head pointer.

Abstract: A method for issuing shadow requests to manage bandwidth allocation between an application that issues input/output (I/O) operation requests and an I/O device. A bandwidth manager detects the completion of an I/O operation, which includes either a read operation or a write operation. The bandwidth manager calculates a statistical duration for future I/O operations between the application and the I/O device based on throughput statistics related to past I/O operations. The bandwidth manager generates a shadow request for reserving a position in a queue that stores pending I/O requests for the I/O device for a first future I/O operation request from the application and having a duration related to the statistical duration, and inserts the shadow request into the queue. Advantageously, applications that do not make frequent I/O operation requests in advance may still execute I/O operations because bandwidth is reserved for future I/O operation requests via the shadow requests.

Abstract: A low-latency queue pair (QP) is provided for I/O Adapters that eliminates the overhead associated with work queue elements (WQEs) and defines the mechanisms necessary to allow the placement of the message directly on the queue pair.

Abstract: An information processor (program processing unit 1) for managing a data sequence in a fixed order comprises a direction array (reference data storage section 2) for storing a reference to each data item of the data sequence in an element of the index associated with the key to the data, and means (CPU 3) for changing all data keys referenced by elements within an arbitrary range of indexes in the direction array by the same amount, where memory contents within the range of the direction array are shifted by the number of indexes corresponding to the changed amount.

Abstract: A data acquisition service on a network node is disclosed for forwarding received process data to a process history database over a potentially slow and/or intermittent network connection. A store and forward functionality within the networked node receives incoming process data via a first network interface and forwards outgoing process data via a second network interface. The disclosed store and forward functionality includes an immediate transmission cache and a store and forward storage. The store control enters, in response to detecting an entry condition, an activated mode wherein incoming process data is directed to the store and forward storage. A read control forwards outgoing process data to the second network interface from the immediate transmission cache and store and forward storage. The read control includes at least a first configurable parameter that constrains a rate at which data retrieved from the store and forward storage is forwarded via the second network interface.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: An audio system communicates with an aggregate device that includes multiple audio devices. When providing audio data for playback, the system compensates for presentation latency differences between the various audio devices. In addition, the system adjusts for device clock drift by selecting a master device and resampling the audio data provided to the other devices based on the difference between the device clock of the master device and the device clocks of the other devices.

Abstract: Embodiments of the invention describe arbitrating requests received from a plurality of agents for memory. Each memory request may indicate a priority level of the memory request and a size of the memory to be accessed. Said requests may be stored in a queue. Arbitration logic, coupled to the plurality of agents and the queue, may receive said memory requests and determine which requests to send to the queue based, at least in part, on the priority of each request and the size of the memory to be accessed by each memory request.

Abstract: In a real-time collaboration server, a control unit manages a collaboration mode. The control unit operates a virtual client that maintains a virtual screen reflecting the status of the collaboration (e.g., the contents of a shared desktop or whiteboard). The virtual client renders collaboration data within the virtual screen. New clients are synchronized with an ongoing collaboration by packing and sending them a copy of the virtual screen. The control unit maintains a queue of collaboration data to be sent to participating clients. Each client may have a pointer identifying the queued data it is processing. The queue may be collapsed (e.g., when it reaches a maximum size) by sending a copy of the virtual screen to one or more clients that have not yet consumed old data in the queue; those clients are then updated to skip the queue entries embodied in the virtual screen.

Abstract: A method of verifying programming of an integrated circuit card includes transferring program data to a page buffer of a non-volatile memory, copying the program data to a buffer memory, calculating a first checksum value with respect to program data in the buffer memory, updating the program data in the buffer memory by copying the program data of the page buffer to the buffer memory, calculating a second checksum value with respect to updated program data in the buffer memory, comparing the first checksum value and the second checksum value, and determining, based on the comparison result, whether the program data of the page buffer is tampered.

Abstract: Interface circuitry that is used to interface data between two different clock regimes that may have somewhat different speeds includes the ability to determine which of the clock regimes is faster. Depending on which clock regime is found to be faster, the baseline (nominal difference between data write and data read addresses of a FIFO memory in the interface circuitry) is shifted (i.e., toward the full or empty condition of the FIFO, as is appropriate for which of the clock regimes has been found to be faster). Adjustments may also be made to the threshold(s) used for such purposes as character insertion/deletion and overflow/underflow indication. This technique may allow use of a smaller FIFO and reduce latency of the interface circuitry.

Abstract: Method and apparatus for processing data packets within a communication system such as a synchronous optical network (SONET) detect an invalid byte and drop and shift bytes of data to address an invalid byte. A method according to one embodiment of the present invention, includes receiving a first data packet in the communication system. Thereafter, it is determined whether this packet ends with both a valid byte and an invalid byte of data. If both the valid and invalid bytes are present, the invalid byte is dropped and a valid byte from a succeeding data packet is concatenated with the valid byte of the first data packet, and byte shifting occurs in the succeeding data packet. Byte shifting continues until a second packet ending with an invalid byte is encountered. Skipping a clock cycle at the end of the second packet with the invalid byte results in packets with only valid data.