Input/output Data Buffering Patents (Class 710/52)
  • Patent number: 10762008
    Abstract: A memory module includes a first memory device that includes first circuit nodes for communication with a memory controller and second circuit nodes for communication inside the memory module, a second memory device that includes first circuit nodes for communication with the memory controller and second circuit nodes for communication inside the memory module, and an internal data bus that couples the first memory device to the second memory device to carry data between the second circuit nodes of the first memory device and the second circuit nodes of the second memory device. When an internal read command is applied to the first memory device and an internal write command is applied to the second memory device, data is transferred from the first memory device to the second memory device through the internal data bus.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: September 1, 2020
    Assignee: SK hynix Inc.
    Inventors: Jung-Hyun Kwon, Do-Sun Hong, Won-Gyu Shin, Seung-Gyu Jeong
  • Patent number: 10756816
    Abstract: A storage controller includes a plurality of submission queues corresponding to an initiator device and a processing device, the processing device to receive a Fibre Channel Protocol (FCP) command from the initiator device and send the FCP command to a first submission queue of the plurality of submission queues, the first submission queue being reserved for use by a kernel space of the storage controller. The processing device further to receive a Non-Volatile Memory Express over Fibre Channel (NVMe/FC) command from the initiator device. The processing device further to send the NVMe/FC command to a second submission queue of the plurality of submission queues without routing the NVMe/FC command through the kernel space, the second submission queue being reserved for direct access by the initiator device to a user space of the storage controller.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: August 25, 2020
    Assignee: Pure Storage, Inc.
    Inventor: Roland Dreier
  • Patent number: 10747666
    Abstract: A memory system includes a non-volatile memory, a buffer memory, and a controller. The controller is configured to write data corresponding to a write command received from a host in the buffer memory, and based on an indication from the host, do not write the data stored in the buffer memory into the non-volatile memory unless a non-volatilization event occurs, the non-volatilization event being one of a flush request from the host and a detection of a power shutdown.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Masahiro Ishiyama
  • Patent number: 10740008
    Abstract: A data reading method includes receiving, by a controller of a memory, a read operation request carrying a first address; performing, by the controller, N read operations on the first address, and obtaining N pieces of data read by the N read operations; and determining, by the controller, whether the N pieces of data are consistent. The method further includes sending, by the controller, response information used to respond to the read operation request if the controller determines that the N pieces of data are consistent, where the response information includes any one of the N pieces of data. The controller may perform T random read operations between any two consecutive read operations of the N read operations to avoid data leakage during reading. If the N pieces of data obtained by performing the N read operations are inconsistent, the memory may send abnormal alarm information to respond to the read operation request to avoid data tampering.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 11, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mingguang Wang, Yu Liu, Jie Chen
  • Patent number: 10725916
    Abstract: A system includes sensors, a first memory component, a second memory component, and an interface. The sensors are configured to generate data responsive to stimuli. Each sensor may transmit its associated data as it becomes available. The first memory component may receive and store sensor data. The second memory component may receive data from the first memory component. The interface may receive data from the second memory component. The sensor data generated during a time which the interface is receiving data from the second memory component is transmitted to the first memory component and stored thereto. No data is transmitted from the first memory component or from the sensors to the second memory component during the time which the interface is receiving data from the second memory component. Subsequently, a subset of data stored on the first memory component is advanced to the second memory component.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: July 28, 2020
    Assignee: InvenSense, Inc.
    Inventors: Vinod Bhat, Amr Zaky, Jatin Gangani
  • Patent number: 10725704
    Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: July 28, 2020
    Assignee: Rambus Inc.
    Inventors: Michael L. Takefman, Maher Amer, Riccardo Badalone
  • Patent number: 10728304
    Abstract: Systems and methods are described to enable synchronized encoding of streaming audio or video content between multiple encoders, in a manner that provides for redundancy of the system to vary based on a demand for the output content. End user devices or content distribution systems can monitor how content is output on end user devices, and report such output to a content encoding system. The encoding system can then redundancy provided for streaming content based on the demand by end users. Streams that are in high demand can be processed with high redundancy among devices that provide seamlessly interchangeable content, thus reducing the likelihood of perceived failure for such streams. Streams that are in low demand can be processed with low redundancy, reducing the computing resources used to process the stream while minimizing the overall impact of a processing failure, should one occur.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: July 28, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Jason LaPier, Aslam Khader
  • Patent number: 10720780
    Abstract: A battery authentication system includes a battery pack, and a host device connected to the battery pack to charge the battery pack. The battery pack includes a battery, a discharge switch that turns on and off discharging of the battery, a charge switch that turns on and off charging of the battery, and a control integrated circuit (IC) that controls the battery. The control IC includes a charge/discharge control circuit that controls the discharge switch and the charge switch, and an authentication circuit that performs a process for performing an authentication with the host device. The authentication circuit is configured to perform a process associated with a first authentication. The charge/discharge control circuit is configured to control the discharge switch to be turned on when the first authentication is established. The authentication circuit is configured to perform a process associated with a second authentication.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masayoshi Okawa, Hiromasa Takahashi
  • Patent number: 10713083
    Abstract: A method includes using a network interface controller to monitor a transmit ring, wherein the transmit ring comprises a circular ring data structure that stores descriptors, wherein a descriptor describes data and comprises a guest bus address that provides a virtual memory location of the data. The method also includes using the network interface controller to determine that a descriptor has been written to the transmit ring. The method further includes using the network interface controller to attempt to retrieve a translation for the guest bus address. The method includes using the network interface controller to read the descriptor from the transmit ring.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: July 14, 2020
    Assignee: Altera Corporation
    Inventor: Kenneth Vincent Bridgers
  • Patent number: 10712967
    Abstract: A method includes identifying, by a processing entity of a computing device, data units to read from non-volatile memory and to write into ordered buffers of volatile memory. The method further includes generating, by the processing entity, read operations regarding the data units, wherein the number of read operations equals ā€œnā€. The method further includes tagging, by the processing entity, each read operation of the read operations with a unique ordered tag value. The method further includes receiving, by the processing entity, read responses to the read operations from the non-volatile memory. The method further includes writing, by the processing entity, data units contained in the read responses into the ordered buffers in accordance with the ordered tag values. The method further includes tracking, by the processing entity, consumption of the data units from the ordered buffers.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: July 14, 2020
    Assignee: Ocient Holdings LLC
    Inventors: George Kondiles, Jason Arnold
  • Patent number: 10691710
    Abstract: Various embodiments relate generally to data science and data analysis, and computer software and systems, to provide an interface between repositories of disparate datasets and computing machine-based entities that seek access to the datasets, and, more specifically, to a computing and data storage platform that facilitates consolidation of one or more datasets, whereby one or more interfaces, such as user interfaces, may be implemented as computerized tools for presenting summarization of dataset attributes to facilitate discovery, formation, and analysis of interrelated collaborative datasets. In some examples, a method may include presenting data representing summary characteristic data in a user interface. This may include user interface elements each specifying a value of a dataset attribute for a collaborative dataset. Also, the method may include presenting aggregated data attributes for a subset of the collaborative dataset associated with the linked atomized datasets.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: June 23, 2020
    Assignee: data.world, Inc.
    Inventors: Shad William Reynolds, David Lee Griffith, Jon Loyens, Bryon Kristen Jacob
  • Patent number: 10642513
    Abstract: A storage device may utilize de-centralized latch management to remove functions from the device controller to the memory die. NAND die located on a common bus may share a pool of latches with one die acting as a proxy or manager for the other die. A bridge or bridges may be used between NAND connections to allow additional die to be controlled by a leader die for the partially de-centralized management of latches. The latch management operations may include a sequence of commands/operations performed by the leader die.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: May 5, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Alon Marcu, Judah Gamliel Hahn, Gadi Vishne, Alex Bazarsky, Ariel Navon
  • Patent number: 10642860
    Abstract: An example method of live migration of distributed databases may include implementing a first intermediate database access mode with respect to a distributed database to be migrated from an original set of storage servers to a destination set of storage servers, wherein, in the first database access mode, database read requests are routed to the original set of storage servers and database update requests are routed to both the original set of storage servers and the destination set of storage servers. The method may further include copying a plurality of records of the distributed database from the original set of storage servers to the destination set of storage servers. The method may further include switching to a second intermediate database access mode, in which database read requests are routed to the destination set of storage servers and database update requests are routed to both the original set of storage servers and the destination set of storage servers.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: May 5, 2020
    Assignee: Electronic Arts Inc.
    Inventors: Greg William Schaefer, Anand Nair, Shengyong Li, MengXin Ye, Xin Feng Zhang, Miao Xiong, Jian Zhou
  • Patent number: 10628054
    Abstract: An apparatus may include a redundant array of independent disks (RAID) array including a plurality of solid state drives (SSDs). The apparatus may further include a RAID array controller coupled to the plurality of SSDs. The RAID array controller may be configured to determine whether one or more logical block addresses (LBAs) of a stripe of the RAID array are unmapped. The one or more LBAs may be associated with one or more SSDs of the plurality of SSDs. The RAID array controller may be configured to determine data corresponding to the stripe based on the determination of whether the one or more LBAs are unmapped. RAID operations (such has Rebuild, Exposed Mode Read, and/or Parity Resync operations) may be optimized based on the knowledge of which LBAs are mapped and unmapped.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Robert Galbraith, Andrew D. Walls
  • Patent number: 10609155
    Abstract: A method, system, and computer program product for scalable and self-healing architecture for client-server operations in transient connectivity conditions are provided in the illustrative embodiments. An application in a second system receives a request from a first system, the request requesting data from a type of service. A first response responds to the request. The request is queued in a service queue corresponding to the type of the service, to make the request available to a third system that provides the type of the service. A notification is received that a second response from the third data processing system has been posted into a session specific queue, the second response being responsive to the request. In response to another request received from the first system, a third response is sent to the first system, the third response including the data from the second response from the session specific queue.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: March 31, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kanak B. Agarwal, Patrick J. Bohrer, Ahmed Gheith, Michael D. Kistler, Ramakrishnan Rajamony, Brian L. White Eagle
  • Patent number: 10592117
    Abstract: According to one embodiment, a memory system is configured to operate as one of semiconductor storage devices in a storage array. The memory system includes a nonvolatile memory and a controller. The controller executes a write operation of writing data, received from a host, to the nonvolatile memory, and an internal operation for managing the memory system. When starting the internal operation, the controller estimates a value related to an amount of reduction in performance of the write operation due to the start of the internal operation, based on content of the started internal operation, and notifies the host or one or more other semiconductor storage devices of the estimated value.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • Patent number: 10585642
    Abstract: A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: March 10, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: XuHong Xiong, Pingping Shao, ZhongXiang Luo, ChenBin Wang
  • Patent number: 10579116
    Abstract: A system on a chip (SOC) and an integrated circuit device having the same are disclosed. The SOC has a chip controller and a first chip element which do not need to operate according to a reference clock signal, and the SOC has a second chip element which needs to operate according to the reference clock signal. During resetting of a main system processor, the chip controller of the SOC is reset simultaneously. After the chip controller finishes resetting, the first chip element is then reset. After the main system processor finishes resetting, the second chip element of the SOC starts to reset. Accordingly, during the resetting of the main system processor, the SOC is reset simultaneously, thereby reducing the boot time of the integrated circuit device.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: March 3, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: I-Hsun Huang, Cheng-Yu Chen, An-Ming Lee
  • Patent number: 10564886
    Abstract: Aspects of the disclosure provide for control of a flash translation layer (FTL) in a non-volatile memory (NVM). Disclosed methods and apparatus provide for receiving a message in the FTL, which is transmitted from a host device, and includes desired recycle ratio information that is determined by the host where the ratio is a number of host writes to a number of recycle writes to be performed by the FTL. Based on the recycle ratio information, the FTL determines a target recycle ratio and performs recycling of memory blocks in the NVM based on the determined target recycle ratio. In this manner, the host device is able to exert control over the recycle ratio utilized in the FTL via a transmitted message, which allows the recycle ratio to be more adaptive to host write conditions known to the host device, but not known in the SSD.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 18, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Saugata Das Purkayastha
  • Patent number: 10560374
    Abstract: Embodiments of the present disclosure describe systems, devices, and methods for traffic steering in mobile networks. Various embodiments may include a service steering and control function to route a service dataflow through one or more service enablers based on service steering and control rules. Other embodiments may be described or claimed.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: February 11, 2020
    Assignee: Apple Inc.
    Inventors: Changhong Shan, Muthaiah Venkatachalam, Puneet Jain, Alexandre S. Stojanovski
  • Patent number: 10546648
    Abstract: A storage control system, and a method of operation thereof, including: a recycle write queue for providing a recycle write; a host write queue for providing a host write; and a scheduler, coupled to the recycle write queue and the host write queue, for scheduling the recycle write and the host write for writing to a memory device.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: January 28, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James M. Higgins, James M. Kresse, Ryan Jones, Mark Dancho
  • Patent number: 10545669
    Abstract: A system comprises a plurality of computing devices that are communicatively coupled via a network and have a file system distributed among them, and comprises one or more file system request buffers residing on one or more of the plurality of computing devices. File system choking management circuitry that resides on one or more of the plurality of computing devices is operable to separately control: a first rate at which a first type of file system requests (e.g., one of data requests, data read requests, data write requests, metadata requests, metadata read requests, and metadata write requests) are fetched from the one or more buffers, and a second rate at which a second type of file system requests (e.g., another of data requests, data read requests, data write requests, metadata requests, metadata read requests, and metadata write requests) are fetched from the one or more buffers.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 28, 2020
    Assignee: Weka.IO Ltd.
    Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel, Kanael Arditti, Tomer Filiba
  • Patent number: 10534417
    Abstract: A rack computer system can provide data indicating electrical power consumption by separate sets of the mass storage devices, including separate individual mass storage devices, of the rack computer system. A power sensor can be electrically coupled to a power transmission line for each mass storage device. The power sensor can be coupled to the power transmission line externally to the mass storage device. The power sensor can be an internal power sensor of the mass storage device, where a mass storage device microcontroller transmits internally-generated data to an external power monitoring system. A microcontroller can transmit the data to a baseboard management controller via a side-band connection between the mass storage device and the controller. The data can be transmitted via an in-band connection between a baseboard management controller and an instance of firmware which accesses internally-generated data from mass storage device microcontrollers.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: January 14, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Felipe Enrique Ortega Gutierrez, Jason Alexander Harland, Roey Rivnay, David Edward Bryan, Christopher Strickland Beall
  • Patent number: 10531871
    Abstract: A method of anchoring a suture into a pilot hole in bone utilizing a suture anchor. A lumen-defining circular soft wall, having a first and second end, is slidably engaged to a piece of suture, a first length of which extends from the first end of the wall and is threaded through the lumen from the second end, and a second length of which extends from the second end and is threaded through the lumen from the first end. The suture anchor is introduced into the pilot hole so that the first length and second length of suture material extend out of the pilot hole. The first length and second length are pulled on alternately, thereby permitting the suture anchor structure to slide on the piece of suture material, and to be compacted evenly by the pulling, until the suture anchor is set in the pilot hole.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: January 14, 2020
    Assignee: RIVERPOINT MEDICAL, LLC
    Inventor: Patrick Edward Ferguson
  • Patent number: 10530511
    Abstract: Embodiments implement a device having a sensor element, where different data streams created as part of a sensor module integrated with the sensor element may create multiple sensor data streams from a single sensor element, and may concurrently convey information from the sensor element to respective different applications having different data parameter requirements such that the data streams each match the parameter requirements of the different applications.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: January 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Joseph Czompo
  • Patent number: 10530513
    Abstract: The present invention provides an asynchronous data multiplexing method and device. The method includes the following steps: acquiring status flag, serial number, and data information of each branch data; performing asynchronous data buffering processing on the data information of each branch data according to preset channel transmission bit-serial number to obtain buffered data of each branch; then determining each branch data according to the status flag, if the status flag is valid identification information, a flag bit corresponding to a frame header is set according to the valid identification information, and the buffered data of the current branch data is added to a corresponding position of the data part by bit; and if the status flag is invalid identification information, the flag bit corresponding to the frame header is kept unchanged.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: January 7, 2020
    Assignee: HANGZHOU YIYUQIANXIANG TECHNOLOGY CO., LTD.
    Inventor: Pingting Wei
  • Patent number: 10516621
    Abstract: Described embodiments provide for minimizing packet discarding in case of spiky traffic reception by using adaptive buffers. Transmission buffers may be adjusted based on traffic behavior, with the buffer size dynamically expanding or shrinking as needed, providing a cushion to hold extra packets when a buffer drain rate is slower than the buffer arrival rate.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 24, 2019
    Assignee: CITRIX SYSTEMS, INC.
    Inventors: Ramanjaneyulu Talla, Anshul Kumar, Narendra Kataria
  • Patent number: 10514849
    Abstract: A storage system includes a plurality of nodes, each of the nodes including a processor and a nonvolatile storage device, and a connection unit directly connected to at least one of the nodes and configured to issue commands directed to a target node. The processor of the target node is configured to access the nonvolatile storage device of the target node in accordance with a command received from the connection unit, notify completion of processing for the command to the connection unit when a processing result responsive to the command is returned from the nonvolatile storage device of the target node within a reference time period, and notify a busy state of the target node to the connection unit when the processing result responsive to the command is not returned from the nonvolatile storage device of the target node within the reference time period.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: December 24, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Makoto Shimamura, Mototaka Kanematsu
  • Patent number: 10498780
    Abstract: Systems, methods, and non-transitory computer-readable media can send at least one request for streaming a content item. Data associated with at least one portion of the content item is streamed. A first rate at which the content item is encoded is determined. A second rate at which the content item is being streamed is determined. A need for adjusting the streaming of the content item is determined based at least in part on the first rate and the second rate. Streaming of the content item is adjusted. The adjustment causes the second rate at which the content item is being streamed to conform to the first rate.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: December 3, 2019
    Assignee: Facebook, Inc.
    Inventor: Maher Afif Saba
  • Patent number: 10489082
    Abstract: Systems and methods for using host command data buffers as extended memory device volatile memory are disclosed. NVM Express implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. Commands may include an indication of a host buffer, resident on the host device, in which to store data for access by the host device. The memory device may use the host buffer as extended memory during execution of the command. As one example, the memory device may process the command in stages, with each stage retrieving data from the host buffer, manipulating the data, and writing the processed data to the same host buffer. As another example, the host buffer can be used for memory device internal relocation and garbage collection operations. Thus, the area/cost of the memory device controller is reduced since less volatile memory is required.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: November 26, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Yoav Weinberg
  • Patent number: 10467407
    Abstract: Methods and systems provide for detecting exploitation of kernel vulnerabilities which typically corrupt memory. The methods and systems are implemented, for example, via a host, which includes a hypervisor, which controls the operating system (OS) user space and the OS kernel space.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: November 5, 2019
    Assignee: Check Point Advanced Threat Prevention Ltd.
    Inventors: Dani Frank, Yoav Alon, Aviv Gafni, Ben Omelchenko
  • Patent number: 10437731
    Abstract: In embodiments, apparatuses, methods and storage media associated with a multi-level cache are described. A first storage level may receive an input/output (I/O) request from a second storage level of the multi-level cache, wherein the I/O request is associated with a data. The first storage level may further receive an indicator to indicate whether the data is stored or will be stored in the second storage level. The first storage level may determine whether to store the data in the first storage level based on the indicator. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Slawomir Putyrski
  • Patent number: 10424043
    Abstract: Graphics processing systems and methods are described. A graphics processing apparatus may comprise one or more graphics processing cores, a shared buffer accessible to a user mode driver (UMD) associated with an application in an unprivileged domain, the UMD to write one or more commands to the shared buffer, and a controller parse a workload in the shared buffer to identify one or more commands in the workload, the workload added by the application executing in the unprivileged domain, associate a trigger with a command in the workload, transfer the workload to one or more components of the graphics processing apparatus for execution, and upon execution of the command associated with the trigger, sample the shared buffer to identify a new workload added to the shared buffer. The one or more components of the graphics processing apparatus automatically execute the new workload added to the shared buffer.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Joseph Koston, Ankur Shah, Murali Ramadoss, Jeffery Boles, Balaji Vembu
  • Patent number: 10405365
    Abstract: In one example, a method and apparatus for web browsing on multihomed mobile devices having multiple communication interfaces are disclosed. In one example, the method establishes a primary multiple path transmission control protocol subflow for the transfer of a resource from a server to a user endpoint device. The method then determines a threshold of resource size. When the size of the resource is determined to exceed the threshold, the method establishes a secondary multipath transmission control protocol connection that cooperates with the primary multiple path transmission control protocol subflow for the transfer of the resource from the server to the user endpoint device.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: September 3, 2019
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Bo Han, Rittwik Jana, Lusheng Ji, Feng Qian
  • Patent number: 10379899
    Abstract: A data processing system can comprise a first module having a workspace and configured to execute a task that can request access to a frame in a system memory, a queue manager configured to store a frame descriptor which identifies the frame in the system memory, and a memory access engine coupled to the first module and the queue manager. The memory access engine copies requested segments of the frame to the workspace and has a working frame unit to store a segment handle identifying a location and size of each requested segment copied to the workspace of the first module. The memory access engine tracks history of a requested segment by updating the working frame unit when the requested segment in the workspace is modified by the executing task.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: August 13, 2019
    Assignee: NXP USA, Inc.
    Inventors: John F. Pillar, Michael Kardonik, Bernard Marchand, Peter W. Newton, Mark A. Schellhorn
  • Patent number: 10372553
    Abstract: Performing parallel file restoration from a serialized storage device using a network data management protocol is presented herein. A system can comprise a reader, a parser component, and a set of writers. The reader can be configured to copy data from a tape drive to memory buffers as buffered data. The parser component can be configured to determine, within the buffered data, a location of a file header record representing a file that has been stored in the tape drive, and generate, based on the file header record, a header work item for facilitating restoration of the file in a file system. Further, the set of writers can be configured to create, based on the header work item using the buffered data, the file in the file system.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: August 6, 2019
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Hsing Yuan, Hymanand Nellore, Ilavarasu Pandian, Moiz Haidry, Abhijeet Kodgire
  • Patent number: 10365950
    Abstract: A method for providing resource throttling management. The method includes accessing a distributed computer system having a plurality of nodes, initiating a new object policy object backup protection for a new object, and implementing a discovery process to determine computer environment components subject to stress. The method further includes generating a physical resource throttling protocol in accordance with the components subject to stress, and processing the new object in accordance with the object management policy and in accordance with the throttling protocol.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 30, 2019
    Assignee: Veritas Technologies LLC
    Inventors: Mark Ambrose Ditto, James Robert Olson, Raymond Streckert
  • Patent number: 10360045
    Abstract: A device or apparatus may be configured to perform memory operations on a memory die while a current multi-level cell programming operation is being performed. In the event that a controller identifies pending memory operations to be performed in the memory die, the controller may communicate with the memory die to determine a status of auxiliary latches of the memory die. Depending on the status, the controller may determine if the memory die is in a suspend/resume period and/or which pending memory operations to have performed.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: July 23, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Uri Peltz, Amir Hadar, Mark Shlick, Mark Murin
  • Patent number: 10342026
    Abstract: The present invention relates to transmitting and receiving data in a wireless communication system employing time division duplex, and in particular to a rate matching for the channels which are mapped onto special subframes such as uplink/downlink switching subframes in TDD. Accordingly, at the transmitter, a data block is stored in a memory unit which is to be operated as a circular buffer, the data block is transmitted in a plurality of subframes including special subframes, a special subframe containing an uplink portion and a downlink portion separated from each other by a switching portion; and before the transmission a rate matching is performed by mapping the stored data block onto the plurality of subframes using the circular buffer, wherein the mapping of bits onto two different special subframes starts from different respective positions in the circular buffer. Moreover, a corresponding receiving apparatus and a transmitting and receiving method are provided.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: July 2, 2019
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Alexander Golitschek Edler von Elbwart, Chi Gao, Lilei Wang, Hidetoshi Suzuki
  • Patent number: 10341097
    Abstract: According to an embodiment, a communication device is connected with another communication device through a quantum communication channel with a shared encryption key. The device includes a communication unit, a sifter, a corrector, a calculator, and an extractor. The communication unit is configured to acquire a sequence of photons through the quantum communication channel and acquire a photon bit string corresponding to the sequence of photons. The sifter is configured to generate a shared bit string from the photon bit string by sifting processing using basis information. The corrector is configured to generate a corrected bit string by correcting an error included in the shared bit string. The calculator is configured to generate a hash-calculated bit string by performing hash calculation on the corrected bit string. The extractor is configured to extract, as the key, from the hash-calculated bit string, a bit string having the length of the key.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: July 2, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ririka Takahashi, Yoshimichi Tanizawa
  • Patent number: 10331555
    Abstract: Apparatus, systems, methods, and computer program products for dynamic memory compaction are disclosed. A memory device comprises a plurality of memory blocks and a controller for the memory device. A controller is configured to generate an input/output command to write a data chunk to a first memory block of a plurality of memory blocks. A controller is configured to compact an amount of valid data in a second memory block of a plurality of memory blocks based on a size of an I/O command.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: June 25, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy, Balaji Thraksha Venkataramanan
  • Patent number: 10303371
    Abstract: A storage device includes a nonvolatile memory, a communication interface connectable to an external device, and a control circuit. The control circuit is configured to carry out over an elapsed time period first write operations to write data received through the communication interface in the nonvolatile memory, second write operations to write data stored in a memory region of the nonvolatile memory to another memory region of the nonvolatile memory, and wait operations during which no data are written, read, or erased in the nonvolatile memory, such that the wait operations are carried out during a smaller percentage of the elapsed time period as the elapsed time period becomes longer.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: May 28, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takamasa Hirata
  • Patent number: 10306182
    Abstract: A user equipment (UE) and method of improving video call quality during handover are generally described. After determining that handover has started (306), the UE may suspend (308) frame transmission and store the frames. After determining that handover has completed (310), the UE may discard (312) frames whose age exceeds a predetermined percent of a latency deviation computed from a real-time transport control protocol report. The UE may determine whether transmission of the remaining frames would exceed a delay proportional to a video frame interval multiplied by an uplink bandwidth for a cell to which the UE is connected or a maximum bitrate of a guaranteed bitrate bearer multiplied by a typical period for a non-access stratum bandwidth and discard frames in order of decreasing age until neither the bitrate nor the delay is exceeded by the transmission.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventor: Eric Perraud
  • Patent number: 10298681
    Abstract: The disclosed computer-implemented method for rerouting data sent between application containers and storage containers may include (1) identifying an application container, a storage container that stores data for the application container, and a host that hosts both the application container and the storage container, (2) configuring the application container and the storage container to share a namespace on the host, (3) creating, within the shared namespace on the host, a resource that enables the application container and the storage container to share data, and (4) rerouting at least one item of data sent between the application container and the storage container to pass through the resource in the shared namespace rather than through a kernel of the host. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: May 21, 2019
    Assignee: Veritas Technologies LLC
    Inventors: Gaurav Makin, John Kjell, Kody Kantor, Bruce R. Montague
  • Patent number: 10298496
    Abstract: A data or packet processing device such as a network interface controller may include cache control logic that is configured to receive a first request for processing a first data packet associated with the queue identifier, and obtain a set of memory descriptors associated with the queue identifier from the memory. The set of descriptors can be stored in the cache. When a second request for processing a second data packet associated with the queue identifier is received, the cache control logic can determine that the cache is storing memory descriptors for processing the second data packet, and provide the memory descriptors used for processing the second packet.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: May 21, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Guy Nakibly, Benzi Denkberg, Erez Izenberg, Nafea Bshara, Uri Leder, Ofer Frishman
  • Patent number: 10291232
    Abstract: A counter includes: a computing module (100) and N counting modules (101). Each counting module includes a plurality of counting spaces corresponding to different counting entries, and counting spaces of the same counting entry in different counting modules have the same address, wherein the counting module is arranged to provide a value for computing to the computing module in response to a counting application of a counting application source. The computing module is arranged to read values of the same counting entry in different counting modules and accumulate the read values to obtain a total count value of the counting entry, N being an integer not less than 1. Also disclosed is a counting method.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: May 14, 2019
    Assignee: Sanechips Technology Co., Ltd.
    Inventor: Junjie Yin
  • Patent number: 10289333
    Abstract: An apparatus includes a non-volatile memory and a memory controller coupled to the non-volatile memory. The memory controller includes a processor configured to perform a first operation and a second operation and further includes an access device interface configured to communicate with a first device. The memory controller further includes a wireless interface configured to communicate with a second device to transfer data associated with the second operation to the second device to enable performance at the second device of one or more tasks of the second operation.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 14, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventor: Kapil Sundrani
  • Patent number: 10291839
    Abstract: An image capturing apparatus comprises an image capturing unit, a moving object detection unit, a depth information detection unit configured to detect a plurality of depth information corresponding to each of the plurality of detection regions, a storage control unit configured to store the plurality of depth information as map data in a storage unit. The depth information detection unit detects a second depth information in a second detection region including at least one of regions in which the moving object is detected, and the storage control unit updates only the second depth information detected by the depth information detection unit with respect to the map data stored in the storage unit.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: May 14, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Ayumi Kato
  • Patent number: 10284353
    Abstract: A method for subsurface radio communication includes transmitting voice data through a subsurface environment, by a transmitter of a radio transceiver. The voice data is received through the subsurface environment, by a receiver of the radio transceiver. A transceiver frequency of the radio transceiver is changed to an optimal transceiver frequency in response to a change to the subsurface environment. The transceiver frequency is one of a transmit frequency of the transmitter and a receive frequency of the receiver. A first impedance of a subwavelength antenna is matched to a second impedance of the transceiver in response to a difference between the first impedance and the second impedance exceeding an impedance mismatch value. The subwavelength antenna has a radiating length less than a transceiver wavelength of the radio transceiver operating in free-space at a maximum of the transceiver frequency.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 7, 2019
    Assignee: Sandia Research Corporation
    Inventors: Steven Michael Shope, Paul Raymond Jorgenson
  • Patent number: 10275777
    Abstract: Systems, computer program products, and methods are described herein for a centralized compliance assessment tool. The present invention is configured to deploy a compliance assessment application to be executed in parallel on one or more applications; initiate one or more retrieval scripts configured to cause the one or more applications to generate one or more digital artifacts to indicate a compliance of the one or more applications to one or more regulatory requirements; determine that the one or more applications are compliant with the one or more regulatory requirements based on at least the one or more digital artifacts generated; and initiate an execution of a regulatory report script based on at least determining that the one or more applications are compliant with the one or more regulatory requirement.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: April 30, 2019
    Assignee: Bank of America Corporation
    Inventors: Anthony Edward Copeland, Eileen Marie Daly, IV, Charlene W. Cook