Input/output Data Buffering Patents (Class 710/52)
  • Patent number: 9977813
    Abstract: As a method for migrating data of a volume adopting a snapshot function to a new storage system, in order to perform migration without depending on a method for compressing snapshot data of a migration source storage system, and without stopping transmission and reception of data between the host computer and the storage system, at first, after migrating data of a volume being the source of snapshot (PVOL), migration is performed sequentially from newer generations. At this time, migration target data of each SVOL is all the data within the migration source storage system. The SVOL data copied to a migration destination storage is compared with one-generation-newer SVOL data within the migration destination storage system, and based on the comparison result, a difference management information is created. If there is difference, a VOL allocation management table is updated, and difference data is stored in the area allocated within the pool.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 22, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Ryosuke Tatsumi, Tadato Nishina, Norio Shimozono
  • Patent number: 9929823
    Abstract: In a telecommunications network including at least a user device and a network node separated by at least a packet-switched part of the telecommunications network, the user device including a primary jitter buffer having a constant packet play-out rate, the network node including a secondary jitter buffer, incoming packets destined for the user device are received and passed through the secondary jitter buffer of the network node downstream towards the primary jitter buffer of the user device. The departure times of packets passing through the secondary jitter buffer of the network node downstream towards the primary jitter buffer of the user device are monitored. On the basis of the monitoring and one or more known characteristics of the primary jitter buffer, an estimate of a current state of the primary jitter buffer is maintained. Operation of the secondary jitter buffer is dynamically controlled according to the maintained estimate.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: March 27, 2018
    Assignee: METASWITCH NETWORKS LTD
    Inventor: Colin Tregenza Dancer
  • Patent number: 9921875
    Abstract: An application sends a first request to an operating system to provide a hardware device with direct memory access to contents of a virtual memory location in an application memory of the application, wherein the virtual memory location is mapped to a physical memory location. In response to determining that the virtual memory location is to be reclaimed, the application sends a second request to the operating system to unmap the physical memory location from the virtual memory location. The second request causes the virtual memory location to be mapped to a new physical memory location. Responsive to receiving an indication from the operating system that the request to unmap the physical memory location has completed, the application then accesses the new physical memory location mapped to the virtual memory location.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: March 20, 2018
    Assignee: Red Hat Israel, Ltd.
    Inventor: Michael Tsirkin
  • Patent number: 9921925
    Abstract: The present invention discloses a method and an apparatus for recovering abnormal data in an internal memory. The method includes: receiving, by a processor, a data abort signal and an address of an abnormal instruction where abnormal data is located; suspending a current instruction being executed, and recording an address pointed to by a computer pointer; obtaining a program unit currently being executed by the processor; if it is determined that the abnormal instruction belongs to the program unit and that instructions between the first instruction and the current instruction in the program unit are all reversible instructions, invoking a destruction program unit corresponding to the program unit, so as to release resources already applied for by the program unit; and causing the computer pointer to point back to an address of the first instruction in the program unit, and re-executing the program unit.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: March 20, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Weifeng Hui, Xiaogang Zhu
  • Patent number: 9905277
    Abstract: A memory system comprises a memory controller and a memory device having one or more memory ranks and multiple memory electrically connected to the one or more memory ranks. The memory controller includes at least one analysis module and at least one switching determination module. The analysis module analyzes states of multiple memory control commands corresponding to a particular memory rank to generate a control parameter. The switching determination module determines whether at least one switching command is sent according to the control parameter, a current operation mode of the particular memory rank, and an operation state of the particular memory rank. When the memory device receives a first switching command of the at least one command, the particular rank and at least one part of the memory internal circuits are switched from the normal voltage operation mode to the low voltage operation mode.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: February 27, 2018
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Pei-Wen Luo, Hsiu-Chuan Shih, Chi-Kang Chen, Ding-Ming Kwai, Cheng-Wen Wu
  • Patent number: 9893990
    Abstract: A network interface controller can include a sideband port controller. The sideband port controller can provide a sideband connection between the network and a sideband endpoint circuit that can be operative to communicate with the network via a sideband. The sideband port controller can include an event notification unit operative to compile information into an event notification packet. The sideband port controller can further include a packet parser. In embodiments, the packet parser could be operative to analyzes a packet to provide an indication that the packet contains the event notification packet. In embodiments, the sideband port controller could be operative to forward the information in the event notification packet to the sideband endpoint circuit, responsive to that indication.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Francois Abel, Claude Basso, Philippe Damon, Fabrice J. Verplanken
  • Patent number: 9886207
    Abstract: A controller and a memory-access method for use in the controller are provided. The controller includes a sensor-processing system, and the sensor-processing system includes a memory, and a buffer, wherein the controller is coupled to an external memory and a sensor. The method includes the steps of: gathering the sensor data from the sensor and writing the gathered sensor data into the memory; writing information associated with the sensor data into the buffer; determining whether a fill level of the buffer has reached a predetermined threshold; and retrieving the sensor data from the memory and writing the retrieved sensor data to the external memory according to the information associated with the stored sensor data in the buffer when it is determined that the fill level has reached the predetermined threshold.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: February 6, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chih-Hsiang Hsiao, Yun-Ching Li
  • Patent number: 9875053
    Abstract: A device includes a schedule engine including a mode selection input. The schedule engine has an operating mode based on the mode selection input. The operating mode includes an opportunistic scheduling mode based on the mode selection input having a first value and a pipelined scheduling mode based on the mode selection input having a second value. The device further includes a buffer coupled to the schedule engine.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: January 23, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Marina Frid, Igor Genshaft, Einat Inna Zevulun, Yacov Duzly, Amir Shaharabany
  • Patent number: 9875182
    Abstract: Systems and methods for writing data are provided. A lock-free container and methods of writing to the lock-free container are disclosed. The container is associated with a tail pointer that identifies free space in the container. Threads writing to the container access the tail pointer and update an offset in the tail pointer to account for a size of a write to the container. Multiple threads can write to the same container without having to contend for a container lock.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: January 23, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Grant R. Wallace, Philip N. Shilane
  • Patent number: 9870318
    Abstract: A system and method for efficiently relocating and initializing a block of memory of the computer system. For data initialization and data relocation, multiple registers in a processor are used for intermediate storage of data to be written into the memory. Regardless of whether the amount of data to initialize or relocate is aligned with the register data size, the processor writes the data into the destination buffer with write operations that only utilize the register data size. The write operations utilize the register data size when each of the start and the end of the destination buffer is aligned with the register width, when the start of the destination buffer is unaligned with the register width, when a source buffer and the destination buffer are unaligned with one another for a copy operation, and when the source buffer and the destination buffer overlap.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: January 16, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Jeremy P. Goodwin
  • Patent number: 9857981
    Abstract: A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has not started up, the first and second buffer sets operate in a cache memory mode to respond to read requests that the CPU repeatedly issues for data of specific addresses of the storage device. When the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the CPU issues for data of sequential addresses of the storage device.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: January 2, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Lin Li, Yunxing Dong, Zhiqiang Hui
  • Patent number: 9851899
    Abstract: A nonvolatile memory device includes a multi-level cell which stores M-bit data at a time and M number of latches for respectively storing M-bit data on a single bit basis. A controller sequentially latches M-bit data of the multi-level cell into the M number of latches, respectively, during a first half read period, and sequentially outputs the latched M-bit data in the M number of latches during a second half read period.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 26, 2017
    Assignee: SK Hynix Inc.
    Inventor: Byoung-Sung You
  • Patent number: 9836391
    Abstract: Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: December 5, 2017
    Assignee: Conversant Intellectual Property Management Inc.
    Inventors: Hong Beom Pyeon, Jin-Ki Kim, HakJune Oh
  • Patent number: 9838346
    Abstract: A computer-implemented method, system, and computer-readable media are disclosed herein. In embodiments, the computer-implemented method may entail receiving, by a data service, live data associated with an entity. The entity may be, for example, a customer of the data service. The method may then route the live data to a dual-queue system of the data service. The live data may be loaded into a live data queue of the dual queue system for processing. Processing may entail generating summary statistics from the live data. An alert may then be transmitted to the customer in response to detecting the occurrence of one or more alert events. In embodiments, the alert events may include events identified in the summary statistics. Additional embodiments are described and/or claimed.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: December 5, 2017
    Assignee: SPLUNK INC.
    Inventors: Ioannis Vlachogiannis, Panagiotis Papadomitsos
  • Patent number: 9817575
    Abstract: A host interface controller with improved boot up efficiency, which uses a buffer mode setting register to set the operation mode of a first and a second buffer set provided within the host interface controller. When a cache memory of a central processing unit (CPU) at the host side has not started up, the first and second buffer sets operate in a cache memory mode to respond to read requests that the CPU repeatedly issues for data of specific addresses of the storage device. When the cache memory has started up, the first buffer set and the second buffer set operate in a ping-pong buffer mode to respond to read requests that the CPU issues for data of sequential addresses of the storage device.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: November 14, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Lin Li, Yunxing Dong, Zhiqiang Hui
  • Patent number: 9785211
    Abstract: The feature size of semiconductor devices continues to decrease in each new generation. Smaller channel lengths lead to increased leakage currents. To reduce leakage current, some power domains within a device may be powered off (e.g., power collapsed) during periods of inactivity. However, when power is returned to the collapsed domains, circuitry in other power domains may experience significant processing overhead associated with reconfiguring communication channels to the newly powered domains. Provided in the present disclosure are exemplary techniques for isolating power domains to promote flexible power collapse while better managing the processing overhead associated with reestablishing data connections.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: October 10, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher Edward Koob, Xufeng Chen, Robert Allan Lester, Manojkumar Pyla, Peixin Zhong
  • Patent number: 9778859
    Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: October 3, 2017
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dejan Vucinic, Zvonimir Z. Bandic, Cyril Guyot, Robert Mateescu, Qingbo Wang
  • Patent number: 9778998
    Abstract: Embodiments of the present invention disclose a data restoration method, including: after a transaction is submitted, saving a generated transaction log to a buffer of a current node, and backing up the transaction log to a buffer of at least one backup node except the current node; writing the transaction log saved in the buffer of the current node or the transaction log backed up in the buffer of the backup node into a transaction log file in a disk, where the transaction log file in the disk is used for restoring data of the current node; and restoring, based on the transaction log file in the disk, lost data of the current node when a data loss event occurs in the current node. By means of the present invention, a risk of system data can be reduced, and durability, safety, and reliability of the system data can be improved.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: October 3, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jijun Wen, Yuanyuan Nie, Wentao Xu
  • Patent number: 9772946
    Abstract: A method and device are provided for processing data. The method includes, after receiving data input by a data bus, according to a destination indication of the data and a valid bit field indication of the data, writing the data input by the data bus into an uplink side shared cache, polling the uplink side shared cache according to a fixed timeslot order, reading out the data in the uplink side shared cache, and outputting the data to respective corresponding channels. The method and device enable effective saving of cache resources, reduction of pressure on area and timing, and improvement of cache utilization while reliably achieving data cache and bit width conversion.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: September 26, 2017
    Assignee: ZTE Corporation
    Inventor: Xinzhuo Shi
  • Patent number: 9762682
    Abstract: An information handling system (IHS) comprising a chassis, a motherboard disposed within the chassis, a management controller (MC) coupled to the motherboard and a network attached storage (NAS) coupled to the MC wherein the MC provides access to the NAS. An IHS may further include and input/output (I/O) module (IOM) disposed within the chassis, at least one blade and a keyboard video mouse (KVM) module, wherein the NAS is directly accessible to the IOM blade(s) and KVM module.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: September 12, 2017
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Brian L. Reuter
  • Patent number: 9754675
    Abstract: A memory system may include a command storage unit for storing maximum N commands received from a host, K memory devices each for storing maximum M commands based on the maximum N commands and performing each set operation in response to the stored maximum M commands in order of input, and a resetting unit for resetting execution sequences of the maximum N commands based on execution information regarding each of the maximum N commands and the maximum M commands in each of the K memory devices whenever the commands received from the host are stored in the command storage unit, and distributing the N commands to the K memory devices. The execution information includes a logical address, a physical address, a length, and a use time of a corresponding command.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: September 5, 2017
    Assignee: SK Hynix Inc.
    Inventor: Jong-Ju Park
  • Patent number: 9734099
    Abstract: System and method of using a processor driven master Quad-SPI (QSPI) bus or interface to simultaneously and time-synchronously transmit different streams of data from a FIFO buffer to a plurality of different slave SPI interface peripherals. Here the QSPI interface data ports are configured to simultaneously transmit multiple 1 bit wide streams of different binary data and different chip select commands on an SPI clock cycle synchronized basis. Additional SPI slave peripherals may be controlled by use of additional non-SPI clock synchronized GPIO chip select commands and suitable logic gates. These methods are useful for creating a variety of embedded systems with faster response speeds, such as improved microwave frequency synthesizers with faster frequency changing times.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: August 15, 2017
    Assignee: Micro Lambda Wireless, Inc.
    Inventor: Shlomo Argoetti
  • Patent number: 9705808
    Abstract: Systems and methods are provided that enable flow aware buffer management. The method includes storing in a queue of a buffer a first type of traffic, storing in the queue of the buffer a second type of traffic, wherein the first type of traffic is less sensitive to latency than the second type of traffic, and when an amount of the first type of traffic meets or exceeds a first threshold, effecting flow control of the first type of traffic to slow a flow of the first type of traffic into the buffer. Flow control can be effected using packet marking or discarding packets. The methodology has particular utility in connection with managing elephant and mouse flows in a network switch.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: July 11, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: Subbarao Arumilli, Peter Newman
  • Patent number: 9680509
    Abstract: Embodiments are generally directed to errors and erasures decoding from multiple memory devices. An apparatus may include logic to store a portion of an error correction codeword in each of multiple memory devices, and logic to decode errors and erasures for the memory devices. The decoding of the errors and erasures includes reading the portions of the error correction codeword from a subset of the memory devices to generate a partial codeword, with the subset excluding at least one of the memory devices. The decoding of the errors and erasures further includes decoding errors and erasures of the plurality of memory devices based at least in part on the partial codeword if the errors and erasures can be decoded from the partial codeword, and, upon determining that the errors and erasures cannot be decoded from the partial codeword, then reading the one or more portions of the error correction codeword from the memory devices excluded from the first subset to generate a complete codeword.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventor: Zion S. Kwok
  • Patent number: 9666270
    Abstract: A nonvolatile memory device includes a multi-level cell which stores M-bit data at a time and M number of latches for respectively storing M-bit data on a single bit basis. A controller sequentially latches M-bit data of the multi-level cell into the M number of latches, respectively, during a first half read period, and sequentially outputs the latched M-bit data in the M number of latches during a second half read period.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: May 30, 2017
    Assignee: SK Hynix Inc.
    Inventor: Byoung-Sung You
  • Patent number: 9639324
    Abstract: A system including an encoder module, a buffer first-in first-out (FIFO) module, a buffer manager module, N FIFO modules, and N input/output (I/O) modules. The encoder module encodes data received from a host and generates P units of encoded data, where P is an integer greater than 1. The buffer FIFO module receives the P units from the encoder module and outputs the P units. The buffer manager module receives the P units from the buffer FIFO module, stores the P units in a buffer, retrieves N of the P units from the buffer, and outputs the N units in parallel, where N is an integer greater than 1. The N FIFO modules respectively receive the N units in parallel directly from the buffer manager. The N I/O modules receive the N units from the N FIFO modules in parallel, respectively, and output the N units to a storage medium.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: May 2, 2017
    Assignee: Marvell World Trade LTD.
    Inventors: Tony Yoon, Siu-Hung Fred Au
  • Patent number: 9632965
    Abstract: Ethernet physical sublayer (PHY) devices each provide PHY register data. One or more of the Ethernet PHY devices are connected to each of one or more management data input/output (MDIO)/management data clock (MDC) interfaces to which a number of MDIO/MDC controllers are connected. Each MDIO/MDC controller polls a corresponding MDIO/MDC interface to receive the PHY register data from the one or more Ethernet PHY devices connected thereto. The MDIO/MDC controllers store portions of the PHY register data received from the Ethernet PHY devices to a memory to which an interface is connected. A processor connected to the interface accesses the portions of the PHY register data stored to the memory. The processor can retrieve the portions of the PHY register data over the interface more quickly than the MDIO/MDC controllers can retrieve the PHY register data over the MDIO/MDC interfaces.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: April 25, 2017
    Assignee: Lenovo Enterprise Solutions (Singapore) PTE. LTD.
    Inventor: Anthony E. Baker
  • Patent number: 9632938
    Abstract: A method and an apparatus for pushing memory data from a memory to a push destination storage used to store data prefetched by a central processing unit (CPU) in a computing system are disclosed. In the method, a memory controller of the computing system periodically generates a push command according to a push period. Then the memory controller acquires a push parameter of to-be-pushed data according to the push command and sends at least one memory access request to memory according to the push parameter, where the at least one memory access request is used to request the to-be-pushed data from the memory. After receiving the to-be-pushed data that is sent according to the at least one memory access request by the memory, the memory controller buffers the to-be-pushed data and pushes the to-be-pushed data from the data buffer to the push destination storage.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: April 25, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mingyang Chen, Mingyu Chen, Zehan Cui, Licheng Chen
  • Patent number: 9614732
    Abstract: Profile generation for bandwidth management is provided. A content provider receive a notification regarding a new application or media file. Profile information for the application or media file is determined. Such profile information includes information regarding consumption of bandwidth throughout a time period of usage of the application or media file. The profile may be stored in memory in association with the application or media file. A request is received from a user device regarding access to the application or media file. Access to the requested application or media is provided to the user device; the profile is also provided to the user device for use in evaluating whether bandwidth requirements of the application or media file exceeds an available network bandwidth of a network of the user device.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 4, 2017
    Assignee: SONY INTERACTIVE ENTERTAINMENT INC.
    Inventor: Gregory Corson
  • Patent number: 9606918
    Abstract: Systems and methods for improving caching mechanisms in a storage system are disclosed. The method includes storing data associated with a write input/output (I/O) request at a cache; determining an amount of dirty data stored in the cache, where the dirty data is data in the cache that has not yet been written to a persistent storage location managed by a storage system; determining if the amount of dirty data exceeds a threshold value; determining a cache flush rate based on the amount of dirty data stored at the cache, when the amount of dirty data exceeds the threshold value; and writing data from the cache at the determined cache flush rate to the persistent storage location.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: March 28, 2017
    Assignee: NetApp Inc.
    Inventors: Randolph Wesley Sterns, Mark Edward Regester, Kevin Lee Kidney, Yulu Diao
  • Patent number: 9606887
    Abstract: Embodiments provide a data persisting mechanism that allows for efficient, unobtrusive persisting of large volumes of data while optimizing the use of system resources by the persisting process. In an embodiment, the persisting process includes a self-tuning algorithm that constantly monitors persistence performance and that adjusts persistence time to maintain performance within user-defined criteria. From one aspect, this allows the persisting process to seamlessly adapt to changes in system environment (speeding up persistence during times of low processor usage and slowing down persistence during times of high processor usage) and to reduce or eliminate CPU spikes caused by persisting process. From another aspect, the persisting process results in the data being persisted as quickly as possible given the system constraints, thereby minimizing the possibility of data loss.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: March 28, 2017
    Assignee: RIVERBED TECHNOLOGY, INC.
    Inventors: Joseph D. Mokos, Edward W. Macomber
  • Patent number: 9594395
    Abstract: Techniques are disclosed relating to clock routing techniques in processors with both pipelined and non-pipelined circuitry. In some embodiments, an apparatus includes execution units that are non-pipelined and configured to perform instructions without receiving a clock signal. In these embodiments, one or more clock lines routed throughout the apparatus do not extend into the one or more execution units in each pipeline, reducing the length of the clock lines. In some embodiments, the apparatus includes multiple such pipelines arranged in an array, with the execution units located on an outer portion of the array and clocked control circuitry located on an inner portion of the array. In some embodiments, clock lines do not extend into the outer portion of the array. In some embodiments, the array includes one or more rows of execution units. These arrangements may further reduce the length of clock lines.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: March 14, 2017
    Assignee: Apple Inc.
    Inventors: Andrew M. Havlir, James S. Blomgren, Terence M. Potter
  • Patent number: 9588690
    Abstract: A computer determines an intrinsic read speed and an intrinsic write speed associated with a first disk and a second disk. The computer receives a request to read a portion of data, wherein the portion of data is stored redundantly on both the first and second disk. The computer identifies a first latency associated with reading the portion of data from the first disk, where the first latency is based on at least the intrinsic read speed and the intrinsic write speed associated with the first disk. The computer identifies a second latency associated with reading the portion of data form the second disk, wherein the second latency is based on at least the intrinsic read speed and the intrinsic write speed associated with the second disk. The computer determines that the first latency exceeds the second latency. The computer selects the second disk to read the portion of data.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: March 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Mudi M. Fluman, Yaacov Frank, Yehuda Shiran, Ronny Vatelmacher
  • Patent number: 9582211
    Abstract: A method of operation in a non-volatile memory system for deferring, in accordance with a determination to reduce power consumption by the non-volatile memory system, execution of commands in a command queue corresponding to a distinct set of non-volatile memory devices during a respective wait period. In some implementations, the respective wait period for a first distinct set of non-volatile memory devices in at least two distinct sets is at least partially non-overlapping with the respective wait period for a second distinct set of non-volatile memory devices in the at least two distinct sets.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: February 28, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Robert W. Ellis, James M. Higgins, Mark Dancho
  • Patent number: 9575677
    Abstract: The various embodiments described herein include methods and/or systems for throttling power in a storage device. In one aspect, a method of operation in a storage system includes obtaining a power metric corresponding to a count of active memory commands in the storage system, where active memory commands are commands being executed by the storage system. The method further includes, in accordance with a determination that the power metric satisfies one or more power thresholds, deferring execution of one or more pending memory commands.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: February 21, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Robert W. Ellis, James M Higgins, Mark Dancho, Ryan R. Jones
  • Patent number: 9547472
    Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: January 17, 2017
    Assignee: HGST Netherlands B.V.
    Inventors: Dejan Vucinic, Cyril Guyot, Robert Mateescu, Qingbo Wang, Zvonimir Z. Bandic, Frank R. Chu
  • Patent number: 9548941
    Abstract: Data flow node validation and provisioning techniques are described. In one or more implementations, a system is described that supports visual design and deployment of data flow pipelines to process streaming data flows. The system may be configured to include nodes and connections between the nodes to represent an arbitrary execution graph of data science algorithms (as algorithm action components) that are used to process the streaming data flows. The system may also support validation techniques to verify that the data flow pipeline may operate as intended. Further, the system may also support implementation and provisioning techniques that involve estimation and adjustment of runtime resource provisioning of a deployed data flow pipeline without preemption or starvation occurring for nodes within the pipeline.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: January 17, 2017
    Assignee: Adobe Systems Incorporated
    Inventor: David M. Tompkins
  • Patent number: 9542330
    Abstract: Storage tracks from at least one host are destaged from the write cache rank when it is determined that the at least one host is idle with respect to a first set of ranks, and storage tracks are refrained from being destaged from each rank when it is determined that the at least one host is not idle with respect to a second set of ranks.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent C. Beardsley, Michael T. Benhase, Binny S. Gill, Lokesh M. Gupta, Sonny E. Williams
  • Patent number: 9535870
    Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: January 3, 2017
    Assignee: HGST Netherlands B.V.
    Inventors: Dejan Vucinic, Cyril Guyot, Robert Mateescu
  • Patent number: 9529667
    Abstract: A method in a memory device implementing error correction includes setting an error correction event register to a first value; accessing a memory location in the first memory array in response to a memory address; retrieving stored memory data from the accessed memory location in the first memory array and retrieving error correction check bits corresponding to the accessed memory location from the second memory array; checking the retrieved memory data for bit errors using the retrieved check bits; in response to a bit error being detected in the retrieved memory data, generating corrected memory data using the retrieved check bits and asserting an error correction event signal; and in response to the error correction event signal being asserted, setting the error correction event register to a second value.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: December 27, 2016
    Assignee: Integrated Silicon Solution, Inc.
    Inventor: Lyn R. Zastrow
  • Patent number: 9529745
    Abstract: A system on chip, SoC, comprising two or more data sources, a memory unit, a memory control unit, and a processing unit. Each of the data sources is capable of providing a data stream. The memory control unit is arranged to maintain, for each of the data streams, a buffer in the memory unit and to route the respective data stream to the processing unit via the respective buffer. Each of the buffers has buffer characteristics which are variable and which comprise at least the amount of free memory of the respective buffer. The memory control unit is arranged to allocate and de-allocate memory regions to and from each of the buffers in dependence of the buffer characteristics of the respective buffer, thereby allowing for re-allocation of memory of the memory unit among the buffers. A method of operating a system on chip is also described.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: December 27, 2016
    Assignee: NXP USA, INC.
    Inventors: Nir Atzmon, Ron-Michael Bar, Eran Glickman, Benny Michalovich
  • Patent number: 9519540
    Abstract: An apparatus, system, and method are disclosed for satisfying storage requests while destaging cached data. A monitor module samples a destage rate for a nonvolatile solid-state cache, a total cache write rate for the cache, and a dirtied data rate. The dirtied data rate comprises a rate at which write operations increase an amount of dirty data in the cache. A target module determines a target cache write rate for the cache based on the destage rate, the total cache write rate, and the dirtied data rate to target a destage write ratio. The destage write ratio comprises a predetermined ratio between the dirtied data rate and the destage rate. A rate enforcement module enforces the target cache write rate such that the total cache write rate satisfies the target cache write rate.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: December 13, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: David Atkisson, Jonathan Ludwig
  • Patent number: 9497018
    Abstract: A jitter occurring due to a difference in operation timing between a receiving part and a processing part is reduced. The receiving part receives reception data. The processing part processes the reception data and generates transmission data. A transmitting part transmits the transmission data at a timing at which a transmission delay time has passed since a timing at which the processing part generates the transmission data. The transmission delay time is a time obtained by subtracting a process delay time from an overall delay time. The process delay time is a time that passes since a timing at which the receiving part receives the reception data until a timing at which the processing part processes the reception data.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: November 15, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasuomi Ando
  • Patent number: 9489173
    Abstract: A computing device with a queue stored in a memory of the computing device is described. The queue may be relocated and/or resized in the memory using a queue address, a queue size, a head pointer, and/or a tail pointer associated with the queue. During operation, a processor, at the request of a software entity, updates one or more values associated with the queue to relocate and/or resize the queue. In response, a write mechanism performs one or more operations to enable the use of the relocated and/or resized queue. In addition, when the queue is relocated, the processor, at the request of the software entity, performs one or more operations to process remaining valid entries in an original location of the queue.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: November 8, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Andrew G. Kegel
  • Patent number: 9488691
    Abstract: An integrated circuit comprises: a first processing stage comprising processing logic for performing a processing operation on an input signal to generate an output signal, wherein the input signal corresponds to an output signal of a previous processing stage; a first sampling element adapted to sample a first value of said output signal synchronously with a clock signal; a second sampling element adapted to sample a second value of said output signal synchronously with a first delayed clock signal; and a first delayed clock signal generator, adapted to selectively generate said first delayed clock signal in response to a control signal generated in said previous processing stage.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: November 8, 2016
    Assignee: NXP B.V.
    Inventors: Juan Echeverri Escobar, Surendra Guntur, Manvi Agarwal, Rinze Ida Mechtildis Peter Meijer
  • Patent number: 9477620
    Abstract: A storage device of a storage system includes a device Direct Memory Access (DMA) configured to calculate a data transfer amount based on size information of data provided to a DMA queue; a command manager configured to receive the data transfer amount from the device DMA and to calculate a transfer speed using a speed mode table; and a device interface configured to transfer the transfer speed to a host.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: October 25, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Min Kim, Sangyoon Oh, HyunSoo Cho, Jeong Hur
  • Patent number: 9467307
    Abstract: In PCI-Express and alike communications systems, it is often desirable to keep track of order of arrival into different queues of packets that will later compete for servicing by a downstream resource of limited bandwidth. Use of time stamping to determine order of arrival can be a problem because time of arrival between different packets entering respective ones of plural queues can vary greatly and thus the number of bits consumed for accurately time stamping each packet can become significant. Disclosed are systems and methods for tracking the arrival orders of packets into plural queues by means of travel-along dynamic counts rather than by means of high precision time stamps.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: October 11, 2016
    Assignee: Microsemi Storage Solutions (US), Inc.
    Inventor: Robert Divivier
  • Patent number: 9465745
    Abstract: Apparatus and associated method concerning managing access commands with a main storage space, a volatile buffer, and a nonvolatile buffer. The volatile buffer is configured to store a plurality of command nodes that are associated with data access commands received from a remote device and directed to the main storage space. The apparatus also has command prioritizing logic configured for using a prescribed rule in repeatedly identifying two or more candidate command nodes of the plurality that are at least individually favored for execution with respect to the main storage space, for selecting one of the candidate command nodes for the execution, and for transferring a nonselected one of the candidate command nodes from the volatile buffer to the nonvolatile buffer where the nonselected command node continues to be considered for execution with respect to the main storage space but is no longer considered by the prescribed rule when identifying subsequent candidate command nodes in the volatile buffer.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: October 11, 2016
    Assignee: Seagate Technology, LLC
    Inventor: Satish Laxmanrao Rege
  • Patent number: 9467389
    Abstract: A switch unit has one frame buffer pool for storing received frames and another frame buffer pool for storing large frames. The frame size in the large frame buffer pool may be optimized to the largest amount of data the switch unit that an FCoE switching is running on can support (i.e., a limitation of zone entries). Should free space be unavailable in the large frame buffer pool, or if a sequence grows bigger than can be supported, the switch unit may still continue to send response frames back to the sender. While the switch unit may store header information of the frame, the switch unit does not store the data of subsequent frames any longer. Once the sequence has been received completely, a rejection message is sent back with an appropriate error or reason code. The rejection message enables the sender to attempt a retransmission or cancel the current request altogether.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: October 11, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christoph Raisch, Stefan Roscher, Alexander Schmidt, Daniel Sentler
  • Patent number: 9459829
    Abstract: Systems and methods are provided for a first-in-first-out buffer. A buffer includes a first sub-buffer configured to store data received from a buffer input, and a second sub-buffer. The second sub-buffer is configured to store data received from either the buffer input or the first sub-buffer and to output data to a buffer output in a same order as that data is received at the buffer input. Buffer control logic is configured to selectively route data from the buffer input or the first sub-buffer to the second sub-buffer so that data received at the buffer input is available to be output from the second sub-buffer in a first-in-first-out manner.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: October 4, 2016
    Assignee: MARVELL ISRAEL (M.I.S.L) LTD.
    Inventors: Evgeny Shumsky, Jonathan Kushnir