Abstract: A first fingerprint corresponding to a first chunk associated with a stream of data is generated. It is determined that the first fingerprint matches a second fingerprint of a plurality of fingerprints listed in at least one entry in a deduplication map associated with a plurality of storage systems. A first storage system of the plurality of storage systems is located at a first geographic location and a second storage system of the plurality of storage systems is located at a second geographic location. The first chunk corresponding to the second fingerprint is stored by at least the second storage system. In response to a determination that the first fingerprint matches the second fingerprint, it is determined to store at the first storage system a local copy of the first chunk based in part on one or more deduplication factors.

Abstract: According to one embodiment, a memory system includes a buffer, a nonvolatile memory and a controller. The buffer is capable of storing packets up to a first upper limit number. The controller generates a packet related to access to the nonvolatile memory and stores the packet in the buffer. The controller classifies the packets into packets of a first type and packets of a second type. The number of packets of the second type allowed to be stored in the buffer is limited to a second upper limit number smaller than the first upper limit number. When the number of packets of the second type stored in the buffer is the second upper limit number or larger, the controller does not generate a second packet of the second type or does not store the second packet in the buffer.

Abstract: A memory interface for interfacing between a memory bus and a cache memory. A plurality of bus interfaces are configured to transfer data between the memory bus and the cache memory, and a plurality of snoop processors are configured to receive snoop requests from the memory bus. Each snoop processor is associated with a respective bus interface and each snoop processor is configured, on receiving a snoop request, to determine whether the snoop request relates to the bus interface associated with that snoop processor and to process the snoop request in dependence on that determination.

Abstract: A technique for copying data from a source range to a destination range includes identifying a chunk of the source range. The chunk includes multiple logical blocks that map, through a series of source-mapping pages, to a set of virtual pages that point to physical data of the chunk. The technique further includes copying the series of source-mapping pages to form a corresponding series of destination-mapping pages pointed to by the destination range, so that a corresponding chunk of the destination range maps, via the series of destination-mapping pages, to the same set of virtual pages mapped to by the series of source mapping pages.

Abstract: Technology is disclosed for QoS (Quality of Service) enforcement with reduced contention. For commands where the QoS wait queue is empty and the QoS credit count is sufficient, an atomic operation subtracts the credits required to process the command from the QoS credit count without locking, and the command is processed. For other commands, credit generation is attempted by first reading a lock flag without obtaining a lock. If the lock flag is clear, an atomic operation sets it, and credit generation is performed if sufficient time has passed since a last credit generation. Credit generation stores a sum of the current QoS credit count and the number of newly generated credits into a local credit count, and processes commands in the QoS wait queue for which sufficient credits exist in the local credit count. When credit generation completes, the local credit count is stored into the QoS credit count.

Abstract: A method of training a physical interface between a first device and a second device includes performing a first training of the physical interface by communicating with the second device by using a first candidate group of lanes from among a plurality of lanes; performing a second training of the physical interface by communicating with the second device by using a second candidate group of lanes from among the plurality of lanes, the second candidate group being different from the first candidate group; determining a lane group based on a result of the first training and a result of the second training; and setting the second device so that the determined lane group is used for the physical interface.

Abstract: A data reduction device, a data reduction method, and a system including the data reduction device are provided. The data reduction device includes a control module configured to generate a control signal in response to a first kernel request received from an external entity, a direct memory access (DMA) engine configured to read request data corresponding to the first kernel request from an external entity in response to the control signal, and a data reduction core configured in such a manner that the request data is reduced through a first operation to be generated first reduction data or the first reduction data is reduced through a second operation to be generated as second reduction data.

Abstract: A method and system are provided for limiting unnecessary data traffic on the data communication connections connecting various system components, including the various levels of system memory. Some embodiments may include processing a buffer allotment request and/or a buffer release command in coordination with a system or network operation requiring temporary storage of data in a memory buffer. The buffer allotment request may be capable of indicating the amount of storage space required on the memory buffer to execute the system or network operation. The system may be capable of precluding the system or network operation from executing until there is sufficient space in the memory buffer to complete the operation without evicting operational data from the memory buffer. In some embodiments, the buffer release command may signal completion of the system or network operation and release of the utilized memory buffer space for other operations.

Abstract: Machine vision devices may be configured to automatically connect to a remote management server (e.g., a “cloud”-based management server), and may offload and/or communicate images and analyses to the remote management server via wired or wireless communications. The machine vision devices may further communicate with the management server, user computing devices, and/or human machine interface devices, e.g., to provide remote access to the machine vision device, provide real-time information from the machine vision device, receive configurations/updates, provide interactive graphical user interfaces, and/or the like.

Abstract: A sensor system can include a sensor configured to output raw sensor data, a plurality of processing modules configured to process the raw sensor data from the sensor to output processed sensor data, a state module for each processing module operative to cause a respective processing module to receive and/or process the sensor data, and a control module configured to receive a coded bitstring and activate or deactivate a predefined set of state modules based on the coded bitstring to control which processing modules process the sensor data and/or an order of processing. The coded bitstring can include a plurality of discrete bits less than the amount of processing modules and/or state modules. A plurality of the state modules and/or processing modules can be associated with at least one discrete bit of the plurality of discrete bits such that each coded bitstring corresponds to a predetermined group of state modules and/or processing modules.

Abstract: Systems and methods for managing interrupts generated by network interface controllers. An example method may comprise: responsive to determining that a memory pressure metric in a computer system does not exceed a threshold value, disabling interrupts that signal completion of a packet transmission by a network interface controller; transmitting a plurality of data packets by the network interface controller; and responsive to detecting that the memory pressure metric exceeds the threshold value, releasing a memory buffer allocated to a data packet of the plurality of data packets.

Abstract: A computer system having a host coupled to a storage device via a peripheral component interconnect express bus. The host communicates write commands of low priority to the storage device, which places them in a queue for execution at an idle time. In response to a determination that the storage device is in an idle state, the storage device best accommodates the write commands in the idle queue in connection with housekeeping tasks, such as garbage collection and wear leveling, to best reduce write amplification.

Abstract: Disclosed are systems and methods for accelerating commands from accelerators in data storage devices using accelerator queues. A data storage device includes accelerator interfaces, each accelerator interface couples a controller to a respective accelerator. The device also includes a device memory comprising one or more memories and one or more sets of queues. Each set of queues corresponds to a respective memory, at least one queue is configured to queue one or more tasks associated with an accelerator, and each queue is associated with a respective priority level of a plurality of priority levels. A controller is configured to: receive an accelerator command, identify a first memory corresponding to a task for the accelerator command; and enqueue the task to a first queue corresponding to the first memory, the first queue configured to queue one or more tasks associated with the first accelerator corresponding to the first accelerator interface.

Abstract: A device that is connected to a conference receives broadcast messages from other devices. The device selects at least a subset of the broadcast messages. Each broadcast message in the subset includes an indication that a respective device transmitting the broadcast message is connected to the conference. The device extracts respective audio synchronization values from the broadcast messages in the subset. The device identifies, based on the respective audio synchronization values, an audio frame of an audio stream of the conference. The device then outputs the audio frame.

Abstract: A data store system may include a storage device configured to store a plurality of data store tables and may include a processor in communication with the storage device. The processor may receive a plurality of requests. For each request, the processor may: (1) determine an associated workload type for the request; (2) determine a first respective rate at which the request is to be released for scheduling of execution; and (3) release the request for scheduling of execution based on the first respective rate. For each released request, the processor may: (1) determine a second respective rate based on the associated workload type at which each released request is scheduled to be executed; and (2) in response to execution being scheduled for a released request, execute the released request. A method and computer-readable medium are also disclosed.

Abstract: A device may include a buffer memory to buffer frames received or to be transmitted via a plurality of ports of the device. The device may include at least one frame processor to process frames. The device may include a buffer manager to store a frame in the buffer memory. The buffer manager may allocate at least one buffer control block (BCB) to the frame based on storing the frame in the buffer memory. The buffer manager may allocate a frame control block (FCB) to the frame. The FCB may include information that identifies the at least one BCB. The buffer manager may perform one or more queueing operations in association with processing of the frame by the at least one frame processor. The one or more queuing operations may be performed using information associated with the FCB.

Abstract: A memory system according to the present technology may include a plurality of memory devices including a plurality of blocks configured of memory cells and a memory controller configured to control the plurality of memory devices corresponding to a plurality of zones by configuring the plurality of zones with the plurality of blocks included in each of the plurality of memory devices, wherein the memory controller is further configured to: receive a write request from a host, determine a target zone indicated by the write request among the plurality of zones, and determine a logical address of the target zone on which a write operation is to be started based on a write pointer and an offset corresponding to the target zone.

Abstract: A vehicle black box includes a sensor interface for receiving sensor data of a sensor module sensing at least one physical vehicle parameter. Further, the vehicle black box includes a wireless module for receiving a radio frequency signal, wherein the wireless module generates IQ data based on the radio frequency signal received. The vehicle black box also includes a recording module with a first memory for temporarily storing the IQ data generated and a second memory for permanently storing the IQ data generated. Moreover, the vehicle black box has a processing unit configured to receive and evaluate the sensor data. The processing unit is further configured to control a transfer of the IQ data from the first memory to the second memory based upon the evaluation result.

Abstract: A memory system may include: a memory device including a plurality of memory cells, and a controller including: an internal reception queue suitable for queueing a command queued in an external transmission queue, the command being externally provided to the controller, and an internal transmission queue suitable for queueing a response to the command, the response being transmitted from the controller and to be queued in an external reception queue, wherein the controller is suitable for controlling the memory device on the basis of the command to generate the response.

Abstract: An electronic device is provided. The electronic device includes a memory and an integrated circuit. The integrated circuit includes an address remapping unit. The memory includes multiple memory pages. The integrated circuit converts multiple virtual addresses into multiple physical addresses in sequence. The address remapping unit prefetches a first physical address corresponding to a first virtual address if a second virtual address exceeds a preset offset. The first virtual address is in a different memory page from the second virtual address. The second virtual address is currently processed. The multiple virtual addresses include the first and second virtual addresses.

Abstract: A storage device is disclosed. The storage device may include storage for data and at least one Input/Output (I/O) queue for requests from at least one virtual machine (VM) on a host device. The storage device may support an I/O queue creation command to request the allocation of an I/O queue for a VM. The I/O queue creation command may include an LBA range attribute for a range of Logical Block Addresses (LBAs) to be associated with the I/O queue. The storage device may map the range of LBAs to a range of Physical Block Addresses (PBAs) in the storage.

Abstract: A system and method that partitions a snoop filter into sub-partitions that reflect an affinity between a given cluster of cache-coherent agents. The process of partitioning reduces messaging traffic between a cache coherent agents connected to a cache-coherent interconnect. A level of snoop filter partitioning using a range of addresses is disclosed. A unique way to define how many snoop filters are needed and which snoop filter is tracking which cache line, is disclosed. A hierarchy of snoop filters can be used with two levels: a cluster level and an interleaving level.

Abstract: A task manager tightly coupled to a programmable real-time unit (PRU), the task manager configured to: detect a first event; assert, a request to the PRU during a first clock cycle that the PRU perform a second task; receive an acknowledgement of the request from the PRU during the first clock cycle; save a first address in a memory during the first clock cycle of the PRU, the first address corresponding to a first task of the PRU, the first address present in a current program counter of the PRU; load a second address of the memory into a second program counter during the first clock cycle, the second address corresponding to the second task; and load, during a second clock cycle, the second address into the current program counter, wherein the second clock cycle immediately follows the first clock cycle.

Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

Abstract: A system includes a memory including a ring buffer having a plurality of slots and at least one processor in communication with the memory. A subset of the plurality of slots are initialized with an initialization value. Additionally, the at least one processor includes a consumer processor and a producer processor. The producer processor is configured to receive a memory entry, identify an available slot in the ring buffer for the memory entry, and store the memory entry in the available slot at an offset in the ring buffer. The initialization value is interpreted as an unavailable slot by the producer processor. The consumer processor is configured to consume the memory entry and invalidate one of the subset of slots in the ring buffer by overwriting the initialization value with an invalid value to transition the one of the subset of slots from an unavailable slot to an available slot.

Abstract: Mechanisms for proving the correctness of software on relaxed memory hardware are provided, the mechanisms comprising: receiving a specification, a hardware model, and an implementation for the software to be executed on the relaxed memory hardware; evaluating the software using a sequentially consistent hardware model; evaluating the software using a relaxed memory hardware model and at least one of the following conditions: a data-race-free (DRF)-kernel condition; a no-barrier-misuse condition; a memory-isolation condition; a transactional-page-table condition; a write-once-kernel-mapping condition; and a weak-memory-isolation condition; and outputting an indication of whether the software is correct based on the evaluating the software using the sequentially consistent hardware model and the evaluating the software using the relaxed memory hardware model.

Abstract: Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.

Abstract: Methods and systems are provided to facilitate network ingress fairness between applications. At an ingress port of a network, the applications providing data communications are reviewed so that and arbitration process can be used to fairly allocate bandwidth at that ingress port. In a typical process, the bandwidth is allocated based upon the number of flow channels, irrespective of the source and characteristics of those flow channels. At the ingress port, an examination of the application providing the data communication will allow for a more appropriate allocation of input bandwidth.

Abstract: A UART communication interface manages transmission/reception at a baud rate using a baud-rate detection circuit. An edge detector detects edges in a reception signal and resets a count value in a digital counter circuit indicating a time between two consecutive edges. In the absence of a detected edge, the digital counter circuit increases the count value. At a newly detected edge, a validation circuit verifies the count value by asserting a second control signal when the count value is smaller than a maximum, and otherwise de-asserting the second control signal. A register provides a threshold signal by storing the count value when the second control signal is asserted. The threshold signal stored by the register is updated when the time is in a permitted range corresponding to the duration of a single bit. The baud rate may be determined as a function of the threshold signal.

Abstract: A cache stores, along with data that is being transferred from a higher level cache to a lower level cache, information indicating the higher level cache location from which the data was transferred. Upon receiving a request for data that is stored at the location in the higher level cache, a cache controller stores the higher level cache location information in a status tag of the data. The cache controller then transfers the data with the status tag indicating the higher level cache location to a lower level cache. When the data is subsequently updated or evicted from the lower level cache, the cache controller reads the status tag location information and transfers the data back to the location in the higher level cache from which it was originally transferred.

Abstract: Disclosed herein is a method of operating a system in a test mode. When the test mode is an ATPG test mode, the method includes beginning stuck-at testing by setting a scan control signal to a logic one, setting a transition mode signal to a logic 0, and initializing FIFO buffer for ATPG test mode. The FIFO buffer is initialized for ATPG test mode by setting a scan reset signal to a logic 0 to place a write data register and a read data register associated with the FIFO buffer into a reset state, enabling latches of the FIFO buffer using an external enable signal, removing the external enable signal to cause the latches to latch, and setting the scan reset signal to a logic 1 to release the write data register and the read data register from the reset state, while not clocking the write data register.

Abstract: Disclosed in the present application are a multi-shared directory tree-oriented control method and system. The method includes: setting a number of circular queues and a number of worker execution units in a Samba configuration file of a server according to a number of directories to be shared; running a Samba main process on the server; obtaining a data read-write test request from a client; and orienting request tasks of individual directories to individual worker execution units according to the data read-write test request by using a Server Message Block (SMB) message header data-based adaptive equalization control algorithm. The system includes an Input/Output (IO) execution unit, a plurality of worker execution units, a setting unit, a request obtaining unit, and a concurrency control unit. According to the present application, the data processing efficiency of a Samba server and the data processing efficiency of a client may be effectively improved.

Abstract: The systems and methods disclosed herein transparently provide data security using a cryptographic file system layer that selectively intercepts and modifies (e.g., by encrypting) data to be stored in a designated directory. The cryptographic file system layer can be used in combination with one or more cryptographic approaches to provide a server-based secure data solution that makes data more secure and accessible, while eliminating the need for multiple perimeter hardware and software technologies.

Abstract: The present disclosure provides new methods and systems for input/output command rebalancing in virtualized computer systems. For example, an I/O command may be received by a rebalancer from a virtual queue in a container. The container may be in a first virtual machine. A second I/O command may be received from a second virtual queue in a second container which may be located in a second virtual machine. The rebalancer may detect a priority of the first I/O command and a priority of the second I/O command. The rebalancer may then assign an updated priority each I/O command based on a quantity of virtual queues in the virtual machine of origin and a quantity of I/O commands in the virtual queue of origin. The rebalancer may dispatch the I/O commands to a physical queue.

Abstract: Managed units (MUs) of data can be stored on a memory device according to a slice-based layout. A slice of the slice-based layout can include a plurality of stripes, each of the stripes including respective partitions and respective MUs of data. A subset of the stripes each include a quantity of partitions and a first quantity of MUs of data. Another subset of the stripes each include a lesser quantity of partitions and a lesser quantity of MUs of data.

Abstract: Disclosed is a method of virtualizing access queues to machines for glass collection distributed throughout a territory. The distinction of management of requests for unloading full containers is based on the configuration of: the machine; the central server, remotely controlling queue management; the plant using glass coming from the collection to process it; and a fleet of trucks executing collection, following a path suggested by the data bank residing on the central server. In the method, the control center monitors availability of crushed glass at the machines, and demands for glass of a particular type by each production plant. If an emptying request arrives from a machine where one or more glass containment cells is filled, the control center reprocesses the updated paths for the fleet of trucks or transport vehicles and for unloading from the machine to the truck based on the contingent requests from each production plant.

Abstract: In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.

Abstract: Methods and systems are provided for performing lossy dropping and ECN marking in a flow-based network. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow are acknowledged after reaching the egress point of the network, and the acknowledgement packets are sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and perform per-flow packet dropping and ECN marking.

Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.

Abstract: Embodiments include methods, systems and non-transitory computer-readable computer readable media including instructions for executing a prefetch kernel that includes memory accesses for prefetching data for a processing kernel into a memory, and, subsequent to executing at least a portion of the prefetch kernel, executing the processing kernel where the processing kernel includes accesses to data that is stored into the memory resulting from execution of the prefetch kernel.

Abstract: Networks, systems and methods for dynamically filtering market data are disclosed. Streams of market data may be buffered or stored in a queue when inbound rates exceed distribution or publication limitations. Inclusive messages in the queue may be removed, replaced or aggregated, reducing the number of messages to be published when distribution limitations are no longer exceeded.

Abstract: A nonvolatile memory system is disclosed. The nonvolatile memory system includes a host device and a storage device connected to the host device through a physical cable including a power line and a data line. The storage device includes: a nonvolatile memory; a link controller configured to temporarily deactivate the data line while supplying power from the host device through the power line; and a memory controller including a user verification circuit configured to authenticate a user of the storage device and change a state of the memory controller according to a verification result, a relink trigger circuit configured to control the link controller based on the state change of the memory controller, and a data processing circuit configured to encrypt and decrypt data.

Abstract: The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device.

Abstract: A data transmission method includes: obtaining information required for performing an acceleration operation in a virtual input/output ring of a target virtual accelerator, where the information required for performing the acceleration operation uses a predefined data structure, and the data structure occupies one entry of the virtual input/output ring of the target virtual accelerator; determining, according to the information required for performing the acceleration operation, information that can be recognized by the hardware accelerator; and sending the information that can be recognized by the hardware accelerator to the hardware accelerator, where the hardware accelerator is configured to obtain to-be-accelerated data according to the information that can be recognized by the hardware accelerator and perform the acceleration operation on the to-be-accelerated data.

Abstract: In variants, the AI/ML development system can include one or more applications, wherein each application can include: one or more components and one or more state storages. Each application can optionally include one or more event loops, one or more shared storages, and/or one or more time schedulers.

Abstract: A method of bidirectional amplification of proprietary TDMA (Time-Division Multiple Access) data modulated signals over CATV infrastructure is described. A method of upstream/downstream switching based on carrier detection/measurement originated from the master and slave modems embodiment is described, along with upstream/downstream direction switching based on the encoded switching command detection, originating from the master modem.

Abstract: This application discloses a congestion control method and related apparatus. In the congestion control method, a network device first obtains statistical information of a target egress queue within a first time period, where the target egress queue is any target egress queue in the network device. The network device determines an explicit congestion notification (ECN) threshold for the target egress queue within a second time period based on the statistical information of the target egress queue within the first time period, where the second time period is chronologically subsequent to the first time period. When a queue depth of the target egress queue exceeds the ECN threshold within the second time period, the network device sets an ECN mark for a data packet in the target egress queue.

Abstract: Disclosed is a method of allocating a buffer memory to a plurality of data storage zones. In some implementations, the method may include comparing a free buffer space size to a reallocation threshold size that is re-allocable at a reallocation cycle, deallocating, upon a determination that the free buffer space size is smaller than the reallocation threshold size, at least a portion of an occupied buffer space size to create a new free buffer space based on a history of buffer memory utilization of the occupied buffer space, and allocating the existing free buffer space and the new free buffer space to targeted data storage zones based on history of buffer memory utilizations corresponding to the targeted data storage zones.

Abstract: A method of compiling neural network code to executable instructions for execution by a computational acceleration system having a memory circuit and one or more acceleration circuits having a maps data buffer and a kernel data buffer is disclosed, such as for execution by an inference engine circuit architecture which includes a matrix-matrix (MM) accelerator circuit having multiple operating modes to provide a complete matrix multiplication. A representative compiling method includes generating a list of neural network layer model objects; fusing available functions and layers in the list; selecting a cooperative mode, an independent mode, or a combined cooperative and independent mode for execution; selecting a data movement mode and an ordering of computations which reduces usage of the memory circuit; generating an ordered sequence of load objects, compute objects, and store objects; and converting the ordered sequence of load objects, compute objects, and store objects into the executable instructions.

Abstract: An individual multimedia contents broadcasting equipment is disclosed, which includes an individual broadcast process unit which provides a private IP through a DHCP (Dynamic Host Configuration Protocol) to a receiving terminal, which requests a connection, and makes a connection of the receiving terminal through a radio network, and transmits a broadcast content to the connected receiving terminal; and a radio communication unit which forms a radio network and communicates data with the connected receiving terminal through the radio network.