Input/output Data Buffering Patents (Class 710/52)
  • Patent number: 11188469
    Abstract: A block-based storage system may implement page cache write logging. Write requests for a data volume maintained at a storage node may be received at a storage node. A page cache for may be updated in accordance with the request. A log record describing the page cache update may be stored in a page cache write log maintained in a persistent storage device. Once the write request is performed in the page cache and recorded in a log record in the page cache write log, the write request may be acknowledged. Upon recovery from a system failure where data in the page cache is lost, log records in the page cache write log may be replayed to restore to the page cache a state of the page cache prior to the system failure.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: November 30, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Danny Wei, John Luther Guthrie, II, James Michael Thompson, Benjamin Arthur Hawks, Norbert P. Kusters
  • Patent number: 11164359
    Abstract: Apparatus and method for encoding sub-primitives to improve ray tracing efficiency. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a ray tracing graphics pipeline; a sub-primitive generator to subdivide each primitive of a plurality of primitives into a plurality of sub-primitives; a sub-primitive encoder to identify a first subset of the plurality of sub-primitives as being fully transparent and to identify a second subset of the plurality of sub-primitives as being fully opaque; and wherein the first subset of the plurality of primitives identified as being fully transparent are culled prior to further processing of each respective primitive.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: November 2, 2021
    Assignee: INTEL CORPORATION
    Inventor: Holger Gruen
  • Patent number: 11139957
    Abstract: An apparatus and method for creating a finite blockchain is provided. The blockchain comprises a genesis block that is the first block of the blockchain. The genesis block comprising a genesis expiry time. The method comprises the steps of creating a reincarnation block when a predefined condition is satisfied and appending it to the blockchain; determining whether the genesis expiry time has elapsed based on an expiry period; if the genesis expiry time has elapsed then identifying a first reincarnation block; if the first reincarnation block is identified then deleting all the blocks preceding the first reincarnation block including the genesis block in the block chain.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: October 5, 2021
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Hans Ahlbäck, Harri Hakala, Mikael Jaatinen, Leena Marjatta Mattila
  • Patent number: 11120161
    Abstract: In particular embodiments, computer-implemented data processing, systems, and method configured to: receive a request to initiate a transaction between an entity and a data subject, generate (i) a consent receipt for the transaction comprising at least a unique subject identifier and a unique consent receipt key and (ii) a unique cookie to identify the data subject's transaction initiated by the data subject, store the consent receipt for the transaction and the unique cookie, receive a data subject access request from the data subject, verify an identity of the data subject based at least in part on the unique cookie process the request, process the request by identifying one or more pieces of personal data associated with the data subject, and taking one or more actions based at least in part on the data subject access request.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 14, 2021
    Assignee: OneTrust, LLC
    Inventors: Jonathan Blake Brannon, Casey Hill
  • Patent number: 11113205
    Abstract: An example apparatus for die addressing can include an array of memory cells and a memory cache. The memory cache can be configured to store at least a portion of an address mapping table. The address mapping table can include entries that map translation units (TUs) to physical locations in the array. The entries can include data that indicate a location within the array that stores a particular TU without including data that indicates which die of the array the TU is stored in.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jonathan M. Haswell
  • Patent number: 11115147
    Abstract: Embodiments of the present disclosure pertain to improved circuit and system architectures for identifying and managing operating statuses and faults in a system having multiple processing circuit chips. Each of the multiple processing circuit chips includes multiple signal rings, one to provide internal communications among circuitry within the circuit chip, and another with inter-chip communications circuitry to provide communications with neighboring circuit chips. One of the multiple processing circuit chips further includes external communications circuitry to provide communications with an external host.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: September 7, 2021
    Assignee: Groq, Inc.
    Inventors: Matthew Pond Baker, Srivathsa Dhruvanarayan, Boone Jared Severson
  • Patent number: 11108931
    Abstract: An information processing apparatus includes a management unit that deletes from a first region a fax document that has been successfully transferred to a predetermined transmission destination and moves from the first region to a second region a fax document that has been unsuccessfully transferred to a transmission destination. A user is not permitted to perform an operation on the fax document stored in the first region and the user is permitted to perform an operation on the fax document stored in the second region.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: August 31, 2021
    Assignee: FUJIFILM Business Innovation Corp.
    Inventor: Makoto Hamada
  • Patent number: 11102299
    Abstract: A data processing system includes a plurality of computers which include a processor and a memory, a storage device which is connected to the plurality of computers to store data, and a management computer controls the plurality of computers. The computer includes a node pool which can perform, stop, and delete one or more nodes. The node pool includes one or more first nodes which function as a data buffer. The management computer causes the node to measure a performance of data transmission between the data buffer and the storage device, determines a number of increased/decreased nodes on the basis of a measurement result of the performance, and notifies the node pool of a command of performing or deleting the first node according to the determined number of increased/decreased nodes. The node pool adjusts a number of the first nodes according to performing or deleting command.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: August 24, 2021
    Assignee: HITACHI, LTD.
    Inventors: Hirofumi Inomata, Yusuke Funaya, Tetsuro Honmura
  • Patent number: 11093329
    Abstract: A RAID proxy storage-device-assisted data update system includes a RAID parity data storage device and a first RAID primary data storage device without storage-device-assisted data update functionality, and a second RAID primary data storage device with storage-device-assisted data update functionality. The second RAID primary data storage device receives a command that identifies updated primary data for the first RAID primary data storage device and, in response, retrieves the updated primary data, current primary data from the first RAID primary data storage device, and current parity data from the RAID primary parity data storage device. The second RAID primary data storage device performs an XOR operation using the updated primary data, the current primary data, and the current parity data to generate updated parity data, transmits the updated primary data to the first RAID primary data storage device, and transmits the updated parity data to the RAID parity data storage device.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 17, 2021
    Assignee: Dell Products L.P.
    Inventors: Gary Benedict Kotzur, William Emmett Lynn, Kevin Thomas Marks, Chandrashekar Nelogal, James Peter Giannoules, Austin Patrick Bolen
  • Patent number: 11074202
    Abstract: Systems and methods are disclosed for efficient management of bus bandwidth among multiple drivers. An example method may comprise: receiving a request from a driver to map the driver to a device memory of a device to allow the driver to write data on the device memory via a bus; mapping the driver to a random access memory (RAM) such that the driver is to write the data to the RAM; reading contents of the RAM at a specified interval of time to determine whether the data written by the driver is accumulated in the RAM; responsive to determining that the data written by the driver is accumulated in the RAM, determining whether a bandwidth of the bus satisfies a bandwidth condition; and responsive to determining that the bandwidth satisfies the bandwidth condition, forwarding, via the bus, a portion of the data written by the driver in the RAM to the device memory.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: July 27, 2021
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 11068207
    Abstract: Storage systems are disclosed. For instance, a storage system comprises a first storage device of a first type and a second storage device of a second type, and the first storage device has a higher access velocity than the second storage device. A threshold indicating a volume limit of data stored in the first storage device can be determined. Data, which is specified by a write request for writing data to the storage system, is written to the first storage device in response to determining the data amount in the first storage device is lower than the threshold. A read request from a client device is processed based on data stored in the first storage device. Consequently, the first storage device with a higher access velocity in the storage system may be utilized as much as possible, so that storage device latency in the storage system is managed more effectively.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: July 20, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Willa Lang Yuan, Chark Wenshuai Yu
  • Patent number: 11068192
    Abstract: Aspects relate to techniques for using read-only volume replicas in a distributed computing environment to enable over-subscription on server performance. In order to provide a good customer experience, the I/O handling replicas of a volume are typically reserved at a high percentage of the customer's desired performance. A read-only replica of the volume does not serve user I/O, and can therefore be reserved at a much lower percentage of desired performance. Particularly, as the number of read-only replicas increases, the performance reservation can be lowered due to the statistical likelihood that the server(s) hosting at least one read-only replica will have sufficient performance to support the desired reads during new volume creation (even though that performance has not been fully reserved). Aspects relate to techniques for selecting among read-only replicas to serve reads during creation of a new volume copy.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Magee Greenwood, James Michael Thompson, Igor A. Kostic
  • Patent number: 11055218
    Abstract: An apparatus for accelerating tasks during storage caching and tiering includes a processor. First and second storage units are coupled to the processor. A memory unit is coupled to the processor. The memory unit is configured to receive a write data operation. An amount of dirty data in the first storage unit is determined based on the received write data operation. The dirty data includes data present in the first storage unit to be synced to the second storage unit. A sync rate associated with a read data operation from the first storage unit to the second storage unit is decelerated when the amount of dirty data is less than a first threshold value. A write rate associated with a write data operation to the first storage unit is accelerated when the amount of dirty data is less than the first threshold value.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: July 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kanchan Joshi, Suresh Vishnoi
  • Patent number: 11032378
    Abstract: Embodiments disclosed herein relate to systems and methods for separately managing control and data plan contexts for a secure connection during a standby node switchover scenario. Primary and standby nodes for a secure connection can both maintain a data plane context for a secure connection such as IPSec. In the event that the primary node becomes inactive, the standby node can immediately begin processing data plane traffic using the data plane context for the secure connection maintained at the standby node. Control plane information necessary for programming and activating a control plane context can be stored until needed. During a switchover, the standby node can retrieve the control plane information and activate the control plane context after it has begun processing the data plane traffic.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: June 8, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Akash Baid, Vinay M. Cherian, Mark Libby, Nan Luo
  • Patent number: 11030098
    Abstract: An incoming write request received from a client is accessed. The incoming write request comprises a write command to transfer write data to a buffer memory. An initial portion of the write data is written to the buffer memory. An alignment of a final portion of the write data with respect to a memory bank width of the buffer memory is determined. The client is determined to be designated as a burst-overwrite client. In response to determining that the final portion of the write data is unaligned with the memory bank width of the buffer memory, the final portion of the write data is written to the buffer memory without preserving previously stored data based on the client being designated as a burst-overwrite client.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Michael Ou
  • Patent number: 11023468
    Abstract: Methods and apparatus, including computer program products, are provided for first and last aggregation. In one aspect, there is provided a method, which may include receiving, by a calculation engine, a query; detecting, by the calculation engine, whether the query includes a first aggregation and/or a last aggregation over at least one group and at least one keyfigure; optimizing the received query, when the detecting indicates the received query includes the first aggregation and/or the last aggregation, wherein the optimizing further comprises initiating execution of the received query by at least: performing a single read of a table, detecting, from the single table read, at least one group, and indicating, in the detected at least one group, the first aggregation in the at least one keyfigure and/or the last aggregation in the at least one keyfigure; and returning, for the at least one detected group, the indicated first aggregation and/or the indicated second aggregation.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: June 1, 2021
    Assignee: SAP SE
    Inventors: Christoph Weyerhaeuser, Tobias Mindnich, Johannes Merx, Julian Schwing
  • Patent number: 10965607
    Abstract: In one embodiment, a gateway includes a memory, and a processor to, in response to receiving a plurality of content requests, generate a plurality of network flows and flow buffers, each one content request of the plurality of content requests being served by one network flow of the plurality of network flows, and one flow buffer of the plurality of flow buffers, the one flow buffer being included in the memory, the plurality of network flows including a first flow and a second flow, the first flow serving one of the plurality of requests having a first priority level, the second flow serving one of the plurality of requests having a second priority level, the first priority level being higher than the second priority level, and run a network arbiter to give prioritize reading the first flow over reading the second flow when the first flow is non-idle.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 30, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Ian Bastable, James Cunningham, Gareth John Bowen
  • Patent number: 10949210
    Abstract: A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Patent number: 10929333
    Abstract: A Serial Peripheral Interface (SPI) master (110) and method therein for transferring data to a peripheral device in a data communication and processing system (100) are disclosed. The SPI master (110) comprises a memory (111) comprising a list of packets, each packet comprises data associated with a time parameter indicating at which time the data is to be transferred to the peripheral device. The time parameter is configurable. The SPI master further comprises a serial transmit and receive unit (112) to transfer the data in the list at a time according to the time parameter associated with the data.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: February 23, 2021
    Assignee: AXIS AB
    Inventors: Per Zander, Johan Wennersten
  • Patent number: 10922248
    Abstract: A slave device is to be connected to a host device through at least one of a first interface and a second interface. The slave device includes a first terminal group used for the first interface, a second terminal group used for the second interface and a signal input and output part. The first terminal group and the second terminal group are provided at positions identical to terminal groups of another slave device to be connected through a third interface different from the second interface. The signal input and output part supplies a signal to a predetermined terminal in the first terminal group within a predetermined period from supply of power to the slave device, the signal notifying the host device whether the second terminal group is compliant with the second interface.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: February 16, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Isao Kato, Osamu Shibata
  • Patent number: 10908821
    Abstract: A request to read data stored at a memory sub-system can be received. A determination can be made whether the data is stored at a cache of the memory sub-system. responsive to determining that the data is not stored at the cache of the memory sub-system, a determination can be made, by a processing device, of a queue of a set of queues to store the request with other read requests for the data stored at the memory sub-system. Each queue of the et of queues corresponds to a respective cache line of the cache. The request can be stored at the determined queue with the other read requests for the data stored at the memory sub-system.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Dhawal Bavishi
  • Patent number: 10909084
    Abstract: Embodiments of the invention relate to small write performance enhancements for parallel file systems. One embodiment includes flushing a received write transaction from a first memory device to a second memory device on a node in a file system based on one or more byte-ranges within a file system block. It is determined to flush the received write transaction to a recovery log that is stored in a non-volatile storage layer of the file system. If it is determined to flush the received write transaction to the recovery log: appending data associated with the received write transaction in the recovery log of the file system, replicating the data associated with the received write transaction in another non-volatile storage layer of another node if required, and marking the one or more byte-ranges as committed.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: February 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dean Hildebrand, Frank B. Schmuck
  • Patent number: 10891236
    Abstract: A method for operating a data storage device which uses a nonvolatile memory device including a buffer memory block which temporarily stores data, as a storage medium, includes receiving an unmap request which requests that an unmap address be erased, from a host device; storing the unmap address and flag information indicating that the unmap address is unmapped, in a first empty page of the buffer memory block; and mapping the unmap address and flagging flag information indicating that the unmap address is unmapped, in a physical-to-logical (P2L) map corresponding to the first empty page of the buffer memory block.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: January 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Byeong Gyu Park
  • Patent number: 10885946
    Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: January 5, 2021
    Assignee: Rambus Inc.
    Inventor: Thomas Vogelsang
  • Patent number: 10884657
    Abstract: A computer device comprises a first processor; a plurality of memory circuits, a first one of which comprises one or more other processors; a data bus coupling the first processor to each of the memory circuits, each of the memory circuits having a data port with a width of m bits and the data bus having a width of n bits, n being higher than m, the first processor and/or another circuit being suitable for reading or writing the data value of n bits in the first memory circuit by converting a first address into a plurality of second addresses corresponding to memory locations of m bits in the first memory circuit, and by performing the reading or writing operation of the data value of n bits in the first memory circuit over a plurality of memory access operations.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: January 5, 2021
    Assignee: UPMEM
    Inventors: Fabrice Devaux, Jean-François Roy
  • Patent number: 10878127
    Abstract: In particular embodiments, computer-implemented data processing, systems, and method configured to: receive a request to initiate a transaction between an entity and a data subject, generate (i) a consent receipt for the transaction comprising at least a unique subject identifier and a unique consent receipt key and (ii) a unique cookie to identify the data subject's transaction initiated by the data subject, store the consent receipt for the transaction and the unique cookie, receive a data subject access request from the data subject, verify an identity of the data subject based at least in part on the unique cookie process the request, process the request by identifying one or more pieces of personal data associated with the data subject, and taking one or more actions based at least in part on the data subject access request.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: December 29, 2020
    Assignee: OneTrust, LLC
    Inventors: Jonathan Blake Brannon, Casey Hill
  • Patent number: 10853241
    Abstract: Disclosed is a data storing method performed by a controller. The method includes storing an attribute value of first data to be written to a nonvolatile memory device in a command queue, determining whether the first data is garbage collection data on the basis of the attribute value when a power interruption occurs, and writing the first data to the nonvolatile memory device according to a result of the determination of whether the first data is garbage collection data or not.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: December 1, 2020
    Assignees: ESSENCORE Limited
    Inventors: Young Joon Choi, Seok Cheon Kwon
  • Patent number: 10855613
    Abstract: Networks, systems and methods for dynamically filtering market data are disclosed. Streams of market data may be buffered or stored in a queue when inbound rates exceed distribution or publication limitations. Inclusive messages in the queue may be removed, replaced or aggregated, reducing the number of messages to be published when distribution limitations are no longer exceeded.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 1, 2020
    Assignee: Chicago Mercantile Exchange Inc.
    Inventors: Paul J. Callaway, Dennis M. Genetski, Adrien Gracia, James Krause, Vijay Menon
  • Patent number: 10839874
    Abstract: Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
  • Patent number: 10824564
    Abstract: An operation method of a memory controller which is configured to control a nonvolatile memory device includes receiving a command from the outside, calculating a delay time based on a currently available write buffer, a previously available write buffer, and a reference value, and processing the command based on the delay time.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yu-hun Jun, Sil Wan Chang, Heechul Chae, Seontaek Kim, In Hwan Doh
  • Patent number: 10827235
    Abstract: A computer-implemented method is provided for capturing one or more image frames of a real-time streaming video using a wrapper module configured to function with a video player. The wrapper module is in electronic communication with a server. The method includes receiving, by the wrapper module, during streaming of the video by the video player, an indication from a user of a current viewing location in the video to initiate image capturing. The method includes capturing, by the wrapper module, one or more image frames from the video based on the indication of the current viewing location. The method also includes transmitting, by the wrapper module, the one or more captured image frames to the server.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: November 3, 2020
    Assignee: VIACOM INTERNATIONAL INC.
    Inventors: Johnson Tang, Sam Blake Hofsetter, Sarah Epler
  • Patent number: 10824698
    Abstract: Techniques are disclosed for systems and methods to conduct transactions using a Multi-mode Card. A Multi-mode Card may include various components of a Smart Card and be configured to interface directly with a personal electronic device (e.g., a smart phone, a tablet computer, a personal computer, and/or other personal electronic devices) to confirm presence of the Multi-mode Card in an unattended digital transaction, such as for e-commerce and Internet purchases. A transaction system may include a logic device and an interface embedded in or on the Card, a client device such as a personal electronic device, and a server configured to provide a sales interface to a user through the client device. The logic device in the Card may be configured to authorize, encrypt, and/or otherwise facilitate a transaction involving a sale and/or other type of communication between the client device and the server.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: November 3, 2020
    Assignee: CARDLOGIX
    Inventor: Bruce Ross
  • Patent number: 10817414
    Abstract: The apparatuses and methods related to a memory device as the store to program instructions. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jason T. Zawodny, Kyle B. Wheeler, Richard C. Murphy
  • Patent number: 10810309
    Abstract: Methods and systems provide for detecting exploitation of kernel vulnerabilities which typically corrupt memory. The methods and systems are implemented, for example, via a host, which includes a hypervisor, which controls the operating system (OS) user space and the OS kernel space.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: October 20, 2020
    Assignee: Check Point Advanced Threat Prevention Ltd
    Inventors: Dani Frank, Yoav Alon, Aviv Gafni, Ben Omelchenko
  • Patent number: 10802828
    Abstract: Provided are systems and methods for implementing a memory for an integrated circuit device. In various examples, the integrated circuit can operate the memory as a FIFO, where each address in the FIFO is directly addressable. The integrated circuit can include a first register for storing a head pointer and a second register for storing a tail pointer. When new data is written to the memory, the data cat be written starting at the tail pointer location, without the tail pointer being modified. The tail pointer can be incremented using write transactions received from external to the integrated circuit.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: October 13, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Thomas A. Volpe, Nafea Bshara
  • Patent number: 10789187
    Abstract: Problems such as an operation stop of a controller caused by leaving out a mismatch requiring a change can be prevented. When a setting value is changed in a unit operation setting, an allocation management part specifies a storage capacity required for a storage of input data based on the changed setting value, and judges whether a mismatch occurs in an allocation state between the input data and a storage area specified in an I/O allocation setting.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: September 29, 2020
    Assignee: OMRON Corporation
    Inventor: Makoto Okuno
  • Patent number: 10762008
    Abstract: A memory module includes a first memory device that includes first circuit nodes for communication with a memory controller and second circuit nodes for communication inside the memory module, a second memory device that includes first circuit nodes for communication with the memory controller and second circuit nodes for communication inside the memory module, and an internal data bus that couples the first memory device to the second memory device to carry data between the second circuit nodes of the first memory device and the second circuit nodes of the second memory device. When an internal read command is applied to the first memory device and an internal write command is applied to the second memory device, data is transferred from the first memory device to the second memory device through the internal data bus.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: September 1, 2020
    Assignee: SK hynix Inc.
    Inventors: Jung-Hyun Kwon, Do-Sun Hong, Won-Gyu Shin, Seung-Gyu Jeong
  • Patent number: 10756816
    Abstract: A storage controller includes a plurality of submission queues corresponding to an initiator device and a processing device, the processing device to receive a Fibre Channel Protocol (FCP) command from the initiator device and send the FCP command to a first submission queue of the plurality of submission queues, the first submission queue being reserved for use by a kernel space of the storage controller. The processing device further to receive a Non-Volatile Memory Express over Fibre Channel (NVMe/FC) command from the initiator device. The processing device further to send the NVMe/FC command to a second submission queue of the plurality of submission queues without routing the NVMe/FC command through the kernel space, the second submission queue being reserved for direct access by the initiator device to a user space of the storage controller.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: August 25, 2020
    Assignee: Pure Storage, Inc.
    Inventor: Roland Dreier
  • Patent number: 10747666
    Abstract: A memory system includes a non-volatile memory, a buffer memory, and a controller. The controller is configured to write data corresponding to a write command received from a host in the buffer memory, and based on an indication from the host, do not write the data stored in the buffer memory into the non-volatile memory unless a non-volatilization event occurs, the non-volatilization event being one of a flush request from the host and a detection of a power shutdown.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Masahiro Ishiyama
  • Patent number: 10740008
    Abstract: A data reading method includes receiving, by a controller of a memory, a read operation request carrying a first address; performing, by the controller, N read operations on the first address, and obtaining N pieces of data read by the N read operations; and determining, by the controller, whether the N pieces of data are consistent. The method further includes sending, by the controller, response information used to respond to the read operation request if the controller determines that the N pieces of data are consistent, where the response information includes any one of the N pieces of data. The controller may perform T random read operations between any two consecutive read operations of the N read operations to avoid data leakage during reading. If the N pieces of data obtained by performing the N read operations are inconsistent, the memory may send abnormal alarm information to respond to the read operation request to avoid data tampering.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 11, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mingguang Wang, Yu Liu, Jie Chen
  • Patent number: 10725704
    Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: July 28, 2020
    Assignee: Rambus Inc.
    Inventors: Michael L. Takefman, Maher Amer, Riccardo Badalone
  • Patent number: 10725916
    Abstract: A system includes sensors, a first memory component, a second memory component, and an interface. The sensors are configured to generate data responsive to stimuli. Each sensor may transmit its associated data as it becomes available. The first memory component may receive and store sensor data. The second memory component may receive data from the first memory component. The interface may receive data from the second memory component. The sensor data generated during a time which the interface is receiving data from the second memory component is transmitted to the first memory component and stored thereto. No data is transmitted from the first memory component or from the sensors to the second memory component during the time which the interface is receiving data from the second memory component. Subsequently, a subset of data stored on the first memory component is advanced to the second memory component.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: July 28, 2020
    Assignee: InvenSense, Inc.
    Inventors: Vinod Bhat, Amr Zaky, Jatin Gangani
  • Patent number: 10728304
    Abstract: Systems and methods are described to enable synchronized encoding of streaming audio or video content between multiple encoders, in a manner that provides for redundancy of the system to vary based on a demand for the output content. End user devices or content distribution systems can monitor how content is output on end user devices, and report such output to a content encoding system. The encoding system can then redundancy provided for streaming content based on the demand by end users. Streams that are in high demand can be processed with high redundancy among devices that provide seamlessly interchangeable content, thus reducing the likelihood of perceived failure for such streams. Streams that are in low demand can be processed with low redundancy, reducing the computing resources used to process the stream while minimizing the overall impact of a processing failure, should one occur.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: July 28, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Jason LaPier, Aslam Khader
  • Patent number: 10720780
    Abstract: A battery authentication system includes a battery pack, and a host device connected to the battery pack to charge the battery pack. The battery pack includes a battery, a discharge switch that turns on and off discharging of the battery, a charge switch that turns on and off charging of the battery, and a control integrated circuit (IC) that controls the battery. The control IC includes a charge/discharge control circuit that controls the discharge switch and the charge switch, and an authentication circuit that performs a process for performing an authentication with the host device. The authentication circuit is configured to perform a process associated with a first authentication. The charge/discharge control circuit is configured to control the discharge switch to be turned on when the first authentication is established. The authentication circuit is configured to perform a process associated with a second authentication.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: July 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masayoshi Okawa, Hiromasa Takahashi
  • Patent number: 10713083
    Abstract: A method includes using a network interface controller to monitor a transmit ring, wherein the transmit ring comprises a circular ring data structure that stores descriptors, wherein a descriptor describes data and comprises a guest bus address that provides a virtual memory location of the data. The method also includes using the network interface controller to determine that a descriptor has been written to the transmit ring. The method further includes using the network interface controller to attempt to retrieve a translation for the guest bus address. The method includes using the network interface controller to read the descriptor from the transmit ring.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: July 14, 2020
    Assignee: Altera Corporation
    Inventor: Kenneth Vincent Bridgers
  • Patent number: 10712967
    Abstract: A method includes identifying, by a processing entity of a computing device, data units to read from non-volatile memory and to write into ordered buffers of volatile memory. The method further includes generating, by the processing entity, read operations regarding the data units, wherein the number of read operations equals “n”. The method further includes tagging, by the processing entity, each read operation of the read operations with a unique ordered tag value. The method further includes receiving, by the processing entity, read responses to the read operations from the non-volatile memory. The method further includes writing, by the processing entity, data units contained in the read responses into the ordered buffers in accordance with the ordered tag values. The method further includes tracking, by the processing entity, consumption of the data units from the ordered buffers.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: July 14, 2020
    Assignee: Ocient Holdings LLC
    Inventors: George Kondiles, Jason Arnold
  • Patent number: 10691710
    Abstract: Various embodiments relate generally to data science and data analysis, and computer software and systems, to provide an interface between repositories of disparate datasets and computing machine-based entities that seek access to the datasets, and, more specifically, to a computing and data storage platform that facilitates consolidation of one or more datasets, whereby one or more interfaces, such as user interfaces, may be implemented as computerized tools for presenting summarization of dataset attributes to facilitate discovery, formation, and analysis of interrelated collaborative datasets. In some examples, a method may include presenting data representing summary characteristic data in a user interface. This may include user interface elements each specifying a value of a dataset attribute for a collaborative dataset. Also, the method may include presenting aggregated data attributes for a subset of the collaborative dataset associated with the linked atomized datasets.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: June 23, 2020
    Assignee: data.world, Inc.
    Inventors: Shad William Reynolds, David Lee Griffith, Jon Loyens, Bryon Kristen Jacob
  • Patent number: 10642513
    Abstract: A storage device may utilize de-centralized latch management to remove functions from the device controller to the memory die. NAND die located on a common bus may share a pool of latches with one die acting as a proxy or manager for the other die. A bridge or bridges may be used between NAND connections to allow additional die to be controlled by a leader die for the partially de-centralized management of latches. The latch management operations may include a sequence of commands/operations performed by the leader die.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: May 5, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Alon Marcu, Judah Gamliel Hahn, Gadi Vishne, Alex Bazarsky, Ariel Navon
  • Patent number: 10642860
    Abstract: An example method of live migration of distributed databases may include implementing a first intermediate database access mode with respect to a distributed database to be migrated from an original set of storage servers to a destination set of storage servers, wherein, in the first database access mode, database read requests are routed to the original set of storage servers and database update requests are routed to both the original set of storage servers and the destination set of storage servers. The method may further include copying a plurality of records of the distributed database from the original set of storage servers to the destination set of storage servers. The method may further include switching to a second intermediate database access mode, in which database read requests are routed to the destination set of storage servers and database update requests are routed to both the original set of storage servers and the destination set of storage servers.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: May 5, 2020
    Assignee: Electronic Arts Inc.
    Inventors: Greg William Schaefer, Anand Nair, Shengyong Li, MengXin Ye, Xin Feng Zhang, Miao Xiong, Jian Zhou
  • Patent number: 10628054
    Abstract: An apparatus may include a redundant array of independent disks (RAID) array including a plurality of solid state drives (SSDs). The apparatus may further include a RAID array controller coupled to the plurality of SSDs. The RAID array controller may be configured to determine whether one or more logical block addresses (LBAs) of a stripe of the RAID array are unmapped. The one or more LBAs may be associated with one or more SSDs of the plurality of SSDs. The RAID array controller may be configured to determine data corresponding to the stripe based on the determination of whether the one or more LBAs are unmapped. RAID operations (such has Rebuild, Exposed Mode Read, and/or Parity Resync operations) may be optimized based on the knowledge of which LBAs are mapped and unmapped.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Robert Galbraith, Andrew D. Walls