Input/output Data Buffering Patents (Class 710/52)
  • Patent number: 10341097
    Abstract: According to an embodiment, a communication device is connected with another communication device through a quantum communication channel with a shared encryption key. The device includes a communication unit, a sifter, a corrector, a calculator, and an extractor. The communication unit is configured to acquire a sequence of photons through the quantum communication channel and acquire a photon bit string corresponding to the sequence of photons. The sifter is configured to generate a shared bit string from the photon bit string by sifting processing using basis information. The corrector is configured to generate a corrected bit string by correcting an error included in the shared bit string. The calculator is configured to generate a hash-calculated bit string by performing hash calculation on the corrected bit string. The extractor is configured to extract, as the key, from the hash-calculated bit string, a bit string having the length of the key.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: July 2, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ririka Takahashi, Yoshimichi Tanizawa
  • Patent number: 10342026
    Abstract: The present invention relates to transmitting and receiving data in a wireless communication system employing time division duplex, and in particular to a rate matching for the channels which are mapped onto special subframes such as uplink/downlink switching subframes in TDD. Accordingly, at the transmitter, a data block is stored in a memory unit which is to be operated as a circular buffer, the data block is transmitted in a plurality of subframes including special subframes, a special subframe containing an uplink portion and a downlink portion separated from each other by a switching portion; and before the transmission a rate matching is performed by mapping the stored data block onto the plurality of subframes using the circular buffer, wherein the mapping of bits onto two different special subframes starts from different respective positions in the circular buffer. Moreover, a corresponding receiving apparatus and a transmitting and receiving method are provided.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: July 2, 2019
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Alexander Golitschek Edler von Elbwart, Chi Gao, Lilei Wang, Hidetoshi Suzuki
  • Patent number: 10331555
    Abstract: Apparatus, systems, methods, and computer program products for dynamic memory compaction are disclosed. A memory device comprises a plurality of memory blocks and a controller for the memory device. A controller is configured to generate an input/output command to write a data chunk to a first memory block of a plurality of memory blocks. A controller is configured to compact an amount of valid data in a second memory block of a plurality of memory blocks based on a size of an I/O command.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: June 25, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy, Balaji Thraksha Venkataramanan
  • Patent number: 10303371
    Abstract: A storage device includes a nonvolatile memory, a communication interface connectable to an external device, and a control circuit. The control circuit is configured to carry out over an elapsed time period first write operations to write data received through the communication interface in the nonvolatile memory, second write operations to write data stored in a memory region of the nonvolatile memory to another memory region of the nonvolatile memory, and wait operations during which no data are written, read, or erased in the nonvolatile memory, such that the wait operations are carried out during a smaller percentage of the elapsed time period as the elapsed time period becomes longer.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: May 28, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takamasa Hirata
  • Patent number: 10306182
    Abstract: A user equipment (UE) and method of improving video call quality during handover are generally described. After determining that handover has started (306), the UE may suspend (308) frame transmission and store the frames. After determining that handover has completed (310), the UE may discard (312) frames whose age exceeds a predetermined percent of a latency deviation computed from a real-time transport control protocol report. The UE may determine whether transmission of the remaining frames would exceed a delay proportional to a video frame interval multiplied by an uplink bandwidth for a cell to which the UE is connected or a maximum bitrate of a guaranteed bitrate bearer multiplied by a typical period for a non-access stratum bandwidth and discard frames in order of decreasing age until neither the bitrate nor the delay is exceeded by the transmission.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventor: Eric Perraud
  • Patent number: 10298681
    Abstract: The disclosed computer-implemented method for rerouting data sent between application containers and storage containers may include (1) identifying an application container, a storage container that stores data for the application container, and a host that hosts both the application container and the storage container, (2) configuring the application container and the storage container to share a namespace on the host, (3) creating, within the shared namespace on the host, a resource that enables the application container and the storage container to share data, and (4) rerouting at least one item of data sent between the application container and the storage container to pass through the resource in the shared namespace rather than through a kernel of the host. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: May 21, 2019
    Assignee: Veritas Technologies LLC
    Inventors: Gaurav Makin, John Kjell, Kody Kantor, Bruce R. Montague
  • Patent number: 10298496
    Abstract: A data or packet processing device such as a network interface controller may include cache control logic that is configured to receive a first request for processing a first data packet associated with the queue identifier, and obtain a set of memory descriptors associated with the queue identifier from the memory. The set of descriptors can be stored in the cache. When a second request for processing a second data packet associated with the queue identifier is received, the cache control logic can determine that the cache is storing memory descriptors for processing the second data packet, and provide the memory descriptors used for processing the second packet.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: May 21, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Guy Nakibly, Benzi Denkberg, Erez Izenberg, Nafea Bshara, Uri Leder, Ofer Frishman
  • Patent number: 10291232
    Abstract: A counter includes: a computing module (100) and N counting modules (101). Each counting module includes a plurality of counting spaces corresponding to different counting entries, and counting spaces of the same counting entry in different counting modules have the same address, wherein the counting module is arranged to provide a value for computing to the computing module in response to a counting application of a counting application source. The computing module is arranged to read values of the same counting entry in different counting modules and accumulate the read values to obtain a total count value of the counting entry, N being an integer not less than 1. Also disclosed is a counting method.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: May 14, 2019
    Assignee: Sanechips Technology Co., Ltd.
    Inventor: Junjie Yin
  • Patent number: 10289333
    Abstract: An apparatus includes a non-volatile memory and a memory controller coupled to the non-volatile memory. The memory controller includes a processor configured to perform a first operation and a second operation and further includes an access device interface configured to communicate with a first device. The memory controller further includes a wireless interface configured to communicate with a second device to transfer data associated with the second operation to the second device to enable performance at the second device of one or more tasks of the second operation.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 14, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventor: Kapil Sundrani
  • Patent number: 10291839
    Abstract: An image capturing apparatus comprises an image capturing unit, a moving object detection unit, a depth information detection unit configured to detect a plurality of depth information corresponding to each of the plurality of detection regions, a storage control unit configured to store the plurality of depth information as map data in a storage unit. The depth information detection unit detects a second depth information in a second detection region including at least one of regions in which the moving object is detected, and the storage control unit updates only the second depth information detected by the depth information detection unit with respect to the map data stored in the storage unit.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: May 14, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Ayumi Kato
  • Patent number: 10284353
    Abstract: A method for subsurface radio communication includes transmitting voice data through a subsurface environment, by a transmitter of a radio transceiver. The voice data is received through the subsurface environment, by a receiver of the radio transceiver. A transceiver frequency of the radio transceiver is changed to an optimal transceiver frequency in response to a change to the subsurface environment. The transceiver frequency is one of a transmit frequency of the transmitter and a receive frequency of the receiver. A first impedance of a subwavelength antenna is matched to a second impedance of the transceiver in response to a difference between the first impedance and the second impedance exceeding an impedance mismatch value. The subwavelength antenna has a radiating length less than a transceiver wavelength of the radio transceiver operating in free-space at a maximum of the transceiver frequency.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 7, 2019
    Assignee: Sandia Research Corporation
    Inventors: Steven Michael Shope, Paul Raymond Jorgenson
  • Patent number: 10275777
    Abstract: Systems, computer program products, and methods are described herein for a centralized compliance assessment tool. The present invention is configured to deploy a compliance assessment application to be executed in parallel on one or more applications; initiate one or more retrieval scripts configured to cause the one or more applications to generate one or more digital artifacts to indicate a compliance of the one or more applications to one or more regulatory requirements; determine that the one or more applications are compliant with the one or more regulatory requirements based on at least the one or more digital artifacts generated; and initiate an execution of a regulatory report script based on at least determining that the one or more applications are compliant with the one or more regulatory requirement.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: April 30, 2019
    Assignee: Bank of America Corporation
    Inventors: Anthony Edward Copeland, Eileen Marie Daly, IV, Charlene W. Cook
  • Patent number: 10255179
    Abstract: A device that provides garbage collection read throttling includes at least one processor that is configured to receive a request to perform a garbage collection read command on one of a plurality of flash memory circuits. The at least one processor is configured to determine whether garbage collection read throttling is enabled, such as when a garbage collection read throttling criterion is satisfied. The at least one processor is configured to buffer the garbage collection read command when garbage collection read throttling is enabled and perform the garbage collection read command when garbage collection read throttling is disabled. When the garbage collection read throttling is enabled and the garbage collection read command is buffered, the at least one processor is configured to perform the buffered garbage collection read command when garbage collection read throttling is subsequently disabled.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 9, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: YungLi Ji, Yun-Tzuo Lai, Haining Liu, Ming-Yu Tai
  • Patent number: 10248327
    Abstract: A semiconductor memory system and an operating method thereof include: a memory device; and a memory controller including a processor, coupled to the memory device, containing instructions executed by the processor, and configured to provide sets of throttling numbers, select a throttling mode, calculate a garbage collection (GC)/HOST ratio based on at least a part of invalid count of garbage collection (GC) blocks and valid count of BGC blocks, and adjust throttling parameters of commands in accordance with the GC/HOST ratio and a number of erased blocks.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 2, 2019
    Assignee: SK hynix Inc.
    Inventor: Siarhei Kryvaltsevich
  • Patent number: 10249355
    Abstract: Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active clock signal to a command path for a first portion of a command cycle for a command of back-to-back commands. The command path decodes the command and provides an output command signal responsive to the clock signal. The method further includes providing an inactive clock signal to the command path for a second portion of the command cycle for the command of the back-to-back commands.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: April 2, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Kallol Mazumder
  • Patent number: 10241829
    Abstract: The present invention resolves the problems of OS jitter and cache pollution, as well as the loss of versatility and increases in development cost. An information processing apparatus includes a control core on which an operating system is installed, and at least one calculation core which is controlled by the control core and performs a predetermined calculation process. The control core includes calculation core control unit for instructing the calculation core in halting, to start the calculation process to be performed by calculation core. The calculation core includes calculation processing control unit for controlling the calculation core so as to start the calculation process in response to an instruction, provided by the calculation core control unit, about starting the calculation process, and exception detection unit for detecting a preset exception process occurring during execution of the calculation process and halting the calculation process in which the exception process has occurred.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: March 26, 2019
    Assignee: NEC Corporation
    Inventors: Toshikazu Aoyama, Teruyuki Imai, Yasuo Ishii
  • Patent number: 10241918
    Abstract: Provided are a computer program product, system, and method for considering a frequency of access to groups of tracks to select groups of tracks to destage. A first scanning of groups of tracks in the cache is performed to destage each of the groups of tracks having a group frequency satisfying a first frequency requirement. The group frequency indicates a frequency with which the tracks in the group are modified. A second scanning of groups of tracks in the cache is performed to destage each of the groups of tracks having the group frequency satisfying a second frequency requirement.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Lokesh M. Gupta
  • Patent number: 10235082
    Abstract: A method, computer program product, and computer system for receiving, by a computing device, an I/O request for data. A number of storage devices of a plurality of storage devices in a Mapped RAID group that will be used to process the I/O request may be determined. It may be determined whether each storage device of the number of storage devices in the Mapped RAID group that will be used to process the I/O request has a respective threshold number of credits to process the I/O request. If each storage device of the number of storage devices in the Mapped RAID group that will be used to process the I/O request has the respective threshold number of credits, the I/O request may be processed. If at least one storage device of the number of storage devices in the Mapped RAID group that will be used to process the I/O request lacks the respective threshold number of credits, the I/O request may be queued.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: March 19, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Jian Gao, Geng Han, Jibing Dong, Shaoqin Gong, Yousheng Liu, Naizhong Chiu
  • Patent number: 10209815
    Abstract: A touch control and display control module of a touch screen includes (n×y) rows of sensing units disposed on a substrate. The touch control and display control module includes: a control circuit, controlling the touch screen to operate in one of a frame update mode and a touch sensing mode; and n first control lines, y second control lines and n control signal output circuits disposed on the substrate. Each control signal output circuit is coupled to one of the n first control line, and includes y control signal buffer units. Each control signal buffer units is coupled to one of the y second control lines and sensing units of one row to output a voltage signal to the sensing units of that row, to cause the sensing units of that row to operate in one of the frame update mode and the touch sensing mode.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: February 19, 2019
    Assignee: ILI TECHNOLOGY CORP.
    Inventor: Ping-Yu Chan
  • Patent number: 10191855
    Abstract: Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD. The DRAM and the SSD are also sectioned into pages and mapped to pages of the host memory. A host processor is operable to generate Input/Output (I/O) requests. An HBA driver is operable to process the I/O requests. The HBA driver is also operable to detect when the pages of the DRAM are accessed, to determine a rate of page reclamation based on the detection, and to reclaim pages of data in the DRAM by moving pages of data from the DRAM into the pages of the SSD based on the determined rate of page reclamation.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: January 29, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Kishore Kaniyar Sampathkumar, Saugata Das Purkayastha
  • Patent number: 10175887
    Abstract: According to one embodiment, a memory system is configured to operate as one of semiconductor storage devices in a storage array. The memory system includes a nonvolatile memory and a controller. The controller executes a write operation of writing data, received from a host, to the nonvolatile memory, and an internal operation for managing the memory system. When starting the internal operation, the controller estimates a value related to an amount of reduction in performance of the write operation due to the start of the internal operation, based on content of the started internal operation, and notifies the host or one or more other semiconductor storage devices of the estimated value.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: January 8, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • Patent number: 10168731
    Abstract: A processor maintains a minimum setup time for data being transferred between clock domains, including maintaining the minimum setup time in response to a frequency change in a clock signal for at least one of the clock domains. The processor employs one or more control modules that monitor clock edges in each of the clock domains to ensure that data is not accessed by the receiving clock domain from a storage location until a minimum number of phases have elapsed in the transferring clock domain after the data has been written to the storage location. Further, the control module maintains the minimum setup time in response to a change in clock frequency at one or both of the clock domains.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: January 1, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven Kommrusch, Amitabh Mehra, Richard Martin Born
  • Patent number: 10163228
    Abstract: Provided is a medical imaging apparatus including: an image processor configured to extract properties that an object has with respect to at least one feature, based on a plurality of medical images of the object; and a controller configured to control a display to display a first medical image from among the plurality of medical images and the extracted properties and display a first property shown in the first medical image from among the properties and a second property not shown in the first medical image in such a manner that the first property and the second property are distinguished from each other.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG MEDISON CO., LTD.
    Inventors: Won-sik Kim, Moon-ho Park, Yeong-kyeong Seong, Boo-kyung Han
  • Patent number: 10162571
    Abstract: A storage system includes: a controller including a plurality of processors; an interface device; and a plurality of queues associated with the interface device. The plurality of queues each store data transmitted from a processor allocated to the queue to the interface device. The plurality of queues include a private queue and a public queue. The private queue is a queue allocated with only a first processor as one of the plurality of processors, the private queue requiring no exclusion processing when data is stored, whereas the public queue is a queue allocated with two or more second processors in the plurality of processors, the public queue requiring the exclusion processing when data is stored.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: December 25, 2018
    Assignee: HITACHI, LTD.
    Inventor: Aritoki Takada
  • Patent number: 10158686
    Abstract: An apparatus is provided that includes communication channels, and m communication media interfaces, and v virtual lanes. V is a positive integer multiple of the least common multiple of m and n. An information stream is transferred into data and alignment blocks striped across all of the v virtual lanes, the blocks being communicated from the virtual lanes onto the communication channels. The blocks are received on the communication channels. Each of the communication channels transmits a different portion of the blocks striped across all of the v virtual lanes. In more particular embodiments, v>=n>=m. The communication media interfaces can be electrical and optical. Each of the communication channels can include a SerDes interface operating at least 5 Gigabits per second. Furthermore, each of the m communication media interfaces is configured to transmit a different stream of information over a single optical fiber.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: December 18, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Mark A. Gustlin, Oded Trainin, Luca Della Chiesa
  • Patent number: 10152358
    Abstract: The present disclosure provides methods, systems, and media for allowing access to quantum ready and/or quantum enabled computers in a distributed computing environment (e.g., the cloud). Such methods and systems may provide optimization and computational services on the cloud. Methods and systems of the present disclosure may enable quantum computing to be relatively and readily scaled across various types of quantum computers and users at various locations, in some cases without the need for users to have a deep understanding of the resources, implementation or the knowledge that may be required for solving optimization problems using a quantum computer. Systems provided herein may include user interfaces that enable users to perform data analysis in a distributed computing environment while taking advantage of quantum technology in the backend.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: December 11, 2018
    Assignee: 1QB INFORMATION TECHNOLOGIES INC.
    Inventors: Majid Dadashikelayeh, Arman Zaribafiyan
  • Patent number: 10152413
    Abstract: The nonvolatile memory module includes at least one nonvolatile memory device and a device controller configured to receive a storage command from an external device and to perform an operation corresponding to the received storage command. The device controller includes a random access memory (RAM). After completing the corresponding operation, the device controller stores status information in the RAM and then transmits an alert signal to the external device.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: December 11, 2018
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Han-Ju Lee, Youngjin Cho, Sungyong Seo, Youngkwang Yoo
  • Patent number: 10146691
    Abstract: One embodiment provides for a memory system comprising a cache memory and a cache control circuit to receive a request to perform a partial cache line write to a first cache line of the cache memory, merge the request to perform the partial cache line write with a pending request to write to the first cache line, and process a merged request as a full cache line write.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 4, 2018
    Assignee: INTEL CORPORATION
    Inventors: Hashem Hashemi, Saurabh Sharma, Altug Koker
  • Patent number: 10146434
    Abstract: A First-In-First-Out (FIFO) system and a method for providing access to a memory shared by a plurality of N clients are provided. The memory has a single memory space for holding a plurality of data storage arrays that are respectively configured to store data in a first-in-first-out manner for corresponding clients among the N clients. An arbiter is configured to receive memory access requests from two or more of the N clients to perform a FIFO operation, to push data into a corresponding storage array or to pop data from the corresponding storage array in response to the memory access request. The arbiter is configured to select a first at least one of the clients to perform a first FIFO operation in a first memory operation cycle and to select a second at least one of the clients to perform a second FIFO operation in a second memory operation cycle.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: December 4, 2018
    Assignee: Marvell Israel (M.I.S.L) Ltd
    Inventors: Dror Bromberg, Roi Sherman
  • Patent number: 10126962
    Abstract: Techniques are described for performing a memory operation where direct memory access and logical address translation are implemented. A request for an I/O operation received that includes information indicative of whether a physical memory address may be changed and whether sector atomicity is desired. Based on the information, the requested I/O operation is performed using unmodified Block Translation Table (BTT) where the physical location associated with the requested I/O operation is changed and sector atomicity is provided, or modified BTT where a physical location associated with the requested I/O operation is not changed, or modified BTT where a physical location associated with the requested I/O operation is not changed and atomicity is provided.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: November 13, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Neal R. Christiansen, Chandra Kumar Konamki Vijayamuneeswaralu, Scott Chao-Chueh Lee, Atul P. Talesara, Pedro d'Aquino Filocre FS Barbuda
  • Patent number: 10120576
    Abstract: Small objects are efficiently stored with erasure codes by combining a small object with other small objects and/or large objects to form a single large object for chunking, and providing early notification of permanent storage to the sources of the objects to prevent small objects from becoming stale while waiting for additional objects to be combined.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: November 6, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Adam Manzanares, Lluis Pamies-Juarez, Cyril Guyot, Koen De Keyser, Mark Christiaens, Robert Mateescu
  • Patent number: 10114585
    Abstract: Various aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes initiating a memory transaction corresponding to first data. The method includes determining a non-unique first signature and a unique second signature associated with the first data based on content of the first data. The method includes determining if the non-unique first signature is stored in at least one of a local buffer on the SoC separate from the DRAM or the DRAM. The method includes determining if the unique second signature is stored in at least one of the local buffer or the DRAM based on determining the non-unique first signature is stored. The method includes eliminating the memory transaction with respect to the DRAM based on determining the unique second signature is stored.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: October 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jeffrey Hao Chu, Subrato Kumar De, Dexter Tamio Chun, Bohuslav Rychlik, Richard Alan Stewart
  • Patent number: 10114586
    Abstract: Systems and methods for using host command data buffers as extended memory device volatile memory are disclosed. NVM Express implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. Commands may include an indication of a host buffer, resident on the host device, in which to store data for access by the host device. The memory device may use the host buffer as extended memory during execution of the command. As one example, the memory device may process the command in stages, with each stage retrieving data from the host buffer, manipulating the data, and writing the processed data to the same host buffer. As another example, the host buffer can be used for memory device internal relocation and garbage collection operations. Thus, the area/cost of the memory device controller is reduced since less volatile memory is required.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: October 30, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shay Benisty, Yoav Weinberg
  • Patent number: 10101964
    Abstract: A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: October 16, 2018
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: XuHong Xiong, Pingping Shao, ZhongXiang Luo, ChenBin Wang
  • Patent number: 10089013
    Abstract: A data storage system has a plurality of hosts that request writes of data to a relatively high-performance storage device (RHPSD) such as NVRAM, which may be one of a plurality of RHPSDs in a plurality of storage nodes. A storage management system receives the write requests and writes received data to the RHPSD. According to an allocation policy, the storage management system indicates to at least one of the hosts that it should limit its use of RHPSD and it then discards data upon indication from that host to do so. Before being discarded from the RHPSD, the data may be written to a persistent storage device.
    Type: Grant
    Filed: August 28, 2016
    Date of Patent: October 2, 2018
    Assignee: Datrium, Inc.
    Inventors: Garrett Smith, Nitin Garg, Alex Mirgorodsky, R. Hugo Patterson, III, Vasudevan Sangili, Ganesh Venkitachalam
  • Patent number: 10077994
    Abstract: A low energy sensor interface for a microcontroller unit (MCU) is provided. The sensor interface may include a sequencer in operative communication with one or more on-chip peripherals, a count and compare block in communication with one or more sensors and the sequencer, and a highly configurable decoder. The sequencer, the count and compare block and the decoder may be configured to autonomously analyze and collect sensor results using the on-chip peripherals in a low energy mode of operation without intervention from an associated central processing unit (CPU).
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: September 18, 2018
    Assignee: SILICON LABORATORIES NORWAY AS
    Inventor: Erik Fossum Faerevaag
  • Patent number: 10074210
    Abstract: Techniques are disclosed relating to rendering graphics objects that require shader operations to determine visibility. In some embodiments, a graphics unit is configured to process feedback objects, which may require shading to determine whether they are visible relative to previously-processed objects, out of draw order. For example, in embodiments where a buffer is used to store fragment data for deferred rendering, the graphics unit may bypass the buffer and shade feedback objects ahead of earlier non-feedback objects whose fragment data is stored in the buffer. This may allow a determination of whether to remove occluded non-feedback fragment data from the buffer, which may reduce graphics overdraw. In disclosed two-pass techniques, data for feedback objects is first allowed to bypass the buffer for visibility shading, but is then stored in the buffer for a second pass to perform fragment shading to actually determine pixel attributes, which may further reduce overdraw.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: September 11, 2018
    Assignee: Apple Inc.
    Inventors: Christopher L. Spencer, Karl D. Mann, Ralph C. Taylor, Dinesh D. Kuwar
  • Patent number: 10074409
    Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, and arithmetic and control circuitry. The arithmetic and control circuitry may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement simple first-in first-out modules and shift registers in addition to implementing memory modules with random access. Arithmetic and control circuitry may include a multiplexer that determines whether the configurable storage block is implementing simple first-in first-out modules or shift registers. When the configurable storage block implements first-in first-out modules, an up-down counter may be activated to generate a count value received at the multiplexer.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Simon Finn, Carl Ebeling
  • Patent number: 10061734
    Abstract: A control unit provides a number of buffer credits, to one or more channels, in response to an initiation of a startup phase of communication between the one or more channels and the control unit, where the provided number of buffer credits when used for transferring data causes transfer ready operations but no retry operations. The control unit iteratively increases the number of buffer credits by an amount that is high enough to eliminate any transfer ready operations or cause retry operations to occur within a predetermined amount of time from the initiation of the startup phase.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: August 28, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roger G. Hathorn, Bret W. Holley, Matthew J. Kalos
  • Patent number: 10055138
    Abstract: Embodiments are directed to a method of optimizing disk striping input/output (I/O) operations to an array of storage devices, by identifying an I/O request as a full stripe write request that stripes data across a plurality of storage devices of the array, converting the full stripe write request to a SCSI command block (CDB), and putting the SCSI command block in one of a stripe cache or a non-stripe cache that comprises a sorted linked list where each node of the linked list is a link to one of the plurality of storage devices.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: August 21, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Charles Hickey, Krishna Gudipati
  • Patent number: 10049065
    Abstract: A communication system is provided. The communication system includes slave modules outputting collected data to a master module, and outputting data priority processing request information to the master module; and the master module connected to slave modules, collecting data from the slave modules, and processing, by priority, data from a corresponding slave module based on the data priority processing request information received from at least one slave module.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: August 14, 2018
    Assignee: LSIS CO., LTD.
    Inventor: Sung Sik Ham
  • Patent number: 10042682
    Abstract: A send buffer is allocated within a kernel of an operating system (OS) of a first node. An application of the first node includes an application buffer. A message of an application buffer is copied to the send buffer. The kernel of the first node is to aggregate a plurality of the messages stored at the send buffer into a single transfer and to output the single transfer across a network to a second node.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: August 7, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Patrick Estep
  • Patent number: 10031867
    Abstract: A memory bus comprising a plurality of latches arranged sequentially between a source node and a destination node of a channel of the memory bus; and a pulse generator. The pulse generator is operable to generate a sequence of pulses, each sequential pulse to be simultaneously received by the plurality of latches. A pulse is generated for each edge of a clock signal. A first latch of the plurality of latches is operable to pass on a first data sample while a first pulse is received by the first latch of the plurality of latches. A second latch of the plurality of latches is operable to pass on a second data sample towards the first latch of the plurality of latches while the first pulse is simultaneously received by the first and second latches of the plurality of latches.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: July 24, 2018
    Assignee: AMPERE COMPUTING LLC
    Inventor: Arun Jangity
  • Patent number: 10025640
    Abstract: Aspects include balancing work of tasks at a sending node of a transaction server in a network. A method can include processing a task from the top of a work queue at the sending node, where the task is an instance of a transaction which requires a transaction message to be sent from the sending node using a network connection. The transaction message is divided into chunks of partial transaction sub-messages. For each chunk, it can be dynamically determined whether a pacing response indicator is required based on metrics that monitor the activity in the work queue and a number of chunks of the transaction message already sent.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: July 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael D. Brooks, Alan Hollingshead, Julian C. Horn, Philip I. Wakelin
  • Patent number: 10019164
    Abstract: A parallel computer includes a first node and a second node, each including a memory having a plurality of memory areas and a cache memory, and a processing unit that acquires a first group of index levels of the cache memory, the first group of index levels corresponding with addresses of first plurality of memory areas storing data accessed by a job in the first node, when continuing an execution of the job by migrating the job carried out on the first node to the second node, judges whether or not the second node has second plurality of memory areas that are a usable state corresponding to a second group of index levels that has same as or relative position relation with the first group of index levels, and relocates the data to the second plurality of memory areas when the second node has the second plurality of memory areas.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: July 10, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Atsushi Ninomiya
  • Patent number: 10013235
    Abstract: Systems and methods of queuing data for multiple readers and writers are provided. Enqueuing operations are disclosed that can process write functionality and can determine whether ring buffers have potentially filled, and dynamically declare a new ring buffer at a multiple of capacity of the current ring. Dequeuing operations are disclosed that can process read functionality for advancing control and determining whether and when to free ring buffers from memory.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: July 3, 2018
    Assignee: TRAVELPORT, LP
    Inventor: Bryan Karr
  • Patent number: 10009420
    Abstract: Aspects include balancing work of tasks at a sending node of a transaction server in a network. A method can include processing a task from the top of a work queue at the sending node, where the task is an instance of a transaction which requires a transaction message to be sent from the sending node using a network connection. The transaction message is divided into chunks of partial transaction sub-messages. For each chunk, it can be dynamically determined whether a pacing response indicator is required based on metrics that monitor the activity in the work queue and a number of chunks of the transaction message already sent.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: June 26, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael D. Brooks, Alan Hollingshead, Julian C. Horn, Philip I. Wakelin
  • Patent number: 10007446
    Abstract: A method for writing data into a persistent storage device includes grouping a plurality of data entries stored in a temporary storage device to form a data unit, such that the data unit has a size equal to an integer multiple of a size of an access unit of the persistent storage device. The method further includes writing the data unit into the persistent storage device.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: June 26, 2018
    Assignee: Macronix International Co., Ltd.
    Inventors: Wei-Chieh Huang, Li-Chun Huang, Yu-Ming Chang, Hung-Sheng Chang, Hsiang-Pang Li, Ting-Yu Liu, Chien-Hsin Liu, Nai-Ping Kuo
  • Patent number: 10007807
    Abstract: Methods and systems for managing I/O requests in a secure storage appliance are disclosed. One method includes receiving a plurality of I/O requests at the secure storage appliance, each I/O request associated with a block of data and a volume, each volume associated with a plurality of shares stored on a plurality of physical storage devices. The method further includes storing a plurality of blocks of data in buffers of the secure storage appliance, each of the blocks of data associated with one or more of the plurality of I/O requests. The method also includes associating a state with each of the blocks of data, the state selected from a plurality of states associated with processing of an I/O request.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: June 26, 2018
    Assignee: Unisys Corporation
    Inventors: Scott Summers, Albert French
  • Patent number: 10001921
    Abstract: A data migration method includes creating, by a first control processor that controls a first cache memory storing first cache data cached from first storage data stored in a storage, first management information including information indicating a storage location of the first cache data on the first cache memory and information indicating whether or not the first storage data has been updated in accordance with an update of the first cache data for each block of a predetermined data size in the first cache memory, when a program that accesses the first cache data migrates to a different node, transmitting, by the first control processor, the first management information to a second control processor that controls a second cache memory capable of being accessed by the program after migration to the different node.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: June 19, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Atsushi Ninomiya