Abstract: Method and apparatus for improving processor performance. In some embodiments, processing speed may be improved by reusing data stored in a buffer during an initial request by subsequent requests. Assignment of temporary storage buffers in a controller may be made to allow for the potential for reuse of the data. Further, a hot buffer may be designated to allow for reuse of the data stored in the hot buffer. On subsequent requests, data stored in the hot buffer may be sent to a requesting device without re-retrieving the data from memory.

Abstract: A hybrid-type storage system having both SAN and NAS interfaces can be implemented by simple hardware capable of carrying out a SAN function independently of a NAS function and a NAS load. To be more specific, a controller of the storage system comprises a NAS controller for accepting an I/O command issued for a file unit and a SAN controller for accepting an I/O command issued for a block unit. The NAS controller converts an I/O command issued for a file unit into an I/O command issued for a block unit, and transfers the I/O command issued for a block unit to the SAN controller. The SAN controller makes an access to data stored in a disk apparatus in accordance with an I/O command received from the SAN or from the NAS controller as a command issued for a block unit. The NAS and SAN controllers are capable of operating independently of each other.

Abstract: An apparatus and method for maintaining a circular FIFO (first-in, first-out) queue in an I/O (input-output) subsystem of a computer system such as a server, workstation, or storage machine. The queue is coupled to a bypass circuit, used to provide access to data items out of the order in which they were stored in the queue, thus bypassing the latency inherent in retrieving the items from the queue. Control logic maintains write and read pointers indicating locations in the queue for writing and reading data items. The write pointer is incremented upon every data event to the queue, thereby maintaining a history of data that has been written to the queue, which is useful for diagnostic purposes. A history flag is maintained to indicate whether the write pointer has wrapped around the addresses in the queue, indicating whether all data items in the queue are valid for diagnostic purposes.

Abstract: Methods and apparatus, including computer program products, for a write queue descriptor count instruction for high speed queuing. A write queue descriptor count command causes a processor to write a single word containing a queue count for each of a plurality of queue entries in a queue array cache.

Abstract: Provided are a method, system, and article of manufacture, where in one embodiment of the method metadata related to a packet may be allocated in a host memory by a protocol processor, where the host memory may be comprised in a host that may be capable of being coupled to a network adapter. The metadata may be copied from the host memory to an adapter memory that may be associated with the network adapter. The copied metadata may be processed by the protocol processor.

Abstract: A method and processor system that substantially enhances the store gathering capabilities of a store queue entry to enable gathering of a maximum number of proximate-in-time store operations before the entry is selected for dispatch. A counter is provided for each entry to track a time since a last gather to the entry. When a new gather does not occur before the counter reaches a threshold saturation point, the entry is signaled ready for dispatch. By defining an optimum threshold saturation point before the counter expires, sufficient time is provided for the entry to gather a proximate-in-time store operation. The entry may be deemed eligible for selection when certain conditions occur, including the entry becoming full, issuance of a barrier operation, and saturation of the counter. The use of the counter increases the ability of a store queue entry to complete gathering of enough store operations to update an entire cache line before that entry is dispatched to an RC machine.

Abstract: A system and method for distributing a portion of the processing of a received packet among a plurality of service threads. When an ISR or similar process retrieves a packet from a communication interface via a receive descriptor ring, it places the packet on one of a plurality of service queues. Each queue has an associated service thread or process that initiates upper layer protocol processing for queued packets. The ISR may select a particular service queue based on the packet's communication flow or connection. Alternatively, the ISR may use a processor identifier provided by the communication interface to select a queue (e.g., in a multi-processor computer system). Or, other information provided by the interface may be used.

Abstract: A method of controlling a queue buffer (2), said queue buffer (2) being connected to a link (1) and being arranged to queue data units (30) that are to be sent over said link (1) in a queue (20), comprising: determining (S1) a value (QL; QL?av#191) of a length parameter related to the length of said queue (20), comparing (S2) said value (QL; QL?av#191) with a length threshold value (L?th#191; min?th#191; max?th#191) and performing (S3) a congestion notification procedure if said value (QL; QL?av#191) is equal to or greater than said length threshold value (L?th#191; min?th#191; max?th#191), and an automatic threshold adaptation procedure (S4, S7), where said automatic threshold adaptation procedure (S4, S7) is arranged to automatically adapt said length threshold value (L?th#191; min?th#191; max?th#191) on the basis of one or more characteristics of said link (1).

Abstract: Method and apparatus for processing data packets within a communication system such as a synchronous optical network (SONET) detect an invalid byte and drop and shift bytes of data to address an invalid byte. A method according to one embodiment of the present invention, includes receiving a first data packet in the communication system. Thereafter, it is determined whether this packet ends with both a valid byte and an invalid byte of data. If both the valid and invalid bytes are present, the invalid byte is dropped and a valid byte from a succeeding data packet is concatenated with the valid byte of the first data packet, and byte shifting occurs in the succeeding data packet. Byte shifting continues until a second packet ending with an invalid byte is encountered. Skipping a clock cycle at the end of the second packet with the invalid byte results in packets with only valid data.

Abstract: A method for updating a subset of a frame of an image is provided. The frame of the image is subdivided into a plurality of tiles. The method initiates with providing a fixed-size queue having a stationary last packet at a bottom of the fixed size queue. Then, a plurality of packets is stored in a time sorted order above the last packet, the plurality of packets corresponding to a frame of an image. Next, an updated packet is received, the updated packet corresponds to a previously received packet of the plurality of packets. Then, the previously received packet is replaced with the updated packet while maintaining the time sorted order. Replacing the previously received packet includes: identifying the previously received packet adjusting any pointers pointing at the previously received packet to point at a packet below the previously received packet; and moving the previously received packet to a top of the fixed size queue.

Abstract: An LCD controller (10) has a DMA unit (18) and a FIFO memory (20) for storing display data. The LCD controller also has a display data generator (26) that generates display information using a line of the display data stored in the FIFO memory in accordance with a predefined algorithm. A holding register (28) is connected to the display data generator and stores the generated display information. A multiplexer (34) selects for display either the data stored in the FIFO memory or the generated display information. The generated display information is selected when there is a bus overload indicating that the data stored in the FIFO may be erroneous.

Abstract: A disk input/output (I/O) system includes a controller, a cache, a disk I/O subsystem, and a command queue. The load on the queue is monitored and when it reaches a threshold, commands are designated cache only. Cache only commands are added to the queue only if they can be completed without accessing the disk I/O subsystem. If the disk I/O subsystem would be accessed in order to complete a cache only command, the command is returned to the operating system with an error. The operating system can then add the command to an operating system or back-up queue.

Abstract: A refetch logic propagates data from a first source to a link controller by default. The link controller prefetches data from the refetch logic to generate a first packet prior to receiving control of the transmission medium on which the data is to be transmitted. The refetch logic changes sources and propagates to the link controller data from a second source if necessary. At the same time, the refetch logic also causes the link controller to discard the first packet and generate a second packet from data provided by the second source.

Abstract: The present invention focuses on the aggregation of flows belonging to different classes of non-guaranteed-delay traffic into a single FIFO queue in a downstream stage of the multi-stage switch. These include the guaranteed flows requiring bandwidth reservation, the best-effort flows that require a fair share of the excess bandwidth, and the flows that require both types of guarantee. We disclose a credit-based backpressure scheme which selectively controls the traffic originating from the previous stage of the system while achieving the goal of meeting the requirements of the individual flows. The credit function is maintained for each controlled traffic component in the aggregate session, and its objective is to balance the actual arrival rate of the component with the service rate dynamically granted by the downstream scheduler. The number of flows that can be aggregated is related to the complexity of maintaining the credit functions for the different traffic components.

Abstract: A method and system for processing data by a storage controller with a buffer controller coupled to a buffer memory is provided. The method includes, evaluating incoming data block size; determining if the incoming data requires padding; and padding incoming data such that the incoming data can be processed by the buffer controller. The method also includes determining if any pads need to be removed from data that is read from the buffer memory; and removing pads from the data read from the buffer memory. The buffer controller can be set in a mode to receive any MOD size data and includes a first channel with a FIFO for receiving incoming data via a first interface. The buffer controller mode for receiving incoming data can be set by firmware.

Abstract: A communication system for issuing commands from an initiator to a target, thereby allowing the target to write or read out data into/from a memory area which the initiator has and exchanging the data. The initiator transmits read and write commands for the memory area to the target so as not to exceed the total number of commands which can be held by the target. The target holds the received read and write commands, holds references to the commands by different queues, and independently processes the commands, so that the number of the commands to be transmitted can be managed efficiently.

Abstract: The present invention provides method, data transfer controller and system for asynchronously transferring data. The method allows to provide a buffer device. The method further allows to define in the buffer device a plurality of buffer segments. Respective ones of the buffer segments are filled with data from at least one data source device operating in a respective clock domain. Upon any respective buffer segment being filled up, the method allows to generate an indication of availability of the contents of the respective buffer segment to at least one data destination device operating in a respective clock domain. The clock domain of the at least one source device is distinct than the clock domain of the at least one destination device.

Abstract: Coded requests are received from Memory Port Interfaces (608 and 612) and stored into Outgoing Queue (604). Coded requests are also received from Transaction Pipeline (610), some of which may be linked requests. In response to each linked request stored in Outgoing Queue (604), multiple bus requests are generated by Outgoing Queue (604) and assembled by Assembler (602) and placed onto Bus Interface (620).

Abstract: At least one queue parameter for a first process running on a system is determined. A queue management process separate from the first process configures one or more queues on a storage device in accordance with the at least one queue parameter.

Abstract: A method and disc drive are disclosed that employ dynamic buffer size allocation for handling multiple data streams, such as time-sensitive audio/video data. The method involves allocating a certain amount of required buffer space for each data stream to be handled without an interruption in recording or playing back the data stream. The method further involves reallocating the amount of required buffer space for each stream including any additional stream when one or more additional streams are to be added to the total number of streams being handled. The method also involves reallocating the amount of required buffer space for each stream including those streams that remain after any of the data streams being handled are terminated.

Abstract: A model in which filter drivers are managed to receive callbacks for I/O requests in which the filter drivers have registered an interest. Per-volume instances of filter drivers register with a filter manager for pre-callbacks (for I/O to the file system) and post-callbacks (for I/O from the file system), and identify which I/O requests (e.g., create, read, write) they are registering to receive callbacks. The filter manager orders the instances for callbacks. When an I/O request is received, the filter manager converts the I/O request to callback data and calls the interested filters in the callback order, whereby the filter instances can process the I/O data. As the request returns from the file system, filters desiring post callbacks are called in the reverse order. Efficient context management for the filters and other functions, such as non-reentrant file I/O, are also provided by the model.

Abstract: The present invention provides a method of transferring incoming multithreaded concurrent sets of data from a sending transport system to a requesting transport system which includes retrieving the sets of data from the sending transport system. A receiving queue is queried for a number of available data storage locations, and the sets of data being transferred to the receiving queue. The method further includes queuing the sets of data in the receiving queue, where each the set of data are divided into blocks of data. Then, determining a number of the data storage locations for storing the blocks of data. Next, the blocks of data are loaded into available data storage locations, and location indexes are provided for each of the blocks of data where the location indexes associate the block of data with a corresponding the storage location.

Abstract: The method and apparatus presented are targeted to improve the performance of moving data between memory portions connected by a system bus where writes have higher performance than reads, such as the PCI bus. Due to the PCI bus design, read requests from memories connected across the PCI bus take a significantly longer time to complete than performing a write operation under the same circumstances. The present invention uses the faster write operations across the PCI bus, and queue management techniques, to take advantage of the relative speed of writes in a PCI system. The overall result is significant performance enhancement, which is especially useful in service aware networks (SAN) where operation at wired-speed is of paramount importance.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Abstract: A shift register is provided to monitor the difference between the read and write pulses to an elasticity buffer. The shift register essentially eliminates the need for any math functions in the elasticity buffer management logic. The shift register is as wide as the elasticity buffer is deep. In other words, for every word in the elasticity buffer, the shift register has a corresponding bit. Each time a word is written into the elasticity buffer without a simultaneous corresponding read, a value of “1” is shifted from a first end into the shift register, indicating that a space has been taken in the elasticity buffer. For every word read out of the elasticity buffer without a simultaneous corresponding write, a value of “0” (zero) is shifted from a second end of the shift register, indicating that one more space is available.

Abstract: A single atomic instruction is used to change up to four disjoint areas in memory concurrently in an extended compare and swap operation, replacing traditional locks for serialization and providing recovery for all queue manipulations. Use count-based responsibility passing is employed so that any number of tasks can read the various message queue chains, concurrent with queue updates being made. A summary queue update sequence number is maintained to provide concurrent chain update detection, so that any number of tasks can add elements to the end, or remove elements from the middle (i.e. any where in the chain) concurrently. Concurrent footprinting is used with chain manipulation, so that all (or none) of the chaining indicators and a footprint are set with a single, non-interruptible instruction, making it possible for recovery to always take the correct action.

Abstract: Methods, systems, and articles of manufacture for communicating with an I/O processor (IOP) are provided. Polling of message queue pointers is utilized to detect the occurrence of certain message queue related events, rather than rely on interrupts generated by the IOP. The polling may decrease the disruptive effects of IOP generated interrupts. In an effort to minimize the latency associated with detecting IOP related events, the polling may be initiated frequently by an operating system task dispatcher. In an effort to minimize context switches, the task dispatcher may schedule the processing of upstream messages detected while polling to coincide with naturally occurring task swaps.

Abstract: A method and system for a pipelined bus interface macro for use in interconnecting devices within a computer system. The system and method utilizes a pipeline depth signal that indicates a number N of discrete transfer requests that may be sent by a sending device and received by a receiving device prior to acknowledgment of a transfer request by the receiving device. The pipeline depth signal may be dynamically modified, enabling a receiving device to decrement or increment the pipeline depth while one or more unacknowledged requests have been made. The dynamic modifications may occur responsive to many factors, such as an instantaneous reduction in system power consumption, a bus interface performance indicator, a receiving device performance indicator or a system performance indicator.

Abstract: The invention relates to a method and apparatus for transmitting data packets over a channel wherein the data packets have compressed headers. After compressing a header using a context, a number of consecutive update packets are transmitted, each containing data indicating the context. According to the invention, the channel quality is determined and the number of update packets is set accordingly. The channel quality may be determined by measuring the block error rate or the signal-to-noise ratio. Alternatively, the channel quality may be estimated by evaluating whether a NACK message has been received. The total number of update and non-update packets transmitted during a context update phase may be set according to the Round Trip Time. The number of non-update packets may further be determined based on codec properties. The invention may advantageously be used over unreliable, e.g. wireless, channels.

Abstract: A queue-based spin lock with timeout allows a thread to obtain contention-free mutual exclusion in fair, FIFO order, or to abandon its attempt and time out. A thread may handshake with other threads to reclaim its queue node immediately (in the absence of preemption), or mark its queue node to allow reclamation by a successor thread.

Abstract: A method and apparatus for reordering transactions in a packet-based fabric using I/O Streams. Packet bus transactions may flow upstream from node to node on a non-coherent I/O packet bus. Some peripheral buses place ordering constraints on their bus transactions to prevent deadlock situations. When a packet transaction originating on a peripheral bus with ordering constraints is translated to a packet bus such as the non-coherent I/O packet bus, those same ordering constraints may be mapped over to the packet bus transactions. To efficiently handle the packets and prevent deadlock situations, packets may be handled and reordered on an I/O stream basis. Thus, reordering logic may consider I/O streams independently and therefore only reorder transactions within an I/O stream and not across more than one I/O stream.

Abstract: A queuing system utilizing dual first-in, first-out (FIFO) memories is provided. The present queuing system is configured to use a first FIFO memory to receive and transfer a plurality of frames to a second FIFO memory wherein the frames include encrypted frame contents. The first FIFO memory is configured to transfer an interrupt to an associated processor in response to completion of the receipt of a valid frame. Next, the processor is configured to reinitialize the first FIFO memory for receipt of a subsequent frame. Additionally, the second FIFO memory is suitably adapted to concurrently store a plurality of frames transferred from the first FIFO memory. Finally, the present system is configured to transfer one of the stored frames out of the second FIFO memory in response to the completion of a data processing operation (e.g. initialization of a decryption algorithm).

Abstract: The present invention provides a pushback FIFO architecture that enables a value that has been unloaded from the FIFO to be pushed back into the FIFO at the beginning of the data stream if a determination as made that the data value should not have been unloaded from the FIFO. Therefore, the pushed back data value will be the first data value unloaded from the FIFO on the following read cycle. Because the data value that should not have been unloaded is not lost, and is placed at the beginning of the data value sequence, the pushback FIFO enables speculative unloads of data values from the FIFO to be performed.

Abstract: A head and tail caching system. The system includes a tail FIFO memory having a tail input to receive incoming data. A memory is included that is operable to store data that is output from the tail FIFO and output the stored data at a memory output. A multiplexer is included having first and second multiplexer inputs coupled to the tail FIFO and the memory, respectively. The multiplexer has a control input to select one of the multiplexer inputs to coupled to a multiplexer output. A head FIFO memory receives data from the multiplexer output, and outputs the data on an output data path. A controller is operable to transfer one or more blocks data having a selected block size from the tail FIFO to the memory and from the memory to the head FIFO, to achieve a selected efficiency level.

Abstract: A memory controller is disclosed. The memory controller includes a slot-based controller adaptable to launch a packet that straddles a first fixed packet slot and a second fixed packet slot.

Abstract: A two-dimensional command block queue includes a plurality of command blocks in a first linked list. One of the command blocks in a string is included in the first linked list. The string is delimited by only a tail pointer stored in a tail pointer list. Following dequeuing the string for processing, a pointer to the one command block of the string that was in the common queue is included in a string head pointer list. The tail pointer to the string is not changed in the tail pointer list following dequeuing of the string. This allows any new SCBs to be appended to the end of the string, while the string is being processed. This allows streaming of new SCBs to an I/O device that had previously been selected and is still connected to the host adapter.

Abstract: An apparatus and method is provided for scheduling USB transaction processing tasks. A periodic queue head list associated with a USB host controller is configured to be processed once every polling period. The periodic queue head list describes a location of the USB transaction processing tasks scheduled for processing. The entries in a frame list of the USB host controller are linked to identify a corresponding periodic queue head list. A USB transaction processing task processed by the USB host controller is assigned to one of the periodic queue head list. A desired response time for the USB transaction processing task is matched with the polling period of the periodic queue head list.

Abstract: A method and apparatus are provided for caching free cell pointers pointing to memory buffers configured to store data traffic of network connections. In one example, the method stores free cell pointers into a pointer random access memory (RAM). At least one free cell pointer is temporarily stored into internal cache configured to assist in lowering a frequency of reads from and writes to the pointer RAM. A request is received from an external integrated circuit for free cell pointers. Free cell pointers are sent to queues of the external integrated circuit, wherein each free cell pointer in a queue is configured to become a write cell pointer. At least one write cell pointer and a corresponding cell descriptor is received from the external integrated circuit. Free cell pointer counter values are then calculated in order to keep track of the free cell pointers.

Abstract: A host channel adapter configured for outputting packets according to InfiniBand™ protocol is implemented using partitioned link modules configured for performing selected link operations prior to outputting the packets. A pre-link module is configured for ordering work queue entries in an order based on determined service level and virtual lane priorities. The pre-link module outputs the ordered work queue entries to a transport service module configured for generating a transport layer header for the packets based on the respective work queue entries. Once the transport layer headers have been generated, a post-link module is configured for retrieval of the transport layer header and transport data and preparing the transmit data packets for transmission on the network by constructing the link layer fields. The post-link module outputs the transmit data packets based on the ordering and the flow control protocol for the appropriate virtual lanes.

Abstract: A method for prioritizing snoop pushes in a data processing system that schedules requests within a request FIFO. Each new request that is received is placed in the last position of the request FIFO and the request FIFO typically grants request based solely on the order within the request FIFO. As prior requests are sequentially granted the subsequent requests move closer to a first position of the request FIFO. However, when a snoop push is received at the request FIFO, the snoop push is automatically inserted at the first position of the request FIFO ahead of all yet to be granted requests within the request FIFO.

Abstract: A programmable FIFO receives a stream of data to be buffered within the FIFO and then output from the FIFO. The programmable FIFO includes the ability to receive program instructions from an application or control circuit to perform specific operations on the stream of data before the data is provided as an output from the programmable FIFO. By performing the specific operations of the program instructions, the programmable FIFO has the ability to filter the stream of data as it passes through the FIFO, including reordering data within the FIFO, if appropriate, and also to synchronize the input and output of the stream of data with external input and output signals, respectively. The programmable FIFO also has the ability to operate as a typical FIFO and buffer the data without manipulating it. The programmable FIFO includes a programmable element and a FIFO memory and control circuit.

Abstract: A method of processing data relating to graphical primitives to be displayed on a display device using region-based SIMD multiprocessor architecture, has the shading and blending operations deferred until rasterization of the available graphical primitive data is completed.

Abstract: A method and an apparatus for sharing a request queue between two or more destinations. The method and apparatus utilizes a common data table and a common age queue. The age queue is used to select the oldest request. The corresponding request from the common data table is then extracted and sent to the appropriate destination.

Abstract: A technique for implementing a novel high-speed high-density packet buffer utilizing a combination of high-speed and low-speed memory devices. The novel packet buffer is organized as a plurality of first-in-first-out (FIFO) queues where each FIFO queue is associated with a particular input or output line. Each queue comprises a high-speed cache portion that resides in high-speed memory and a low-speed high-density portion that resides in low-speed high-density memory. Each high-speed cache portion contains FIFO data that contains head and/or tail information associated with a corresponding FIFO queue. The low-speed high-density portion contains FIFO data that is not contained in the high-speed cache portion. A queue identifier (QID) directory refills the high-speed portion of one or more queues with data from a corresponding low-speed portion. Queue head start and end offsets are used to determine whether a corresponding queue is empty.

Abstract: A data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The interface includes: a global memory; a plurality of front-end directors coupled between the global memory and the host computer/server; and, a plurality of back-end directors coupled between the global memory and the bank of disk drives. Each one of the first directors and each one of the second directors has a data pipe. Each one of such front-end directors passes front-end data between the global memory and the host computer through the data pipe therein and each one of the second directors passing back-end data between the global memory and the bank of disk drives through the data pipe therein.

Abstract: Multiple non-blocking FIFO queues are concurrently maintained using atomic compare-and-swap (CAS) operations. In accordance with the invention, each queue provides direct access to the nodes stored therein to an application or thread, so that each thread may enqueue and dequeue nodes that it may choose. The prior art merely provided access to the values stored in the node. In order to avoid anomalies, the queue is never allowed to become empty by requiring the presence of at least a dummy node in the queue. The ABA problem is solved by requiring that the next pointer of the tail node in each queue point to a “magic number” unique to the particular queue, such as the pointer to the queue head or the address of the queue head, for example. This obviates any need to maintain a separate count for each node.

Abstract: A mechanism for executing requests in a system. More specifically, a technique for processing requests to a memory system is provided. A shift register may be used to store an index associated with requests, such as read and write requests, to a memory system. Each request is stored in a respective queue depending on the source of the request and the request type (e.g. read or write). Each request includes flags which may be set to determine the processing order of the requests, such that out-of-order processing is feasible. An index corresponding to each of the requests is stored in an index shifter to facilitate the out-of-order processing of the requests. Alternatively, a shift register may be used to store each of the requests. Rather than shifting the indices to facilitate the out-of-order processing of requests, depending on the state of the corresponding request flags, the entire entry may be shifted.

Abstract: In one of the many embodiments disclosed herein, a method for dispatching read and write requests to a memory is disclosed which includes queuing at least one write request in a write queue and queuing an incoming read request in a read queue. The method also includes comparing the read request with at least one write request in the write queue to detect a matching write request, and if there is a matching write request, storing a write queue index of the matching write request as a first entry in an ordering queue. The method further includes dispatching the at least one write request to the memory in response to the first ordering queue entry.

Abstract: An integrated data controller that utilizes a first-in first-out (FIFO) management system that compensates for the unpredictable nature of latency associated with requesting data from memory and enables the timing of data requests to be determined based on the number of pending requests and the amount of data currently residing in the buffer. The FIFO management system includes a FIFO controller and a FIFO buffer that monitor a credit value and a trigger value to determine when to make data request bursts upon a memory unit. The trigger value is an indication of whether there is a sufficient amount of free space for it to be beneficial to make a data request burst and the credit value is a number that indicates the number of a data blocks that should be requested in the data request burst.

Abstract: A single host adapter hardware I/O control block contains information used to specify a transfer of data from a host system to a first target device and in addition information that specifies whether the data is to be mirrored, and if so, optionally identifies a second target device on which the data is to be mirrored. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.