Abstract: A dynamic data queuing mechanism for network packets is disclosed. A three-dimensional coil may be expanded or contracted in length. In addition, the size of each loop of the three-dimensional coil may be adjusted. Moreover, simple circular queue and dynamic buffer management techniques are combined to implement circular queues that may be adjusted in size. Size adjustment, in turn, causes an entire queue either to expand or contract. Circular queue size is changed dynamically, without any copying or moving of queue data. This advantage is attained with little overhead added to conventional circular queues, and is useful in reducing memory requirements for simple circular queues by adjusting queue size as needs change. This is particularly useful for multiple queues that share the same memory space.

Abstract: A method and apparatus is presented providing high-performance lossless data compression implemented in hardware for improving network communications. A compression module useful in a switching platform is also presented capable of compressing data stored in buffer memory. Instructions for a compression task are assigned to the compression module by a microprocessor writing a control block to a queue in stored local memory. The control block informs the compression module of the size and location of the unprocessed data, as well as a location in the buffer memory for storing the processed data and the maximum allowed size for the compressed data. Using this technique, the microprocessor can limit the compression of data to those data streams allowing compression, to those segments that are susceptible to compression, and to those segments that are large enough to show a transmission speed improvement via compression.

Abstract: A buffer for adapting data flows from input channels to output channels is provided. The buffer includes a DRAM organized in blocks and a memory controller for managing assignment of the blocks to the chains of linked blocks. The DRAM contains, as a chain of linked blocks, data associated with each communication channel formed by a pair of input and output channels, and also contains a main queue of free blocks for listing unoccupied blocks. The memory controller includes a cache memory containing a partial queue of free blocks that the memory controller uses in managing block assignment. According to one embodiment, when a level of the partial queue reaches a predetermined minimum limit the cache memory is at least partially filled by a burst from the main queue, and when a level of the partial queue reaches a predetermined maximum limit the cache memory is at least partially emptied by a burst into the main queue.

Abstract: A technique is provided for automatically bypassing a transaction order queue for read completion transactions. The technique incorporates logic within an ASIC bridge, wherein read completion transactions are designated a relaxed ordering attribute value. Logic within the ASIC facilitates the read transactions by bypassing the transaction order queue if the relaxed ordering attribute is set accordingly. Similarly, the logic disables the attribute and enqueues the read completion transaction into the transaction order queue, if the relaxed ordering attribute is set to logical zero.

Abstract: Speculative prefetching during DMA reads in a message-passing, queue-oriented bus system is controlled by creating a special data structure, called a “DMA scoreboard”, for each work queue entry associated with a DMA read. The DMA scoreboard tracks the completion of DMA writes and reads by monitoring acknowledgements received from DMA writes and data tags received from DMA read responses. The DMA scoreboard also contains a section that indicates the current PCI address, and size and number of prefetches to be performed. After a DMA read has completed, the PCI current address is incremented to obtain a new PCI address for the first prefetch request. A new work queue entry is then created from the information in the DMA scoreboard to perform the prefetch.

Abstract: A host controller, such as a host controller for a Universal Serial Bus, may process isochronous and interrupt transfers on a preferential basis. If time permits, bulk and control transfers may be executed. The bulk and control transfers may be executed in queues having a queue context made up of a queue head and one or more transfer descriptors. These queues may be processed one after another in a circular linked list. By uniquely marking an element in the circular linked list and determining the status of the transfer operation, the host controller can be avoid thrashing the bus when the reclaim list is empty.

Abstract: There is provided a micro-processor including (a) a pre-fetch cue FIFO which fetches and stores therein a command code, (b) a pre-fetch cue valid indicating that an effective command code is stored in the pre-fetch cue FIFO, (c) an access priority judging circuit receiving a pre-fetch request signal indicating that there is vacancy in the pre-fetch cue FIFO, a cue empty signal indicating that the pre-fetch cue FIFO is entirely empty, and an operand data request signal indicating that there has been generated an operand data access, and determining a kind of next bus access, (d) a bus state control circuit transmitting a bus interface signal, based on the kind of next bus access having been determined by the access priority judging circuit, and also transmitting a burst transfer signal indicating that a memory is in a condition for carrying out burst transfer, and (e) an access register storing data about the previous bus access.

Abstract: Deter the lowering of the efficiency of data exchange in a data processing device that conducts data communications by using a serial bus conforming to the IEEF 1394 Standards.

Abstract: A queue having a ‘duplicate’ counter associated with each entry whereby duplicate data is not stored in the queue. Before data is placed in the queue, the queue is searched for an entry matching the data to be written. If a match is found, the duplicate counter associated with the entry is incremented. Further, if a match is found and the data stored therein is inconsistent with the current data, the contents of the queue are updated and the duplicate counter associated with the entry is reset to one. If a match is not found, the data is written to the queue and the duplicate counter associated with the entry is initialized to one.

Abstract: A tag-based write-combining apparatus in a microprocessor. The apparatus includes a register that stores the store address of the last write-combinable store passing through the store stage of the pipeline. Tag allocation logic compares the last store address with the store address of a new store and allocates the same tag as was previously allocated to the last store if the addresses are in the same cache line, and assigns the next incremental tag otherwise. Tag registers store write buffer tags associated with store data in write buffers waiting to be written to memory on the processor bus. When the new store reaches the write buffer stage, tag comparators compare the new store tag with the write buffer store tags. If the tags match, the write buffer control logic combines the new store data with the store data in the write buffer with the matching tag.

Abstract: A network interface device and a method of transferring data between a host and a network medium employs transmit descriptors that do not contain transmit status information. Upon fetching a transmit data frame from a host system memory at a location pointed to by a transmit descriptor, the network interface device immediately generates an interrupt to the CPU to allow the CPU to re-use the buffers in which the data frame was stored. At the same time, the network interface device attempts transmissions of the data frame to the network medium. Transmit status information is kept in statistics counters on the network interface device.

Abstract: A command filter selectively forwards received commands to a command queue for in-order execution. If the received command is a probe response command or if probe response information is extracted.from other commands, the probe response is stored in a storage location other than the command queue and executed out-of-order. Data movements specified by memory modifying commands already in the command queue and affecting the cache line in question are also performed out-of-order and the memory modifying command is discarded when it is removed in-order from the command queue.

Abstract: A system and method includes a server that includes a processor and a memory system coupled that are coupled to a bus system. A network interface is coupled to the processor and an egress buffer is coupled to the processor and the network interface by an egress bus.

Abstract: A method and apparatus for prioritizing the use of multifunctional printing system's basic processing resources to permit job streaming. The printing system employs a controller with an improved job contention manager (JCM). A plurality of basic resources of the printing system are provided with a queue. One or more job services, at desired times, signals the JCM to carry out a sub-job of a given job. The signal for each of the sub-jobs includes information about the respective sub-job's, job service and its priority. Responsive to the signal from the job service the JCM adds a corresponding basic resource sub-job to the queues of each basic resource which the sub-job will require to perform the sub-job. A first of the sub-jobs is placed in an “Active” state ready for processing, if the first sub-job is at the top of all of the queues, of all the basic resources, required to perform the first sub-job.

Abstract: A method of deadlock-free, automatic configuration and reconfiguration of modules having a two- or multidimensional cell arrangement, in which a unit for controlling the configuration and reconfiguration manages a set of associated configurable elements, the set being a subset or the total set of all configurable elements, and the management takes place as follows: reconfiguration requests from the associated configurable elements are sent to the unit; the unit processes the requests; the unit processes the configuration data of the command sequence; and after the configuration data has been fully processed, new requests are accepted again, the configuration data still to be loaded of the existing previous requests being loaded from a buffer memory (FILMO) into the configurable elements until a new request occurs.

Abstract: A method for managing a queue of cells received from a plurality of sources, wherein the last cell received is stored at a receive address in a buffer, and a time stamp is established for the last cell received that represents the theoretical time it is to leave the queue. The receive address is inserted into a programmer at a location identified by the time stamp of the last cell received, and an occupancy bit associated with the time stamp is set to an active state. The first cell(s) to leave the queue from the first active occupancy bit following that of the cell that has just left the queue is determined, with the occupancy bits being classified in increasing order of the associated time stamps, and the occupancy bit of the first cell is set to an inactive state when it leaves the queue.

Abstract: Disclosed is an apparatus, method, and system to precisely position packets for a queue based memory controller. The memory controller operates with a queue having a plurality of queue positions. A timestamp logic circuit in communication with the memory controller designates scheduled times for each queue position. The memory controller may schedule a packet for a queue position at a scheduled time. The timestamp logic circuit utilizes a plurality of bubble adders to add bubbles to queue positions to adjust the scheduled time for a packet to precisely position the packet.

Abstract: The present invention relates to a queuing system, implemented in the memory of a computer by the execution of a program element. The queuing system includes a queue with a plurality of memory slots, a write pointer and a read pointer. The write pointer permits to enqueue data elements in successive memory slots of the queue. The read pointer permits to dequeue data elements from the queue memory slots for processing, where these data elements are potentially non-dequeuable. Upon identifying a non-dequeuable data element in a particular memory slot of the queue, the read pointer is capable to skip over the particular memory slot and move on to a successive memory slot.

Abstract: A distributed computing system having (host and I/O) end nodes, switches, routers, and links interconnecting these components is provided. The end nodes use send and receive queue pairs to transmit and receive messages. The end nodes use completion queues to inform the end user when a message has been completely sent or received and whether an error occurred during the message transmission or reception process. A mechanism implements these queue pairs and completion queues in hardware. A mechanism for controlling the transfer of work requests from the consumer to the CA hardware and work completions from the CA hardware to the consumer using head and tail pointers that reference circular buffers is also provided. The QPs and CQs do not contain Work Queue Entries and Completion Queue Entries respectively, but instead contain references to these entries.

Abstract: A method and apparatus is for buffering data cells in a queuing element is presented. Each queuing element includes a partitioned buffer, where the partitioned buffer includes a plurality of partitions. Each of the partitions stores data cells received by the queuing element. Storage of the data cells into the partitions is accomplished by using an array of logical queues. Each logical queue of the array of logical queues maps data cells corresponding to that logical queue to a particular partition of the plurality of partitions. More than one logical queue may map data cells to a particular partition. Each partition may include a reserved portion, where each logical queue that maps to the partition may map a portion of its data cells to the reserved portion. The resources of the reserved portion to which a logical queue maps data cells are reserved to that specific logical queue and cannot be utilized by other logical queues.

Abstract: A system and method for distributing output queue space is provided that includes an output queue (18), a input queue (12), an asynchronous input queue (14), and a credit allocation module (22). The output queue (18) has a certain number of output spaces (19) where each output space (19) represents an output queue credit. The output queue (18) releases output queue credits when releasing data from output spaces (19) and receives data in response to a command being processed from the input queue (12). The input queue (12) queues commands and requests a number of output queue credits in response to receiving a command. The input queue (12) also releases the queued commands for processing in response to receiving the requested number of output queue credits. The asynchronous input queue (14) queues commands and requests a number of output queue credits in response to receiving a command.

Abstract: A main data memory is provided in a network device and includes a plurality of buffers for storing data packets. A plurality of descriptors, or pointers, point to the individual buffers. A status of the descriptors is stored in a descriptor reference memory. The status information includes whether the descriptors are in an active or free state, and an indication of copies of the descriptors in the transmit queues. A descriptor free pool includes a list of the descriptors in the free state.

Abstract: A command queue control device, when there is the command which is not completed in spite of a lapse of prescribed time period, is capable of facilitating the command processing of the disk device, even though delay occurs in the command processing of the disk device, by causing the disk device to facilitate acceleration of the command.

Abstract: A method for managing a buffer queue that stores a data queue, wherein the data queue comprises a set of n data elements, n being at least zero. A head pointer is stored at a first location, which may be in a cache controlled by a first processor. The head pointer indicates a head buffer of the buffer queue. The first processor reads the head pointer to determine the head buffer of the buffer queue when a data element is to be removed from the data queue. The first processor reads a next pointer of the head buffer to determine whether the data queue is empty. The first processor determines that the data queue is empty when the next pointer has a first value, which indicates that the head buffer is a dummy buffer.

Abstract: A method for recording data about internal and external messages in a software system which is, in particular, part of a digital telecommunications switching center. Within a software system which, as a rule, comprises a number of components, the components interchange internal messages with one another and/or receive/transmit external messages to and from the outside world via an interface. Such messages are registered at so-called trace points (TP1, . . . , TPn) defined in the software system, and are transmitted without any delay to a FIFO buffer store (ZS), without any acknowledgment from the receiver, and are stored there until they are read after a request from a data-processing system (PC), which is connected to the software system, for the purpose of processing them further.

Abstract: A need to store data between a producing stage and a consuming stage commonly arises in digital processing applications. However, factors such as fabrication process limitations and circuit area constraints may restrict the amount of available storage. A novel method and apparatus for data buffering are disclosed which use less data storage than would be required by double buffering techniques.

Abstract: A disk array controller having a first interface unit to a host computer, a second interface unit to a plurality of disk drives, a cache memory unit for temporarily storing data to be transferred to and from the disk drives, and a selector unit provided between the first and second interface units and the cache memory unit, wherein a plurality of connection requests from the first and second interface units are queued to preferentially process a connection request for a vacant access port to the cache memory unit.

Abstract: This invention provides a class queuing system where data is placed in queues distinguished by class. The class queuing system distinguishes one class from another based on desired characteristics of a host process such as a network process. The class queuing system groups the class queues into groups based on output ports, for example. Each of the groups is separated into logical or physical multiple levels that extend from an input to an output. Input data is queued in a lowest level queue and the data is moved from level to level until the data is placed in an output queue and transferred via a respective output port. Data movement between levels of the class queues is controlled by weight sets where the weights of the weight sets are determined based on the desired characteristics that distinguish the classes. In this way, classes having greater bandwidth, for example, are moved through the class queues at a faster rate than classes having lower bandwidth specifications.

Abstract: A host channel adapter is configured for efficiently managing multiple queue pairs by compressing queue pairs having similar properties into queue pair tables configured for storing compressed queue pair entries having shared attributes. Hence, multiple virtual queue pairs can be created out of fewer physical queue pairs stored within a queue pair attribute database.

Abstract: In a router comprising one or more network processing (NP) devices for routing data packets from a source NP device to a destination device via a switch fabric, with each network processing device supporting a number of interface ports, each port capable of interfacing with one or more data queues for receiving packets associated with a class-of-service characterizing the routing of the packets, a system and method for routing packets comprising: classifying a packet to be forwarded from a source NP device according to a particular class-of-service and determining outgoing interface port information of a destination NP device to forward the packet, the interface port having a pre-defined queue base address associated therewith; encoding a queue index offset for the packet associated with a particular class-of-service associated with the packet to be routed; forwarding the packet, queue index offset and outgoing interface port information to the destination NP; and, determining a queue identifier from the base

Abstract: A data transfer apparatus and a data transfer system intended to transfer data continuously input or output to/from a main memory without any interruption and to transfer continuous data on a general-purpose bus such as a PCI bus, and a recording medium storing a program that commands a computer to execute all or some of functions of each component of the data transfer apparatus or the data transfer system.

Abstract: Printing priority is ascertained according to a bidding process that allows users to submit bids along with their print jobs. The printer orders the print jobs from highest to lowest bid. This allows individual users to determine the importance of each print job. If urgent, the user can submit a higher bid to place the print job at the top of the queue ahead of print jobs deemed less important by the users that submitted them. Prioritizing the print jobs according to user submitted bids allows the printer to better reflect the urgencies and printing needs of all users.

Abstract: A method of managing a queue of print jobs in a printer is disclosed, wherein the jobs are created by specifying print data and print parameters for each job, and the jobs are put into the print queue, and wherein, before print processing of a job in the queue begins, a start condition for the job is checked and printing is started only when the start condition is fulfilled. The method includes steps of checking a status of mode indicator specifying whether the printer is in a “keep going” mode or a “keep sequence” mode; and, when a job in the queue is reached for which the start condition is not fulfilled, postponing print processing of this job and proceeding with a next job, if any, for which the start condition is fulfilled, if the printer is in the “keep going” mode, or stopping print processing, if the printer is in the “keep sequence” mode.

Abstract: The data transfer apparatus and method employs two queue counters to maintain the status of a first-in-first-out buffer memory. A master count (251) indicates the number of entries available for use within the FIFO (410). New data can be allocated to the FIFO only if this master count is non-zero. This master count is decremented (401) upon allocation of new data to the FIFO. A remote count (252) stores the number of data entries stored in the FIFO. This remote count is incremented (413) upon allocation of data to the FIFO and decremented (414) upon reading data from the FIFO. A confirm decrement signal (408) from the remote count triggers an increment of the master count. This two counter technique makes better use of the available bandwidth than the prior art by not requiring a FIFO depth equal the to the data transfer latency. This technique is particularly useful in systems with delays between the data source and data destination and a mismatch of maximum data transfer rates.

Abstract: The present invention concerns a circuit comprising a memory, a flag/array address circuit and a flag logic circuit. The memory may be configured to read and write data in response to one or more memory address signals. The flag/array address circuit may be configured to present one or more flag address signals in response to (i) one or more enable signals and (ii) a control signal. The flag logic circuit may be configured to present one or more logic flags in response to the one or more flag address signals.

Abstract: Provided is a system, method, and program for managing read and write requests to a cache to process enqueue and dequeue operations for a queue. Upon receiving a data access request to a data block in a memory, a determination is made as to whether any data block is maintained in a cache line entry in the cache. If so, a cache line entry maintaining the data block is accessed to perform the data access request. A first flag, such as a read flag, associated with the accessed cache line entry is set “on” if the data access request is a read request. Further, if the data access request is a write request to update the data block in the memory, a second flag, such as a write flag, associated with the cache line entry including the data to update may be set “on”. The update data may be data to be enqueued onto a queue, where the queue may be, but is not limited to, a circular buffer in the memory having a head and tail pointer.

Abstract: An input/output (I/O) controller in an I/O system processes I/O requests from a host computer to a plurality of I/O devices. The I/O controller generates an interrupt to the host computer and reports a plurality of completed I/O requests from the I/O devices when at least one condition of the I/O system is met. A first condition of the I/O system comprises a predetermined ratio between the total number of unreported I/O completions by the I/O devices and the total number of remaining I/O requests from the host computer. A second condition comprises the expiration of a timer, which starts when the number of remaining I/O requests left to process for any individual I/O device reaches a predetermined minimum limit.

Abstract: A memory request management system for use with a memory system employing a directory-based cache coherency scheme is disclosed. The memory system includes a main memory coupled to receive requests from multiple cache memories. Directory-based logic is used to determine that some requests presented to the main memory can not be completed immediately because the most recent copy of the requested data must be retrieved from another cache memory. These requests are stored in a temporary storage structure and identified as “deferred” requests. Subsequently, predetermined ones of the memory requests that are requesting access to the same main memory address as is being requested by any deferred request are also deferred. When a data retrieval operation is completed, an associated request is designated as undeferred so that processing for that request may be completed, and the request may be removed from the temporary storage structure.

Abstract: Direct memory access controller (DMA) (2) adapted to directly execute C language style FOR tasks, where the FOR task includes a movement of a data element from a first location to a second location in memory, and the movement is controlled by a master DMA engine (MDE) (6). A master DMA engine (MDE) (6) includes a top level state machine (52) to coordinate a context save state machine (54), a parse state machine (56), and a running state machine (58). An loop control descriptor (LCD) queue (74) and a data routing descriptor (DRD) cache store information. The LCD queue allows pipelining of descriptor parsing, while the DRD cache avoids refetching of DRDs on reentry of loops.

Abstract: A method of avoiding deadlocks in cache coherency protocol for a multi-processor computer system, by loading a memory value into a plurality of cache blocks, assigning a first coherency state having a higher collision priority to only one of the cache blocks, and assigning one or more additional coherency states having lower collision priorities to all of the remaining cache blocks. Different system bus codes can be used to indicate the priority of conflicting requests (e.g., DClaim operations) to modify the memory value. The invention also allows folding or elimination of redundant DClaim operations, and can be applied in a global versus local manner within a multi-processor computer system having processing units grouped into at least two clusters.

Abstract: A method in a computing system (100) includes the steps of enqueuing items in a functional queue prioritized according to sort criteria (132), modifying the sort criteria (132) while the functional queue contains the enqued items, and re-prioritizing the enqued items in the functional queue according to the modified sort criteria (132). The computing system (100) includes a set of functions (122) that operate on a queue data structure (130) to maintain enqued items prioritized in the queue data structure (130) after changes in the sort criteria (132). The set of functions (122) operate with an arbitrary number of sort criteria (132) and with arbitrary values for the sort criteria (132).

Abstract: The data processor contains a memory and a data prefetch unit. The data prefetch unit contains a respective FIFO queue for storing prefetched data from each of a number of address streams respectively. The data prefetch unit uses programmable information to generate addresses from a plurality of address streams and prefetches data from addresses successively addressed by a present address for the data stream in response to progress of execution of a program by the processor. The processor has an instruction which causes the data prefetch unit to extract an oldest data from the FIFO queue for an address stream and which causes the data processor to use the oldest data in the manner of operand data of the instruction.

Abstract: A programmable split-queue structure includes a first queue area for receiving entries, a second queue area for outputting entries input to said first queue area, and a queue overflow engine logically coupled to the first queue area and the second queue area. The queue overflow engine functions to transfer entries from the first queue area to the second queue area using one of two transfer modes. The queue overflow engine selects the most appropriate transfer mode based on a prescribed threshold value that can be dynamically programmed. An overflow storage area having high capacity may be provided in an external memory in order to increase the overall capacity of the queue structure.

Abstract: A Redundant Array of Independent Disks (RAID) data storage system includes an AutoRAID memory transaction manager for a disk array controller that enables a consistent, coherent memory image of the data storage space to all processors across hot-plug interfaces. To external processes seeking to read or write data, the memory image looks the same across the hot-plug interface. The disk array controller has two identical controllers, each with its own non-volatile memory, to maintain redundant images of disk array storage space. A hot-plug interface interconnects the two controllers. Each controller has an AutoRAID memory transaction manager that enables sharing of cyclic redundancy check (CRC)-protected memory transactions over the hot-plug interface between the two controllers. The AutoRAID memory transaction managers also facilitate ordered execution of the memory transactions regardless of which controller originated the transactions.

Abstract: Disclosed is an apparatus, method, and system to precisely position packets for a queue based memory controller. The memory controller operates with a queue having a plurality of queue positions. A timestamp logic circuit in communication with the memory controller designates scheduled times for each queue position. The memory controller may schedule a packet for a queue position at a scheduled time. The timestamp logic circuit utilizes a plurality of bubble adders to add bubbles to queue positions to adjust the scheduled time for a packet to precisely position the packet.

Abstract: A method and system in data processing system are disclosed for efficiently servicing requests to access a disk. Each of the requests are associated with a location on the disk. The requests include real-time requests and non-real time requests. A most urgent one of the requests is determined. The most urgent one of the requests is associated with a first deadline and a first location on the disk. A second most urgent one of the requests is also determined. The second most urgent one of the requests is associated with a second deadline and a second location on the disk. The first deadline is earlier in time than the second deadline. A service time is determined. The service time is earlier in time than the first deadline. The service time is determined so that sufficient time will exist to service the most urgent one of the requests before the first deadline and service the second most urgent one of the requests before the second deadline.

Abstract: A queuing architecture and method for scheduling disk drive access requests in a video server. The queuing architecture employs at least two access request queues for each disk drive within a disk drive array, and a queue selector for selecting the first and second queues. The first queue is for disk access requests by steady-state users requesting new data streams who are currently viewing a program from the video server. The second queue is for all other types of disk access requests, including requests by new users, requests for loading content, disk maintenance, meta-data synchronizing, and the like. Steady-state disk access requests are serviced in order of ascending time deadlines. The queue selector gives highest priority to requests in the first queue, and requests from the second queue are serviced only upon a guarantee that all of the steady-state requests in the first queue will meet their time deadlines in the worst case access times for the disk drives.

Abstract: A write combining buffer that supports snoop requests includes a first cache memory and a second cache memory. The apparatus also includes a write combining buffer, coupled to the first and second cache memories, to combine data from a plurality of store operations. Each of the plurality of store operations is to at least a part of a cache line, and the write combining buffer can be snooped in response to requests initiated external to the apparatus.

Abstract: A buffer management subsystem receives data from one or more source processes for transfer to one or more destination processes. The buffer management subsystem includes a buffer memory and a buffer pointer FIFO that associated with one of the destination process. The buffer pointer FIFO stores pointers to buffers in the buffer memory which are available to be used to store data from the source process(es) for transfer to the respective associated destination process. When data is received from a source process for transfer to a destination process, a buffer pointer is retrieved from the buffer pointer FIFO associated with the destination process and used in storing the data in the buffer pointed to by the buffer pointer. When the data is retrieved from the buffer for transfer to the destination process, the buffer pointer to the buffer is returned to the buffer pointer FIFO.

Abstract: A computer program product and storage device used for exchange and transfer of data in a network computing system having a main storage capable of connecting to at least one application server and an interface element with at least one adapter capable of establishing processing communication with at least one application user(s).