Abstract: A data transmission method includes obtaining dequeue information that indicates a queue which requests to output data in a communications device and a target data volume that is output from each queue at a time, and the communications device manages the target data volume based on a burst value, reading, based on the queue, a sub-packet descriptor (PD) that is obtained by segmenting the first PD, the sub-PD includes target description information indicating a target data packet, the first PD includes first description information indicating a first data packet set including the target data packet, the first data packet set and the sub-PD are stored in a packet cache including a dynamic random access memory (DRAM), the first PD is stored in a control cache including a static random access memory (SRAM), and determining, the target data packet based on the sub-PD, and sending the target data packet.

Abstract: A bus data analysis method comprises the steps of receiving an input signal, decoding the input signal according to a protocol, thereby extracting a data signal from the input signal, and analyzing the data signal extracted from the input signal statistically, thereby generating a statistically analyzed data signal. Furthermore, a bus data analysis system is described.

Abstract: Provided are a data integrity protection method and device for protecting key data in control components of an industrial control system. The method includes establishing a correlation among a plurality of control components in the industrial control system; and determining a summary indicating the integrity of data to be protected in a first control component based on identity features and data features of other control components correlated to the first control component among the plurality of control components. The data features are used for identifying the data to be protected in the control components, and the first control component is any one of the plurality of control components. Since the security of the data in any control component is established over other correlated control components, the key data in the control components can be effectively protected.

Abstract: Various systems and methods are provided for prioritized sending of transaction messages to an electronic exchange. According to one embodiment, a system determines a priority level for each transaction message based on a potential monetary reward or risk associated with sending or delaying the message. Once the priority levels are determined, the messages may be sent based on the priority levels. Additionally, each priority level may be associated with a predetermined threshold level. If a message threshold is reached, a new message corresponding to that priority level is queued until the message may be transmitted without exceeding the threshold limit.

Abstract: A data storage device with improved space-trimming capability. A microcontroller operating in accordance with a host allocates a non-volatile memory to store data. The microcontroller manages the mapping information between the logical addresses used by the host and the space of the non-volatile memory. The microcontroller further takes responsibility for the transformation of a trimming command that is issued by the host to invoke a plurality of trimming requests. After the transformation, a target-host block repeatedly indicated by the plurality of trimming requests is transformed to be trimmed at one time. The mapping information of the target-host block, therefore, is not read frequently from the non-volatile memory for real-time amendment.

Abstract: The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access with a memory device includes receiving at least one command from a host and controlling execution of the at least one command with the memory device.

Abstract: Systems and methods that facilitate reduced latency via stashing in multi-level cache memory architectures of systems on chips (SoCs) are provided. One method involves stashing, by a device includes a plurality of multi-processor central processing unit cores, first data into a first cache memory of a plurality of cache memories, the plurality of cache memories being associated with a multi-level cache memory architecture. The method also includes generating control information including: a first instruction to cause monitoring contents of a second cache memory of the plurality of cache memories to determine whether a defined condition is satisfied for the second cache memory; and a second instruction to cause prefetching the first data into the second cache memory of the plurality of cache memories based on a determination that the defined condition is satisfied.

Abstract: A page replacement algorithm is provided. An idle range of memory pages is determined based, at least in part, on indications of references to memory pages in the idle range of memory pages, wherein the idle range of memory pages is a set of one or more memory pages. A first memory page is identified in the idle range of memory page for paging out of memory. The first memory page is identified based, at least in part, on indications of modifications to the memory pages. The first memory page is paged out of memory.

Abstract: A method and system are provided for processing a reply message out of order from a first-in-first-out (FIFO) storage, and processing other messages in an order as received in the FIFO storage. The system provides a second FIFO storage for storing any messages that have been retrieved from the first FIFO while searching for the reply message.

Abstract: A data storage device includes: a nonvolatile memory device comprising a plurality of memory blocks, each including a plurality of pages; and a controller suitable for controlling an operation of the nonvolatile memory device in response to a request from an external device, wherein the controller determines whether or not a memory block including damaged pages in which stored data are damaged occurs in the memory blocks, sets a memory block including the damaged pages to an invalid memory block based on the determination result, and regenerates free pages of the memory block set as the invalid memory block into a valid memory block.

Abstract: Aspects of the invention relate generally to validating array bounds in an API emulator. More specifically, an OpenGL (or OpenGL ES) emulator may examine each array accessed by a 3D graphic program. If the program requests information outside of an array, the emulator may return an error when the graphic is drawn. However, when the user (here, a programmer) queries the value of the array, the correct value (or the value provided by the programmer) may be returned. In another example, the emulator may examine index buffers which contain the indices of the elements on the other arrays to access. If the program requests a value which is not within the range, the emulator may return an error when the graphic is drawn. Again, when the programmer queries the value of the array, the correct value (or the value provided by the programmer) may be returned.

Abstract: Techniques for configuring validation rules in a client-server architecture, and for enforcing such validation rules are provided. A developer is enabled to configure a display screen for an application to enable a user at a client to input data. The developer is further enabled to input a validation rule that is configured to be applied to validate the data at the client and/or at a server. The validation rule is integrated into code of the application. During execution of the application, a client-side rules engine may be present to evaluate the validation rule at the client, and a server-side rules engine may be present to evaluate the validation rule at the server. The client-side rules engine and server-side rules engine may be configured to evaluate validation rules in an asynchronous manner.

Abstract: A buffer controller includes a first write pointer generation module for generating a first write pointer that points to a first sequence of write locations in a buffer memory, that directs an input module to store a sequence of samples of a real-time signal in a buffer memory. A read pointer generation module generates a plurality of read pointers for a corresponding plurality of output modules, wherein each of the plurality of read pointers points to a sequence of read locations in the buffer memory, in a buffer order, that contain the sequence of samples.

Abstract: This disclosure describes techniques to improve a user experience in a Wireless Display (WD) system. The WD system includes a source device that provides media data to one or more sink devices. The techniques are directed toward reducing end-to-end latency in the WD system while improving video playback quality at the sink devices. More specifically, the techniques include customized buffering at the sink devices based on application awareness for the media data. The techniques include learning the type of application for the media data, and adjusting the size of buffers in the processing pipeline to achieve an appropriate balance between smoothness and latency for the application type. For example, when the media data is for a video playback application, the techniques include increasing the buffer size to increase smoothness in the video playback application.

Abstract: One or more out-of-band input signals (GPIO) are handled and efficiently embedded into a USB capture stream. In order to conserve resources, the state of the input signals can be sent only when a change occurs. The signals are accurately time-stamped, and then presented within the context of the captured USB data. In order to provide maximum visibility, if the digital inputs occur during a normally filtered multi-packet sequence, the filter is canceled and the surrounding packets will also be sent to an analysis computer. Furthermore, because digital inputs may happen during a USB packet, the digital inputs are queued in a FIFO buffer until there is an opportunity to send the digital inputs. Even though the state of the inputs may be sent at a later time, the state of the inputs may be time-stamped when the state of the inputs is perceived by the analyzer.

Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.

Abstract: Buffer memory reservation techniques for use with NAND flash memory include dynamically reserving regions of the buffer memory, responsive to a read/write request. Where the read/write request includes a plurality of data transfer requests, following completion of a data transfer request, the reserved buffer space may be recycled for use in a further data transfer request or for other purposes. During fulfillment of a read request, a buffer region is reserved from a larger buffer pool for a time period significantly smaller than the time required to execute a sense operation associated with the read request. The reserved buffer region may be reused for unrelated processes during execution of the sense operation.

Abstract: A method and system for processing buffer status reports (BSRs) such that when BSR triggering is performed, the size(s) of the necessary sub-header(s) are also to be considered together in addition to the BSR size. The steps of checking whether any padding region is available in a MAC PDU that was constructed, comparing the number of padding bits with the size of the BSR plus its sub-header, and if the number of padding bits is larger than the size of the BSR plus its sub-header, triggering BSR are performed. Doing so allows the sub-header(s) to be inserted or included into the MAC PDU or transport block (TB) or other type of data unit.

Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.

Abstract: Tracking several open data connections is difficult with a large number of connections. Checking for timeouts in software uses valuable processor resources. Employing a co-processor dedicated to checking timeouts uses valuable logic resources and consumes extra space. In one embodiment, a finite state machine implemented in hardware increases the speed connections can be checked for timeouts. The finite state machine stores a last accessed time stamp for each connection in a memory, and loops through the memory to compare each last accessed time stamp with a current time stamp of the system minus a global timeout value. In this manner, the finite state machine can efficiently find and react to timed out connections.

Abstract: An adaptive multi-thread buffer supports multiple writer process and reader processes simultaneously without blocking. Writer processes are assigned a reserved write slot using a writer index that is incremented for each write request. When a reserved write slot is not null, the buffer is resized to make room for new data. Reader processes are assigned a reserved read slot using a reader index that is incremented for each read request. When data is read out to the reader process, the read slot content is set to null. When a writer process attempts to write null data to a write slot, the buffer replaces the null write data with an empty value object so that content of the buffer is null only for empty slots. When an empty value object is read from a slot, the buffer replaces the content with null data to send to the reader process.

Abstract: An assembly where a number of receivers receiving packets for storing in queues in a storage and a means for de-queuing data from the storage. A controller determines addresses for the storage, the address being determined on the basis of at least a fill level of the queue(s), where information relating to de-queues addresses is only read-out when the fill-level(s) exceed a limit so as to not spend bandwidth on this information before it is required.

Abstract: An interfacing circuit comprising a First In First Out (FIFO) memory for exchanging data between a “data producer device” and a “data consumer device”. The FIFO memory is controlled by first write control signals (WR, CLK_WR) and second read control signals (ENABLE, Clk_Rd). The interfacing circuit further includes: a redundancy filter (230) for receiving a sequence of N data (Y0, Y1, Y2 . . . Yn?1 ) to be stored within said FIFO, and for generating a redundancy control word representative of the presence of consecutive identical data within said sequence; means (250) for controlling said first and said second control signals of said FIFO for the purpose of preventing the storage into said FIFO of multiple consecutive identical data and more important to make possible to accelerate the average speed of the data flux going to the “data consumer device” without need to accelerate the clocking of the memory feeding the said FIFO thanks to increase of efficiency of transfers due to redundancy filtering.

Abstract: A gasket of a data processing device controls the number of released storage locations of a buffer where read and write access requests are stored so that more read access requests can be stored without a corresponding increase in the amount of space at the buffer to store write access requests. An interface of the gasket accepts new access requests from one or more requesting modules only when a number of released storage locations at a buffer associated with the interface (referred to as an outbound buffer) is above a threshold number. As long as the number of stored access requests at the outbound buffer are less than a threshold amount, a buffer location can be immediately released. In addition, the gasket is configured to issue read access requests from the outbound buffer without regard to whether the inbound buffer has space available.

Abstract: A tape drive, tape drive recording system, and method are provided for improving tape speed selection during data transfer. The tape drive includes a buffer, a tape for recording the data to be temporarily stored in the buffer, and a read head. The tape drive further includes a reading controller that initially sets a tape speed such that a drive transfer rate matches a host transfer rate as closely as possible and that drives the tape at the tape speed. To address backhitching caused by one or more host transfer halts, the reading controller subsequently adjusts the tape speed such that the drive transfer rate is lower than the host transfer rate by recalculating the host transfer rate in consideration of the host transfer and the host transfer halt and setting the tape speed such that the drive transfer rate matches the recalculated host transfer rate as closely as possible.

Abstract: A method for operating a fieldbus interface (FI) connected to a fieldbus of process automation technology. The method includes the following: tapping data traffic on the fieldbus by the fieldbus interface; and registering tapped configuration information relative to cyclic data traffic on the fieldbus by the fieldbus interface.

Abstract: Various embodiments relate to systems and methods for simultaneously switching input image streams to output devices, while providing optional image processing functions on the image streams. Certain embodiments may provide vision systems and methods suitable for use in vehicles, particularly windowless vehicles, such as armored ground vehicles, submerged watercraft, and spacecraft. Some embodiments may enable sharing of image streams (e.g., with one or more other vehicles), generation of panoramic views (e.g., from various camera feeds), intelligent encoding of image streams, and implementation of security features based on image streams.

Abstract: A method for operating a peripheral device includes receiving at the peripheral device service orders, which are identified with respective service instances and are submitted to the peripheral device over the bus by software applications running on a host processor, which write copies of the service orders to a memory. The received service orders are queued for execution by the peripheral device. When one or more of the service orders have been dropped from the queue prior to execution, a recovery of a selected service instance is initiated by submitting a read request from the peripheral device to the memory over the bus to receive a copy of any unexecuted service order associated with the service instance.

Abstract: A method for managing a queue, such as for example a FIFO queue, and executing a look-ahead function on the data contained in the queue includes associating to the data in the queue respective state variables (C1, C2, . . . CK), the value of each of which represents the number of times a datum is present in the queue. The look-ahead function is then executed on the respective state variables, preferentially using a number of state variables (C1, C2, . . . CK) equal to the number of different values that may be assumed by the data in the queue. The look-ahead function can involve identification of the presence of a given datum in the queue and is, in that case, executed by verifying whether among the state variables (C1, C2, . . . CK) there exists a corresponding state variable with non-nil value.

Abstract: Various embodiments of the present invention provide systems and methods for monitoring out of order data decoding. For example, a method for monitoring out of order data processing is provided that includes receiving a plurality of data sets that is associated with a plurality of identifiers with each of the plurality of identifiers indicates a respective one of the plurality of data sets; storing each of the plurality of identifiers in a FIFO memory in an order that the corresponding data sets of the plurality of data sets was received; processing the plurality of data sets such that at least one of the plurality of data sets is provided as an output data set; accessing the next available identifier from the FIFO memory; and asserting an out of order signal when the next available identifier is not the same as the identifier associated with the output data set.

Abstract: A system and method for dynamically migrating stash transactions include first and second processing cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), and an operating system (OS) scheduler. The first core executes a first thread associated with a frame manager. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers to indicate scheduling-out and scheduling-in of the first thread from the first core and to the second core. The STMMU uses the pre-empt notifiers to enable dynamic stash transaction migration.

Abstract: A method, system, and computer program product for fast cancellation of an I/O request in a data processing system are provided in the illustrative embodiments. A first component in a stack comprising a plurality of components determines whether a memory buffer associated with the I/O request is valid, the memory buffer being an addressable area in a memory in the data processing system. The first component, responsive to the memory buffer being valid, creates a first request data structure corresponding to the I/O request, wherein the first request data structure includes a reference to the memory buffer. The first component passes the first request data structure to a second component in the stack.

Abstract: According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a peripheral interface and may not require a response. It may then be determined that an error is associated with the message, and an alert message may be sent from the upstream device to the downstream device via the peripheral interface.

Abstract: A method, apparatus, and machine readable storage medium is disclosed for establishing a test protocol processor which autonomously intercepts success path protocol messages at a network element port buffer and substitutes a corresponding failure path messages to simulate the introduction of unexpected protocol messages into the protocol message flow from an external source to the network element under test. Subsequent to intercepting messages, the test protocol processor may perform one or more of several actions according to the results of statistical calculations. These actions include allowing the message to drop, replacing the message after a delay, replacing the message after altering the payload of the message, and replacing the message after altering the message type. The disclosed autonomous self disrupting network element is particularly useful for providing a means to perform in situ field testing of network performance indicators under desired statistical conditions.

Abstract: A method for validating outsourced processing of a priority queue includes configuring a verifier for independent, single-pass processing of priority queue operations that include insertion operations and extraction operations and priorities associated with each operation. The verifier may be configured to validate N operations using a memory space having a size that is proportional to the square root of N using an algorithm to buffer the operations as a series of R epochs. Extractions associated with each individual epoch may be monitored using arrays Y and Z. Insertions for the epoch k may monitored using arrays X and Z. The processing of the priority queue operations may be verified based on the equality or inequality of the arrays X, Y, and Z. Hashed values for the arrays may be used to test their equality to conserve storage requirements.

Abstract: A method for storing information, the method includes: receiving information to be stored on a removable mass storage device; and storing a compact disc recordable (CDR) session representation on a non-optical re-writable storage area of the removable mass storage device; wherein the CDR session representation comprises the received information.

Abstract: Herein described are at least a system and a method for regulating data flow in a data pipeline that may be used in a video processing system. The system comprises a processor, one or more data buffers, and one or more processing stations. The one or more data buffers may be used to buffer corresponding processing stations. Each of the one or more processing stations may comprise a switching circuitry that is used to inhibit data transmission when a hold signal is received from the processor. The processor may send the signal in response to a feedback control signal generated by the one or more processing stations. The method may comprise determining if the processing time of a processing station exceeds a specified time. The method further comprises generating a feedback control signal to a processor if the specified time is exceeded.

Abstract: A computer implemented method for writing to a software bound ring buffer. A network adapter may determine that data is available to write to the software bound ring buffer. The network adapter determines that a read index is not equal to a write index, responsive to a determination that data is available to write to the software bound ring buffer. The network adapter writes the data to memory referenced by the hardware write index, wherein memory referenced by the write index is offset according to an offset, and the memory contents comprise a data portion and a valid bit. The network adapter writes an epoch value of the write index to the valid bit. The network adapter increments the write index, responsive to writing the data to memory referenced by the write index. Further disclosed is method to access a hardware bound ring buffer.

Abstract: This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided.

Abstract: Methods, systems, and computer program products for implementing a validation framework for validating commands for configuring entities in a telecommunications network are disclosed. According to one aspect, the subject matter described herein includes a method for implementing a validation framework for validating commands for configuring entities in a telecommunications network. The method includes providing, to a first computing system, a validation configuration file containing at least one rule for validating, based on domain knowledge of a network entity, commands for configuring the network entity, wherein the validation configuration file is provided from a developer of the network entity. The first computing system receives data associated with a command for configuring the network entity, validates the received data using the at least one rule, and, responsive to validating the data, performs at least one action.

Abstract: Embodiments of the present invention provide a buffer manager and a buffer management method based on an address pointer linked list. In the embodiments, address pointers of all buffer blocks in a buffer are divided into several groups, lower bits of address pointers in each group are used to record a linked list between the address pointers in the same group, and an address pointer which is pointed by one predetermined address pointer of each group and is in a different group is further recorded to upbuild a linked list between the groups. Thereby, an address linked list can still be stored without a RAM with a width equal to a pointer depth and with a depth equal to the total number of buffer blocks in the buffer as required by the conventional art, which greatly reduces hardware resources required.

Abstract: The disclosure relates to accessing memory content with a high temporal locality of reference. An embodiment of the disclosure stores the content in a data buffer, determines that the content of the data buffer has a high temporal locality of reference, and accesses the data buffer for each operation targeting the content instead of a cache storing the content.

Abstract: Disclosed is an electronic device featuring a multi buffer scheme for processing incoming signals. For example, two buffers can be used. A processor can read and process stored signals from a first buffer while an incoming data module can concurrently store signals in a second buffer. Once, the processor is done, it can move on to the second buffer and process signals stored therein while the incoming data module stores signals in the first buffer. Also provided is a flagging scheme for allowing the processor and the incoming data module to control their respective access to the various buffers, so that only one of them accesses a single buffer at any time.

Abstract: An information processing device includes a processing unit which manages an association processing network formed by image processing devices. The processing unit includes a service evaluation content generating unit which acquires requirement performance information of a service to be stored from a service requirement performance managing unit and generates an evaluation content to be evaluated for the service by including the requirement performance information in an evaluation object, a service evaluation unit which evaluates the evaluation content of the service according to a predetermined requirement, and an association object managing unit which registers the service as a new association object the evaluation content of the service the predetermined requirement of which has been met by the evaluation of the service evaluation unit.

Abstract: A method and system for processing buffer status reports (BSRs) such that when BSR triggering is performed, the size(s) of the necessary sub-header(s) are also to be considered together in addition to the BSR size. The steps of checking whether any padding region is available in a MAC PDU that was constructed, comparing the number of padding bits with the size of the BSR plus its sub-header, and if the number of padding bits is larger than the size of the BSR plus its sub-header, triggering BSR are performed. Doing so allows the sub-header(s) to be inserted or included into the MAC PDU or transport block (TB) or other type of data unit.

Abstract: A panel adjustment method is executed on a host to adjust settings of a panel connected to the host through a serial bus. The method determines whether the panel is supported by the host. When the panel is supported by the host, the settings of the panel is read from a database of the host to accordingly set the panel. It is further determined whether the panel is correctly set or not. When the panel is correctly set, it is further determined whether the panel is of a frame buffer mode or not. When the panel is of a frame buffer mode, it is determined whether a header file generation is required or not. When the header file generation is required, the settings and a panel name are included in an include file. The include file is compiled to thereby generate a binary file which is loaded into the panel.

Abstract: A module for controlling integrity properties of a data stream input into a device, such as a machine for manufacturing or a management system related to such machines. A plurality of control items are registered in a database. At least one activable control means executes a control of one integrity property according to one of several registered control items. A list is attached to the database with selectable links for activating at least one of the control means. Configuration means perform on at least one of the links a chronological selection according to a predefined management profile on integrity properties of the data stream in order to introduce a selectable relative time delay between activations of control items. Due to that configuration, the integrity control thus obtained is provided with high reliability as well as in a very flexible manner.

Abstract: In a system-on-chip (SoC) including a processor, a method is provided for stashing packet information that prevents cache thrashing. In operation, an Ethernet subsystem accepts a plurality of packets and sends the packets to an external memory for storage. A packet descriptor is derived for each accepted packet and is added to an ingress queue. Packet descriptors are transferred from the ingress queue to an egress queue supplying the packet descriptors to a processor. A context manager monitors the fill level of packet descriptors in the egress queue. In response to monitoring the fill level, the context manager stashes packets from the external memory into a cache, where each stashed packet is associated with a packet descriptor in the egress queue. Packet descriptors are transferred from the ingress queue to the egress queue in response to a number of packet descriptors in the egress queue falling below the fill level.

Abstract: A communication control device includes a plurality of receive buffers each storing therein received information that corresponds to all or a part of a received message or an argument of a receive function, a hash-value generating unit that generates a hash value from a receive key contained in the received message in accordance with a hash-value generation rule, a storing unit that stores the received information in a selected one of the receive buffers corresponding to the hash value, and an output unit that outputs the received information from one of the receive buffers corresponding to the hash value in response to a transmission request from a receiving unit that performs a receiving operation by determining a matching based on a receive key specified by the receive function.

Abstract: There is provided an apparatus including a plurality of modules. Each module includes a storage unit configured to store a waiting ID and a specific ID of the module, a communication unit configured to transmit and receive packets to and from a bus, and a processing unit configured to process data of a packet which includes a valid flag indicating that the packet is valid, wherein the communication unit takes in data held by a packet which has an ID that coincides with the waiting ID, and stores the processed data in a packet which includes the valid flag indicating invalid and an ID coincident with the specific ID, and transmits the packet.