Abstract: A network device includes a main storage memory and a queue handling component. The main storage memory includes multiple memory banks which store a plurality of packets for multiple output queues. The queue handling component controls write operations to the multiple memory banks and controls read operations from the multiple memory banks, where the read operations for at least one of the multiple output queues alternates sequentially between the each of the multiple memory banks, and where the read operations and the write operations occur during a same clock period on different ones of the multiple memory banks.

Abstract: According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a peripheral interface and may not require a response. It may then be determined that an error is associated with the message, and an alert message may be sent from the upstream device to the downstream device via the peripheral interface.

Abstract: A method and apparatus are provided for controlling a translation lookaside buffer in connection with the execution of an atomic instruction. The method comprises identifying load instructions within a plurality of instructions to be executed, and placing the identified load instructions in a queue prior to execution. An atomic instruction identified in the queue is prevented from executing until the atomic instruction is the oldest instruction in the queue. The apparatus comprises a queue and a translation lookaside buffer. The queue is adapted to: identify an atomic instruction within a plurality of instructions to be executed; prevent execution of the atomic instruction until it is the oldest instruction in the queue; and send a virtual address corresponding to the atomic instruction and an atomic load signal in response to determining that the atomic instruction is the oldest instruction in the queue.

Abstract: A method, system, and computer program product for fast cancellation of an I/O request in a data processing system are provided in the illustrative embodiments. A first component in a stack comprising a plurality of components determines whether a memory buffer associated with the I/O request is valid, the memory buffer being an addressable area in a memory in the data processing system. The first component, responsive to the memory buffer being valid, creates a first request data structure corresponding to the I/O request, wherein the first request data structure includes a reference to the memory buffer. The first component passes the first request data structure to a second component in the stack.

Abstract: A method and system for facilitating communication between a host system and one or more hardware-based functional verification systems. The one or more hardware-based functional verification systems verify the functionality of electronic circuit designs. A controller switch comprises a host interface connecting to a host system, and a plurality of device ports. Each device port connects to a hardware emulator. The controller switch further comprises a plurality of direct memory access (DMA) engines and a plurality of execution units. An execution unit comprises an instruction cache and memory storing at least one DMA instruction and at least one address for performing a software instruction and a plurality of execution unit registers.

Abstract: Some of the embodiments of the present disclosure provide a method comprising managing a plurality of buffer addresses in a system-on-chip (SOC); and if a number of available buffer addresses in the SOC falls below a low threshold value, obtaining one or more buffer addresses from a memory, which is external to the SOC, to the SOC. Other embodiments are also described and claimed.

Abstract: A license issue system includes a user terminal and a license information issue server that are connected to a network. In the case in which there is a transfer source device in which license information issued by the license information issue server has been installed, and there is a transfer destination device that is to take over the license information installed in the transfer source device, the license issue system has the feature that the user terminal transmits, to the license information issue server, information regarding the transfer source device and the transfer destination device, and a license period during which the license can be used simultaneously in the transfer source device and the transfer destination device, and the license information issue server issues time-restricted license information to the transfer source device.

Abstract: A tape drive, tape drive recording system, and method are provided for improving tape speed selection during data transfer. The tape drive comprises a buffer, a tape for recording the data to be temporarily stored in the buffer, and a read head. The tape drive further comprises a reading controller that initially sets a tape speed such that a drive transfer rate matches a host transfer rate as closely as possible and that drives the tape at the tape speed. To address backhitching caused by one or more host transfer halts, the reading controller subsequently adjusts the tape speed such that the drive transfer rate is lower than the host transfer rate by recalculating the host transfer rate in consideration of the host transfer and the host transfer halt and setting the tape speed such that the drive transfer rate matches the recalculated host transfer rate as closely as possible.

Abstract: A data transfer device includes a data buffer, an odd number flag, and a control unit. The data buffer holds an even number of data blocks from a data transfer controller. The odd number flag is set when the number of data blocks to be transferred to a receiving device is odd. The control unit transfers an even number of data blocks to the receiving device for each data transfer cycle with respect to the receiving device, and transfers one data block to the receiving device in a last transfer cycle when the odd number flag is set. Thus, also when the data transfer controller which transfers data in a unit of an even number of data blocks is used, not only an even number of data blocks but an odd number of data blocks may be transferred to the receiving device.

Abstract: A computer implemented method for writing to a software bound ring buffer. A network adapter may determine that data is available to write to the software bound ring buffer. The network adapter determines that a read index is not equal to a write index, responsive to a determination that data is available to write to the software bound ring buffer. The network adapter writes the data to memory referenced by the hardware write index, wherein memory referenced by the write index is offset according to an offset, and the memory contents comprise a data portion and a valid bit. The network adapter writes an epoch value of the write index to the valid bit. The network adapter increments the write index, responsive to writing the data to memory referenced by the write index. Further disclosed is method to access a hardware bound ring buffer.

Abstract: Apparatus for processing data is provided comprising processing circuitry and monitoring circuitry for monitoring write transactions and performing transaction authorizations of certain transactions in dependence upon associated memory addresses. The processing circuitry is configured to enable execution of a write instruction corresponding to a write transaction to be monitored to continue to completion while the monitoring circuitry is performing monitoring of the write transactions and the monitoring circuitry is arranged to cause storage of write transaction data in an intermediate storage element for those transactions for which an authorization is required. Storage of write transaction data in an intermediate storage element enables the write transaction to be reissued in dependence upon the result of the transaction authorization although the corresponding write instruction has already completed.

Abstract: A method and system are provided for transferring data in a networked system between a local memory in a local system and a remote memory in a remote system. A RDMA request is received and a first buffer region is associated with a first transfer operation. The system determines whether a size of the first buffer region exceeds a maximum transfer size of the networked system. Portions of the second buffer region may be associated with the first transfer operation based on the determination of the size of the first buffer region. The system subsequently performs the first transfer operation.

Abstract: In one embodiment, a device is disclosed. For example, in one embodiment of the present invention, the device comprises a memory core having a shared buffer, and an arbitration logic module for receiving a destination ready signal from a processing source of a plurality of processing sources. The device also comprises at least one pipeline stage for storing at least one piece of data read from the shared buffer, and at least one matching pipeline stage storing at least one valid signal associated with the at least one piece of data read from the shared buffer. The device also comprises a counter for storing a value, wherein the value represents a number of pieces of data read from the shared buffer, but have not been delivered to the processing source.

Abstract: An interfacing circuit comprising a First In First Out (FIFO) memory for exchanging data between a “data producer device” and a “data consumer device”. The FIFO memory is controlled by first write control signals (WR, CLK_WR) and second read control signals (ENABLE, Clk_Rd). The interfacing circuit further includes: a redundancy filter (230) for receiving a sequence of N data (Y0, Y1, Y2 . . . Yn-1 ) to be stored within said FIFO, and for generating a redundancy control word representative of the presence of consecutive identical data within said sequence; means (250) for controlling said first and said second control signals of said FIFO for the purpose of preventing the storage into said FIFO of multiple consecutive identical data and more important to make possible to accelerate the average speed of the data flux going to the “data consumer device” without need to accelerate the clocking of the memory feeding the said FIFO thanks to increase of efficiency of transfers due to redundancy filtering.

Abstract: Architecture that allows programmatic association of devices to sessions and redirects input to the desired session. When the solution is active, input from the devices is not realized by the standard operating system input stack, thereby allowing even reserved key sequences such as Ctrl-Alt-Del to be intercepted and redirected to a desired session. Moreover, in addition to redirecting input to a specific session, the architecture facilitates the filtering of input from unwanted/unmapped devices, the interception and filtering or redirection of reserved key sequences such as Ctrl-Alt-Del, and the maintenance of input state for each session.

Abstract: Method and system for efficient buffer management for layer 2 through layer 5 network interface controller applications are provided. Aspects of the method may comprise determining whether an active NIC connection is an L2 type, an L4 type, or an L5 type. At least one buffer descriptor may be cached locally on a network interface controller (NIC) managed by a NIC application. The buffer descriptor is associated with the determined type of the active NIC connection. If the at least one active NIC connection is of the L2 or L4 type, the buffer descriptor may comprise at least one of a receive (RX) buffer descriptor and a transmit (TX) buffer descriptor. If the NIC connection is of the L5 type, the buffer descriptor may comprise at least one of a upper translation page table (TPT) entry and a lower TPT entry.

Abstract: Disclosed herein is an information processing apparatus that transfers information, using direct memory access (DMA), between a first storage section in an information processing system and a second storage section in an information transfer system. The information processing system includes the first storage section for storing the information, and a control section. The information transfer system includes: the second storage section for storing descriptor information indicating the location at which the information is stored in the first storage section and the size of the information; and a DMA transfer section for DMA transferring the information between the first storage section and the second storage section based on the descriptor information. The DMA transfer section DMA transfers the descriptor information concerning the DMA transferred information from the second storage section to the first storage section. The control section loads the descriptor information from the first storage section.

Abstract: Disclosed is a technique for flow control. It is detected that a work request is being transferred to an in-memory structure. A maximum limit is compared with a number of work requests stored in the in-memory structure. If the number of work requests stored in the in-memory structure equals the maximum limit, a notification is sent that indicates that additional work requests are not to be sent.

Abstract: A computer implemented method, data processing system, and computer program product for detecting circular buffer overflow. When an entry in the circular buffer is read, a valid mark bit in the entry is set to an inactive state and the location of the entry is stored as an entry previously processed. A valid mark bit of a next entry and the valid mark bit in the entry previously processed are read. Responsive to determining that the valid mark bit in the entry previously processed is in the inactive state and the valid mark bit in the next entry is in an active state, the next entry is read, the valid mark bit in the next entry is set to an incactive state, and the location of the next entry is stored as the entry previously processed. Responsive to determining that the valid mark bit in the entry previously processed is in the active state, a determination is made that a circular buffer overflow has occurred.

Abstract: A system and method for parallel scanning among multiple scanning entities. According to various embodiments of the present invention, buffers are allocated from a pool of memory pages, with one packet being located on each page. Each of the pages is mapped such that unprivileged scanners, privileged scanners, and hardware-based scanners are all capable of accessing the pages. By having the packets located on separate pages, additional data other than the packets at issue do not have to be shared, and copying is not necessary to complete the scanning process.

Abstract: In a frame transfer method and device by which an address space of a shared buffer can be effectively utilized without a reduction of the space even if an abnormal operation occurs in a management of the shared buffer, after frame data is written in the shared buffer during one monitor cycle when the frame data is to be read without fail from the shared buffer, an address space where the frame data has not been read from the shared buffer is detected during a next monitor cycle, and an address space where not a read but a write of the frame data has been performed at least during the monitor cycle is detected. In the next monitor cycle, the address space is released as a free address of the shared buffer.

Abstract: A data acquisition service on a network node is disclosed for forwarding received process data to a process history database over a potentially slow and/or intermittent network connection. A store and forward functionality within the networked node receives incoming process data via a first network interface and forwards outgoing process data via a second network interface. The disclosed store and forward functionality includes an immediate transmission cache and a store and forward storage. The store control enters, in response to detecting an entry condition, an activated mode wherein incoming process data is directed to the store and forward storage. A read control forwards outgoing process data to the second network interface from the immediate transmission cache and store and forward storage. The read control includes at least a first configurable parameter that constrains a rate at which data retrieved from the store and forward storage is forwarded via the second network interface.

Abstract: A method of verifying programming of an integrated circuit card includes transferring program data to a page buffer of a non-volatile memory, copying the program data to a buffer memory, calculating a first checksum value with respect to program data in the buffer memory, updating the program data in the buffer memory by copying the program data of the page buffer to the buffer memory, calculating a second checksum value with respect to updated program data in the buffer memory, comparing the first checksum value and the second checksum value, and determining, based on the comparison result, whether the program data of the page buffer is tampered.

Abstract: A system and method for sharing peripheral first-in-first-out (FIFO) resources is disclosed. In one embodiment, a system for utilizing peripheral FIFO resources includes a processor, a first peripheral FIFO controller and a second peripheral FIFO controller coupled to the processor for controlling buffering of first data and second data associated with the processor respectively. Further, the system includes a merge module coupled to the first peripheral FIFO controller and the second peripheral FIFO controller for merging a first FIFO channel associated with the first peripheral FIFO controller and a second FIFO channel associated with the second peripheral FIFO controller based on an operational state of the first FIFO channel and an operational state of the second FIFO channel respectively. Also, the system includes a first FIFO and a second FIFO coupled to the merge module via the first FIFO channel and the second FIFO channel respectively.

Abstract: According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a peripheral interface and may not require a response. It may then be determined that an error is associated with the message, and an alert message may be sent from the upstream device to the downstream device via the peripheral interface.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design, the design structure comprising for an interface system is disclosed. The system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock domain and the second clock domain; a write pointer that points to data written by the source; and a read pointer that points to data read by the destination. According to the design structure, the write pointer and the read pointer are utilized to enable the data to be transmitted from the first clock domain to the second clock domain asynchronously.

Abstract: A buffer management apparatus that sequentially receives L (L>1) types of data and transmits the L types of data to an external device, including: a reception unit that receives data; M (M<L) data storage units, each including a buffer area; an interval storage unit that, for each type of data, stores reception interval information; M timing units, that each time an elapsed time from a last storing of data in a corresponding data storage unit, and a control unit that, if all of the data storage units have been allocated, in particular, to different types of data, according to a judgment result based on the elapsed times and the reception interval information, either stores the received data in at least one of the data storage units in place of previously stored data, or transmits the received data to the external device.

Abstract: A computer implemented method for writing to a software bound ring buffer. A network adapter may determine that data is available to write to the software bound ring buffer. The network adapter determines that a read index is not equal to a write index, responsive to a determination that data is available to write to the software bound ring buffer. The network adapter writes the data to memory referenced by the hardware write index, wherein memory referenced by the write index is offset according to an offset, and the memory contents comprise a data portion and a valid bit. The network adapter writes an epoch value of the write index to the valid bit. The network adapter increments the write index, responsive to writing the data to memory referenced by the write index. Further disclosed is method to access a hardware bound ring buffer.

Abstract: A transaction elimination hardware unit 5 controls the writing to a frame buffer in a memory 2 of tiles generated by a tile-based graphics processor. The transaction elimination hardware unit 5 has a signature generator 20 that generates a signature representative of the content of the tile for each tile. A signature comparator 23 then compares the signature of a new tile received from the graphics processor with the signatures of one or more tiles already stored in the frame buffer to see if the signatures match. If the signatures do not match, then the signature comparator 23 controls a write controller 24 to write the new tile to the frame buffer. On the other hand, if the signatures match, then no data is written to the frame buffer and the existing tile is allowed to remain in the frame buffer. In this way, a tile is only written to the frame buffer if it is found by the signature comparison to differ from the tile or tiles that are already stored in the frame buffer that it is compared with.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one” or “zero” and indicates when the data buffer having the last bit is transmitted. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract: A method and apparatus to perform buffer management for media processing are described.

Abstract: Elements of the inventive development system include hardware and software objects. These objects can be instanced, ordered, parameterized, and connected in a software environment to implement different functions. Once in software, the description defines the topology and the properties of a set of objects and hence the overall function. These objects are hierarchically composed from a set of primitive objects. By using a piece of hardware that can model any primitive object set as pre-established encapsulated hardware objects, the topology and properties define a piece of hardware that can perform the desired, implemented, functions. Using embodiments of the invention, circuit designers can design hardware systems with little or no knowledge of hardware or hardware design, requiring only a high-level software description.

Abstract: A method and mechanism for managing requests to a resource. A request queue receives requests from multiple requestors and maintains a status for each requestor indicating how many requests the requestor has permission to issue. Upon initialization, the request queue allots to each requestor a predetermined number of “hard” entries, and a predetermined number of “free” entries. Un-allotted entries are part of a free pool of entries. If a requestor has an available entry, the requestor may submit a request to the request queue. After receiving a request, the request queue may allot a free pool entry to the requestor if the free pool currently has entries available. Upon de-allocation of a queue entry, if the entry corresponds to a hard entry, then the hard entry is re-allotted to the same requestor. If the entry is a free entry, the entry is made available and a free pool counter is incremented.

Abstract: Embodiments of the present invention provide a method and system for pulling network contents. The method includes: recording operation information of a network user; setting at least one of network service priority and user group priority for the network user according to the operation information of the network user; generating and storing a contents pulling strategy corresponding to at least one of the network service priority and the user group priority; when it is necessary to pull network contents for the network user, obtaining the contents pulling strategy corresponding to at least one of the network service priority and the user group priority of the network user, and pulling the network contents according to the contents pulling strategy. The system includes an operation information database, a priority generator, a contents-pulling-strategy generator and a network contents pulling agent.

Abstract: A multi-queue memory system is configured to operate in a packet mode. Each packet includes a SOP (start of packet) marker and an EOP (end of packet) marker. A packet status bit (PSB), is used to implement the packet mode. The packet status bit enables partial packet write and partial packet read operations, such that a queue switch can be performed in the middle of packet write or packet read operations. The packet status bit also enables data filtering to be performed between an activated EOP marker and a subsequently received SOP marker (i.e., between the end of one packet and the start of the next packet). Packet mark and re-write and packet mark and re-read operations are also enabled.

Abstract: A storage device includes a host interface, a buffer memory, a storage medium, and a controller. The host interface is configured to receive storage data and an invalidation command, where the invalidation command is indicative of invalid data among the storage data received by the host interface. The buffer memory is configured to temporarily store the storage data received by the host interface. The controller is configured to execute a transcribe operation in which the storage data temporarily stored in the buffer memory is selectively stored in the storage medium. Further, the controller is responsive to receipt of the invalidation command to execute a logging process when a memory capacity of the invalid data indicated by the invalidation command is equal to or greater than a reference capacity, and to execute an invalidation process when the memory capacity of the invalid data is less than the reference capacity.

Abstract: A system and method have been provided for pushing cacheable control messages to a processor. The method accepts a first control message, identified as cacheable and addressed to a processor, from a peripheral device. The first control message is allocated into a cache that is associated with the processor, but not associated with the peripheral device. In response to a read-prompt the processor reads the first control message directly from the cache. The read-prompt can be a hardware interrupt generated by the peripheral device referencing the first control message. For example, the peripheral may determine that the first control message has been allocated into the cache and generate a hardware interrupt associated with the first control message. Then, the processor reads the first control message in response to the hardware interrupt read-prompt. Alternately, the read-prompt can be the processor polling the cache for pending control messages.

Abstract: A method for providing a buffer status report in a mobile communication network is implemented between a base station and a user equipment. When data arrives to buffers of the user equipment and the priority of a logical channel for the data is higher than those of other logical channels for existing data in the buffers, a short buffer status report associated with the buffer of a logical channel group corresponding to the arrival data is triggered. The user equipment is based on obtained resources allocated by the base station to fill all data of the buffer of the logical channel group in a Protocol Data Unit. If all data of the buffer of the logical channel group corresponding to the arrival data can be completely filled in the Protocol Data Unit, the short buffer status report is canceled. Otherwise, the user equipment transmits the short buffer status report.

Abstract: Apparatus and circuitry are provided for supporting collection and/or verification of data integrity information. A circuitry in a storage controller is provided for creating and/or verifying a Data Integrity Block (“DIB”). The circuitry comprises a processor interface for coupling with the processor of the storage controller. The circuitry also comprises a memory interface for coupling with a cache memory of the storage controller. By reading a plurality of Data Integrity Fields (“DIFs”) from the cache memory through the memory interface based on information received from the processor, the DIB is created in that each DIF in the DIB corresponds to a respective data block.

Abstract: Certain embodiments of the invention may be found in a method and system for handling data in port bypass controllers for storage systems and may comprise receiving a data stream from a receive port bypass controller's port and buffering at least a portion of the received data stream in at least one EFIFO buffer integrated within the port bypass controller. A data rate or frequency of the received data stream may be changed by inserting at least one extended fill word in the buffered portion of the received data stream or by deleting at least one fill word from the received data stream buffered in the EFIFO buffer. The extended fill word may comprise a loop initialization primitive (LIP), a loop port bypass (LPB), a loop port enable (LPE), a not operation state (NOS), an offline state (OLS), a link reset response (LRR) and/or a link reset (LR).

Abstract: A communication system complying with SPI-4 Phase 2 standard includes a local device, an opposing device, a first data channel to transfer payload data from the local to the opposing device, a second data channel opposed to the first data channel, and a first status channel to be able to transfer data from the local to the opposing device. The local device periodically outputs buffer status information of a data buffer for storing payload data received over the second data channel to the first status channel. Further, the local device inserts the buffer status information between the payload data according to a priority of the buffer status information in order to output the buffer status information to the first data channel. The opposing device controls to output payload data to the second data channel according to the buffer status information received over the first status channel and the first data channel.

Abstract: Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.

Abstract: Method and apparatus for synchronizing a software buffer index with an unknown hardware buffer index. Specifically, a method of processing data is disclosed comprising synchronizing a software buffer index to a hardware buffer index. The method sequentially searches through a plurality of buffers containing data to find a second buffer with unprocessed data. The method is implemented when the software buffer index points to a first buffer containing processed data. Thereafter, the software buffer index is reset to the next available buffer having processed data following the second buffer.

Abstract: A method for verifying data in a storage system is disclosed. A host computer transmits area management data to a storage controller. The area management data specifies a range of a storage area in a storage device to be used by an application program having a mechanism for verifying data suitability. Upon receipt of an input/output request transmitted from the host computer, the storage controller performs verification, which is usually performed by the application program, of the data that is to be processed according to the data input/output request and to be input/output to/from the storage area, which is specified in accordance with the received area management data.

Abstract: Methods and systems are provided for reducing partial cache writes in transferring incoming data status entries from a peripheral device to a host. The methods comprise determining a lower limit on a number of available incoming data status entry positions in an incoming data status ring in the host system memory, and selectively transferring a current incoming data status entry to the host system memory using a full cache line write if the lower limit is greater than or equal to a first value. Peripheral systems are provided for providing an interface between a host computer and an external device or network, which comprise a descriptor management system adapted to determine a lower limit on a number of available incoming data status entry positions in an incoming data status ring in a host system memory, and to selectively transfer a current incoming data status entry to the host system memory using a full cache line write if the lower limit is greater than or equal to a first value.

Abstract: A method and system for processing out of order frames received by a host bus adapter is provided. The method includes, determining if a current frame is out of order; determining if a frame is within a range of transfer for an Exchange; and creating (or appending if not the first out-of-order frame) an out of order list if the current frame is a first out of order frame. The method also includes, determining if an entry in an out of order list has a relative offset value of zero; determining if at least one entry has a relative offset value equal to a total transfer length of an Exchange; and determining if every non-zero starting relative offset has a matching entry. The method also scans an out of order list and combines a last entry with an entry whose starting point matches the end point of the last entry.

Abstract: Embodiments of the present invention provide a media drive that is intended for reduction in power consumption required for serial communications to/from a host, and a power saving method thereof. In one embodiment, a HDD includes: a cache; a host interface for transferring, to a host, transfer data read out from the cache; a host interface manager that controls the execution of commands so as to generate a transfer unnecessary period during which a command and transfer data need not be exchanged with the host; and a MPU that brings a serial communication part of the host interface into a power save mode during the transfer unnecessary period. The host interface manager determines the optimum data transfer timing of transferring data from the cache to the host on the basis of a transfer rate at which data is transferred to the host, and a read rate at which data is read out from a disk into the cache.

Abstract: A portable memory device is provided that is capable of easy connection to a personal computer via a universal serial bus (USB) port, IEEE 1394 (i.e., firewire) or similar port. Included in the portable memory device is a compression/decompression engine capable of compressing and decompressing data. Data residing on a personal computer or other host platform is compressed by the engine and saved to the memory of the portable memory device. Compressed data is retrieved and decompressed by the engine and transmitted to the personal computer for use by the user. Embodiments of the present invention thus provide a highly convenient system and apparatus for users to access and save larger quantities of data to a relatively small device.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract: A semiconductor memory device includes a nonvolatile memory device having a plurality of physical sectors, and a memory controller configured to translate a logical address received from a host to a physical address, with reference to mapping data that defines a correspondence between the logical address and the physical address. The nonvolatile memory device is configured to access a first physical sector corresponding to the physical address, and, when a data delete command is provided from the host to the memory controller to delete first data that is stored in the first physical sector, the memory controller delays an erase and/or merge operation for the first physical sector in which the first data is stored.