Abstract: A data communication circuit buffers data between a shared resource and a plurality of data communication interfaces through a plurality of respective first-in-first-out ("FIFO") buffers. The data is divided into multiple-bit data frames having a start and an end. The circuit maintains a priority level for each FIFO buffer and initializes the priority level of each FIFO buffer to a first priority level. The circuit passes bits of the multiple-bit data frames from the shared resource to respective ones of the FIFO buffers in a buffer order which is based on the priority level of each FIFO buffer. The circuit passes the bits from the FIFO buffers to the respective data communication interfaces and selectively increases the priority level of each FIFO buffer to a second, higher priority level as a function of a level the bits within the FIFO buffer and whether the end of at least one data frame is stored in the FIFO buffer.

Abstract: A data processing apparatus runs a messaging and queuing software package whereby messages received at the data processing apparatus are stored in a message queue. The apparatus has: a processor; a high storage capacity storage device; and a low storage capacity storage device (e.g., a high-speed cache); the high storage capacity storage device stores full-length expiration data for each message in the message queue; and the low storage capacity storage device stores an abbreviated version of the full-length expiration data for each message in the message queue, the abbreviated version used to quickly and efficiently determine whether a queued message is expired.

Abstract: An input/output (I/O) buffer has a block-end detector which detects that an access has reached the last word in a block of the I/O buffer. If the block-end detector detects the last word of the block, then the block is invalidated. The I/O buffer also has a direct-memory-access-end detector which detects that an access has reached the last word in a direct-memory-access (DMA) transfer. If the DMA-end detector detects the last word of the DMA transfer, then the block is invalidated. The I/O buffer may also have a configuration memory which stores configuration information concerning whether a DMA controller accesses the input/output buffer instead of a storage. If the configuration information indicates that the DMA controller does not access the input/output buffer, then data from the storage are bypassed to the DMA controller.

Abstract: An address buffer that stores information used to access a data memory is disposed in a cache unit that supplies data such as an instruction code to an instruction executing unit. A tag memory and a data memory are independently accessed. The data memory is accessed corresponding to access information stored in the address buffer. Data is output from the data memory in the input order of data requests. When a data release signal is not received from the instruction executing unit, since access information is buffered in the address buffer, a large data buffer for storing the output data of the data memory is not required. In addition, in an associative type cache unit, the tag memory and the address buffer can be formed in the same memory.

Abstract: A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external registers which are connected to the processor over a data bus, address translation means, connected to the processor over the data bus and an address bus, for calculating, based on an index written to the data bus, an address associated with one of the memory locations, and transfer means, connected to the plurality of external registers, for transferring data between the addressed memory location and one of the external registers.

Abstract: A bridge circuit for coupling a first bus to a second bus includes a read buffer adapted to store read data and control logic. At least a portion of the read data includes prefetch data, and the read data is associated with a requesting device coupled to one of the first and second buses. The control logic is adapted to identify a write request having a target address on one of the first and second buses, flush at least a portion of the prefetch data in response to the target address corresponding to the requesting device, and transfer the write request to the requesting device independent of the read buffer. The write request is useful for signaling the requesting device that the read data is no longer required.

Abstract: A device interface for communicating between a processor system and a separate device employs cacheable control registers, both to indicate the receipt of a message and to receive messages to be transmitted. The data structure of the cacheable control registers may be that of a queue, minimizing the need for routine handshaking signals to clear the queue after each message. Communication of queue pointers is minimized by the use of a shadow pointer relied on as long as adequate queue space exists and queue entry valid flags which are interpreted with alternate sense for each cycling through the queue.

Abstract: A data processing apparatus serves as I/O units coupled to information processes apparatuses such as computers. The data processing apparatus decodes encrypted data and performs processing according to message data. The data processing apparatus includes a data processing circuit performing decoding processing and message processing according to message data, a data buffer accessible from both the data processing circuit and the information processing apparatus, a data buffer monitor circuit monitoring states of read/write of the data to the data buffer, and an access control circuit controlling an access from the information processing apparatus to the data buffer.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: In a multiprocessor data processing system including at least one main processor and one sub-processor utilizing a shared queue, queue integrity is maintained by associating a semaphore with each queue entry to indicate ownership of that queue entry. Ownership of a queue entry is checked by a processor attempting to post to the queue entry. Upon determining that the queue entry is available to the processor, the queue entry is loaded by an atomic write operation, ownership of the queue entry transferred to another processor, and the other processor may be alerted of the post to the queue. The other processor maintains ownership of the queue entry until the other processor has read and saved the data from the queue entry. Items may thus be posted to the queue and cleared from the queue by a processor independent of the state of the other processor.

Abstract: Buffers are provided in a computer system to allow posting data to the buffers, followed by concurrent operation by different portions of the computer system. A CPU buffer is provided to buffer CPU accesses, a CPU-to-PCI buffer is provided to buffer CPU accesses to the PCI local bus, and a memory buffer is provided to buffer CPU accesses to main memory. This configuration allows the CPU-to-PCI buffer to write data concurrently with the memory buffer accessing data from main memory.