Buffer Space Allocation Or Deallocation Patents (Class 710/56)
  • Patent number: 7685335
    Abstract: An enhanced fibre channel adapter with multiple queues for use by different server processors or partitions. For a non-partitioned server, the OS owns the adapter, controls the adapter queues, and updates the queue table(s). An OS operator can obtain information from the fibre channel network about the fibre channel storage data zones available to the physical fibre channel adapter port and can specify that one or more zones can be accessed by a specific processor or group of processors. The processor or group of processors is given an adapter queue to access the zone or zones of storage data. This queue is given a new World Wide Port Name or new N-Port ID Virtualization identifier, to differentiate this queue from another queue that might have access to a different storage data zone or zones. For a partitioned server, one partition owns the adapter, controls the adapter queues, and updates the queue table(s).
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Richard Louis Arndt, Patrick Allen Buckland, Harvey Gene Kiel, Renato John Recio, Jaya Srikrishnan
  • Patent number: 7676611
    Abstract: A method and system for processing out of order frames received by a host bus adapter is provided. The method includes, determining if a current frame is out of order; determining if a frame is within a range of transfer for an Exchange; and creating (or appending if not the first out-of-order frame) an out of order list if the current frame is a first out of order frame. The method also includes, determining if an entry in an out of order list has a relative offset value of zero; determining if at least one entry has a relative offset value equal to a total transfer length of an Exchange; and determining if every non-zero starting relative offset has a matching entry. The method also scans an out of order list and combines a last entry with an entry whose starting point matches the end point of the last entry.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: March 9, 2010
    Assignee: QLOGIC, Corporation
    Inventors: Ben K. Hui, Sanjaya Anand
  • Patent number: 7669028
    Abstract: Embodiments of the present invention optimize data bandwidth across an asynchronous buffer in a system with a variable clock domain. A move signal may be asserted to transfer data associated with a command into the asynchronous buffer. After the data has been moved into the buffer, an acknowledge signal may indicate that the transfer is complete. A launch signal may transfer the data in the asynchronous buffer to memory. Embodiments of the present invention allow the processing of a next command to begin at the earliest possible time while data associated with a previous command is being transferred into and out of the buffer, thereby increasing throughput and improving performance.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Mark D. Bellows, Brian M. McKevett, Tolga Ozguner
  • Publication number: 20100042762
    Abstract: A technique is disclosed for observing the data movement pattern in a peripheral device attached to a computer communications network data transmission switch, in order to arrive at a (statistical) determination of whether the peripheral device is being used as a “load intensive” device or as a “store intensive” device (or as neither type) over a defined time period. This determination is used to dynamically adjust (and re-allocate) the “outbound” and “inbound” buffer memory sizes assigned to a switch transmission port attached to the peripheral device, in cases where the device is operating in either “load intensive” or “store intensive” mode. The invention is applicable for use with all types of communications network switches (i.e. “Bridges”, “Hubs”, “Routers” etc.).
    Type: Application
    Filed: August 14, 2008
    Publication date: February 18, 2010
    Inventors: Anil Pothireddy, Jayashri Arsikere Basappa, Gopikrishnan Viswanadhan, Neranjen Ramalingam
  • Patent number: 7664893
    Abstract: Media drive control system and method. The media drive control system comprises a player console, a user operation filter, and a plurality of playback management devices. The player console provides an instant user operation (UOP) according to a received user command. The user operation filter comprises a queue and a management device. The queue receives and stores a plurality of UOPs, and outputs stored UOPs as control instructions on a first-in-first-out basis. The management device determines whether the queue is full. If the queue is full, the management device discards at least one of the stored UOPs prior to storing the instant UOP in the queue. Each playback management device receives control instructions for controlling corresponding playback devices.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: February 16, 2010
    Assignee: Via Technologies Inc.
    Inventor: King Huang
  • Patent number: 7664884
    Abstract: Embodiments of the present invention provide a media drive that is intended for reduction in power consumption required for serial communications to/from a host, and a power saving method thereof. In one embodiment, a HDD includes: a cache; a host interface for transferring, to a host, transfer data read out from the cache; a host interface manager that controls the execution of commands so as to generate a transfer unnecessary period during which a command and transfer data need not be exchanged with the host; and a MPU that brings a serial communication part of the host interface into a power save mode during the transfer unnecessary period. The host interface manager determines the optimum data transfer timing of transferring data from the cache to the host on the basis of a transfer rate at which data is transferred to the host, and a read rate at which data is read out from a disk into the cache.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: February 16, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Atsushi Kanamaru, Tadahisa Kawa, Hiromi Kobayashi, Hirofumi Saitoh
  • Patent number: 7653766
    Abstract: A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: January 26, 2010
    Inventor: Philip M. Adams
  • Publication number: 20100017548
    Abstract: A buffer management apparatus that sequentially receives L (L>1) types of data and transmits the L types of data to an external device, including: a reception unit that receives data; M (M<L) data storage units, each including a buffer area; an interval storage unit that, for each type of data, stores reception interval information; M timing units, that each time an elapsed time from a last storing of data in a corresponding data storage unit, and a control unit that, if all of the data storage units have been allocated, in particular, to different types of data, according to a judgment result based on the elapsed times and the reception interval information, either stores the received data in at least one of the data storage units in place of previously stored data, or transmits the received data to the external device.
    Type: Application
    Filed: November 27, 2008
    Publication date: January 21, 2010
    Inventors: Daisuke Iwahashi, Hideyuki Kanzaki
  • Publication number: 20100017542
    Abstract: A storage subsystem includes a variable-size write buffer that temporarily stores write data received from a host system. The storage subsystem is capable of adjusting the size of the write buffer so as to vary both the performance (e.g., sustained write speed) of the storage subsystem and a risk of data loss. In one embodiment, the storage subsystem implements a command set that enables the host system to directly control the size of the write buffer. The storage subsystem may additionally or alternatively be capable of adjusting the size of the write buffer based on monitored operating conditions, such as the temperature, the stability/consistency of a power signal received from the host system, and/or the elapsed time since the storage subsystem was last powered up.
    Type: Application
    Filed: September 24, 2009
    Publication date: January 21, 2010
    Applicant: SILICONSYSTEMS, INC.
    Inventors: David E. Merry, Jr., Mark S. Diggs
  • Patent number: 7647437
    Abstract: Systems, methods, and software products for moving and/or resizing a producer-consumer queue in memory without stopping all activity is provided so that no data is lost or accidentally duplicated during the move. There is a software consumer and a hardware producer, such as a host channel adapter.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: January 12, 2010
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Arndt, David F. Craddock, Ronald E. Fuhs, Thomas A. Gregg, Thomas Schlipf
  • Patent number: 7643493
    Abstract: An apparatus and method for scheduling within a switch is described. A set of input signals is received from input ports. The set of input signals is associated with a set of packets at the input ports. A request for each packet from the set of packets is generated based on the set of input signals. Each request has an input-port indicator, an output-port indicator and a service-level indicator. The packets are scheduled based on the service-level indicator.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: January 5, 2010
    Assignee: Altera Corporation
    Inventor: Kamran Sayrafian-Pour
  • Patent number: 7640381
    Abstract: An I/O decoupling system comprising an I/O accelerator coupled between a host interface and a channel interface, wherein the I/O accelerator comprises a host manager, a buffer manager a function manager, and a disk buffer. The host manager is coupled to the host interface to receive a request from a connected host computer. The function manager in response to receiving the request allocates the disk buffer and determines a threshold offset for the buffer while coordinating the movement of data to the disk buffer through the channel interface coupled to the disk buffer.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: December 29, 2009
    Inventors: Ji Zhang, Hain-Ching Liu, Jian Gang Ding
  • Patent number: 7634617
    Abstract: Disclosed are methods, systems, and computer program products for optimized copying of logical units (LUNs) in a redundant array of inexpensive disks (RAID) environment using buffers that are larger than delta map chunks. According to one method, a delta map is provided including delta indicators for tracking locations of changes to data stored in a plurality of source delta map chunks representing partitions of storage in physical disks of a redundant array of inexpensive disks (RAID) array. A first buffer of a buffer size larger than a delta map chunk size is provided. An amount of data is sequentially copied to fill the first buffer beginning at an address in the delta map chunk corresponding to a first change indicated by a delta indicator in the delta map.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: December 15, 2009
    Assignee: EMC Corporation
    Inventor: Pawan Misra
  • Patent number: 7634618
    Abstract: Disclosed are methods, systems, and computer program products for optimized copying of logical units (LUNs) in a redundant array of inexpensive disks (RAID) environment using buffers that are smaller than delta map chunks. According to one method, a delta map is provided including delta indicators for tracking locations of changes to data stored in a plurality of source delta map chunks representing partitions of storage in physical disks of a redundant array of inexpensive disks (RAID) array. A first buffer of a buffer size smaller than a delta map chunk size is provided. An amount of data is sequentially copied to fill the first buffer beginning at an address in the delta map chunk corresponding to a first change indicated by a delta indicator in the delta map.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: December 15, 2009
    Assignee: EMC Corporation
    Inventor: Pawan Misra
  • Patent number: 7630096
    Abstract: An image processing apparatus which reduces memory requirements of a printer and realizes high-speed printing is provided for a color image forming apparatus having a plurality of image forming units, transferring sequentially developed images in color to a recording medium, and forming a color image. In a host computer connected to a printer which has a plurality of image forming units, transfers sequentially developed images in color with overlapping timing to a recording medium, and forms a color image, the CPU converts document data into image data, and transfers the data in the order in which the data is printed in accordance with the delay among the image forming units.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: December 8, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoshiharu Ikegawa
  • Patent number: 7631122
    Abstract: One embodiment of the invention sets forth a method for performing a queue allocation operation that includes receiving a memory address associated with a queue allocation aperture, where the memory address is read by a client to request memory space in a memory queue for a payload, computing a payload size based on the memory address, determining an insertion pointer for the payload based on a first position of a horizon pointer, where the insertion pointer indicates a location within the memory queue for the client to insert the payload, adjusting the horizon pointer to a second position based on the payload size, and returning the insertion pointer to the client. Such an approach enables multiple clients to advantageously request and obtain space within a shared memory queue in a single atomic operation, thereby allowing clients to share a memory queue more efficiently relative to prior art approaches.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: December 8, 2009
    Assignee: NVIDIA Corporation
    Inventor: David Wyatt
  • Publication number: 20090300235
    Abstract: A method for allocation of a buffer memory with three buffers of a module having a processing unit and a bus connection is provided. The module sends or receives data via the bus connection and uses the processing unit to generate data for transmission via the bus connection and process data received via the bus connection. The bus connection and the processing unit function as a producer or consumer in a communication relationship established via the buffer memory. Each buffer assumes one of four statuses—“input area local”, “local”, “input area external” and “external”. Either the bus connection or the processing unit attempt to reserve one of the three buffers by a strategy: when one of the three buffers is already allocated, this buffer is used. Otherwise a buffer with the status “input area external” or “input area local” is used and the status “external” or “local” is assigned.
    Type: Application
    Filed: May 28, 2009
    Publication date: December 3, 2009
    Inventor: Karl Weber
  • Publication number: 20090300234
    Abstract: A buffer control method stores data to be written on a recording medium or data read from the recording medium to consecutive addresses within a storage region of a buffer, based on a sequential access command which instructs a continuous access to consecutive logical addresses of the recording medium, and variably sets a size of the storage region of the buffer depending on an unused region or a used region in the storage region of the buffer. The buffer is used as a buffer ring.
    Type: Application
    Filed: February 18, 2009
    Publication date: December 3, 2009
    Applicant: FUJITSU LIMITED
    Inventor: Tatsuya Haga
  • Patent number: 7624207
    Abstract: Data movement within a computing environment is at the very least reduced. Data is transmitted between a file system of the computing environment and a transmission medium of that environment. The transmission includes bypassing non-file system buffers in performing the transmission. For example, when data is sent to the file system to be written to one or more storage media, the file system swaps one or more buffers of the file system with the one or more buffers containing the data. The swapping does not require the copying of data. Further, for a read operation, the file system calls a routine, which is provided with one or more pointers to the data that is to be sent to a requester of the data.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: November 24, 2009
    Assignee: International Business Machines Corporation
    Inventor: Scott Thomas Marcotte
  • Patent number: 7620753
    Abstract: A reader and writer access a ring buffer without using a locking mechanism, thereby avoiding any delays attendant to using a locking mechanism when performing read operations to supply the reader with data from the ring buffer. Other measures are used to reduce delayed performance of read operations. If data requested by a reader is not available in the ring buffer, rather than waiting until the data becomes available, substitute data not from the ring buffer is provided instead. The ring buffer's size may be dynamically increased or decreased to improve performance of read and write operations and/or to conserve computer resources.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: November 17, 2009
    Assignee: Apple Inc.
    Inventors: Alexander B. Beaman, Daniel Steinberg
  • Patent number: 7617332
    Abstract: A method, apparatus and computer program product are provided for implementing packet command instructions for network processing. A set of packet commands is provided. Each packet command defines a corresponding packet operation. A command from the set of packet commands is issued to perform the defined corresponding packet operation. A packet buffer structure hardware is provided for performing one or more predefined packet manipulation functions responsive to the issued command.
    Type: Grant
    Filed: May 1, 2003
    Date of Patent: November 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Paul Allen Ganfield, Kent Harold Haselhorst, Kerry Christopher Imming, John David Irish
  • Patent number: 7617291
    Abstract: A method and system for handling received out-of-order network data using generic buffers for non-posting TCP applications is disclosed. When incoming out-of-order data is received and there is no application buffer posted, a TCP data placement may notify a TCP reassembler to terminate a current generic buffer, allocate a new current generic buffer, and DMA the incoming data into the new current generic buffer. The TCP data placement may notify the TCP reassembler the starting TCP sequence number and the length of the new current generic buffer. Moreover, the TCP data placement may add entries into a TCP out-of-order table when the incoming data creates a new disjoint area. The TCP data placement may adjust an existing disjoint area to reflect any updates. When a TCP application allocates or posts a buffer, then the TCP reassembler may copy data from a linked list of generic buffers into posted buffers.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: November 10, 2009
    Assignee: Broadcom Corporation
    Inventors: Kan Frankie Fan, Scott McDaniel
  • Patent number: 7613109
    Abstract: A method and apparatus for processing data received and transmitted on a TCP connection is described. An offload unit processes received data for which a special case does not exist, to produce payload data, which is uploaded directly to application memory. The offload unit partially processes received data for which a special case does exist and uploads the partially processed received data to a buffer stored in system memory. The partially processed received data is then further processed by a TCP stack to produce payload data, which is copied to application memory.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: November 3, 2009
    Assignee: NVIDIA Corporation
    Inventors: Ashutosh K. Jha, Radoslav Danilak, Paul J. Gyugyi, Thomas A. Maufer, Sameer Nanda, Anand Rajagopalan, Paul J. Sidenblad
  • Patent number: 7613848
    Abstract: Disclosed are a method, upstream processing node, and computer readable medium for dynamically stabilizing a stream processing system. The method includes receiving at least one computing resource allocation target. The method further includes determining that an input data flow rate of at least one upstream processing element varies. The computing resource is dynamically allocated to the upstream processing element in response to the input rate of the upstream processing element varying. Data flow is dynamically controlled between the upstream processing element and at least one downstream processing element.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: November 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Lisa D. Amini, Anshul Sehgal, Jeremy I. Silber, Olivier Verscheure
  • Patent number: 7613199
    Abstract: A system permits queues to use more than an allocated amount of bandwidth. The system allocates an amount of bandwidth to each of the queues and determines whether any of the queues is using less than the allocated amount of bandwidth. If so, the system reallocates the allocated bandwidth from one of the queues to at least one other one of the queues based on the amount of bandwidth used by each of the queues.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: November 3, 2009
    Assignee: Juniper Networks, Inc.
    Inventors: Pradeep Sindhu, Debashis Basu, Jayabharat Boddu, Avanindra Godbole
  • Patent number: 7610415
    Abstract: A system and method of transferring characters from a first device through a buffer memory to a second device. A descriptor is read and a buffer address and a buffer length are extracted from the descriptor, wherein the buffer address and buffer length define a buffer of data stored in the first device. The data stored in the buffer is transferred from the buffer to the buffer memory, and from there to the second device. A check is made to determine if the descriptor should be closed and, if the descriptor should be closed, an indication is made that the descriptor is closed.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: October 27, 2009
    Assignee: Digi International
    Inventors: Mark H Wickham, Travis Lubbers, Brad Jacula
  • Patent number: 7603488
    Abstract: Systems and methods for providing efficient memory allocation, reduced processor intervention and power consumption, and increased memory access bandwidth. One embodiment comprises a system including a plurality of memory units which are accessible in parallel, a dynamic memory unit configured to dynamically allocate and deallocate storage space in the memory units, and a plurality of direct memory access (DMA) engines configured to access the memory units in parallel through the memory management subsystem. The system may be implemented in the MAC engine of a device that communicates with other devices via a wireless communication link. This embodiment may store packets in FIFOs within the memory units as elements of linked list data structures that can be joined together without having to move the previously stored data. DMA engines access a context table to obtain DMA channel information that enables them to move data through appropriate DMA channels.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: October 13, 2009
    Assignee: Alereon, Inc.
    Inventors: Martin Gravenstein, Nirmalendu B. Patra, Andrew Probst, Dave Ohmann, Clair A. Hardesty
  • Patent number: 7603026
    Abstract: This invention provides an information processing method and apparatus, which can set all extent sizes of data divisionally recorded on a disk to be equal to or larger than the minimum recording unit, and can guarantee continuous reproduction of the divisionally recorded data. Of data divisionally recorded on a recording medium (5), data which corresponds to an end portion of that data and cannot be recorded as a recording area equal to or larger than a minimum recording unit specified in the recording medium (5) due to the presence of a recording area (6) of another data, that has already been recorded on the recording medium (5), is re-recorded on a recording area equal to or larger than the minimum recording unit. At this time, new data is generated by combining data less than the minimum recording unit, and data recorded in another recording area, and the new data is re-recorded on a new recording area.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: October 13, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Ikuo Watanabe
  • Patent number: 7603495
    Abstract: This invention relates to a method and system for changing an output rate of information for a buffer (3) with a constant first output rate (R1) which receives output data from a data source (2a), where the method step comprises; halting the reception of output data from the data source (2a); outputting (4) the stored output data of the buffer (3) at the first output rate (R1) until said buffer is empty, and resuming receiving and storing of output data in the buffer (3); setting a second constant output rate (R2) as the output rate of the buffer; and commencing/starting output of the content of the buffer at the second output rate (R2) when the amount of buffered data is equal to the second constant output rate (R2) times a requested buffer-time (TB2).
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: October 13, 2009
    Assignee: IPG Electronics 503 Limited
    Inventors: Antonie Dijkhof, Maarten Alexander Ghijsen, Simon Tony Dekker
  • Patent number: 7603429
    Abstract: A network interface adapter includes a network interface and a client interface, for coupling to a client device so as to receive from the client device work requests to send messages over the network using a plurality of transport service instances. Message processing circuitry, coupled between the network interface and the client interface, includes an execution unit, which generates the messages in response to the work requests and passes the messages to the network interface to be sent over the network. A memory stores records of the messages that have been generated by the execution unit in respective lists according to the transport service instances with which the messages are associated. A completion unit receives the records from the memory and, responsive thereto, reports to the client device upon completion of the messages.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: October 13, 2009
    Assignee: Mellanox Technologies Ltd.
    Inventors: Michael Kagan, Dieo Crupnicoff, Gilad Shainer, Ariel Shahar
  • Patent number: 7599753
    Abstract: Systems and methods for processing data from priority-based operating system threads within a realtime component are described. The component submits blank buffers to hardware. The component receives data from priority based operating system threads and processes and writes the data from within an independent second real-time thread to buffers before the buffers into which the data is written are used by the hardware. Hardware buffers are created offset from memory page boundaries such that the least significant bits of any memory address referencing the start of the buffer uniquely identify it and can be used as an index into a circular buffer queue to determine which buffer is currently being processed. Data is always processed and written into a buffer that is a predetermined range of buffers in front of the buffer currently being processed by the hardware.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: October 6, 2009
    Assignee: Microsoft Corporation
    Inventors: Jeffrey Eames Taylor, Joseph C. Ballantyne, Shanmugam Mohanraj
  • Publication number: 20090248922
    Abstract: A memory buffer allocation device for allocating a memory buffer in a virtual computer system in which a plurality of virtual operating systems operate in time-sharing on one CPU having the memory buffer, includes a memory buffer division unit which divides the memory buffer into a number (n) of areas and reserves a division unit number (m) of areas out of the n areas as a dedicated memory buffer and the other areas except for the number n of the areas as a shared memory buffer. The device also includes a memory buffer allocation unit which allocates each area of the dedicated memory buffer to a number m of domains and each area of the shared memory buffer to other n-m domains except for the number m of domains, wherein the domains are of the virtual operating systems that are operating in the virtual computer system.
    Type: Application
    Filed: March 31, 2009
    Publication date: October 1, 2009
    Applicant: FUJIFILM LIMITED
    Inventors: Hisashi HINOHARA, Shigenobu ONO
  • Patent number: 7596643
    Abstract: A storage subsystem includes a variable-size write buffer that temporarily stores write data received from a host system. The storage subsystem is capable of adjusting the size of the write buffer so as to vary both the performance (e.g., sustained write speed) of the storage subsystem and a risk of data loss. In one embodiment, the storage subsystem implements a command set that enables the host system to directly control the size of the write buffer. The storage subsystem may additionally or alternatively be capable of adjusting the size of the write buffer based on monitored operating conditions, such as the temperature, the stability/consistency of a power signal received from the host system, and/or the elapsed time since the storage subsystem was last powered up.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: September 29, 2009
    Assignee: Siliconsystems, Inc.
    Inventors: David E. Merry, Jr., Mark S. Diggs
  • Publication number: 20090240851
    Abstract: A USB controller according to one aspect of the present invention is a USB controller incorporated in a USB device, the USB controller including a RAM that stores data transferred through a USB port or a CPU bus, and a register that holds a setting for determining to which one of a region for host used for a host function and a region for peripheral used for a peripheral function a part of the RAM is allocated.
    Type: Application
    Filed: March 12, 2009
    Publication date: September 24, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Shinya Saito
  • Patent number: 7594023
    Abstract: Data objects are sent using a data carousel and forward error correction. This involves segregating a file into groups, wherein each group represents k data blocks. From the k data blocks of each group, n erasure-encoded blocks are calculated, where n>k. The n erasure-encoded blocks are sent in a round-robin fashion using IP multicast technology: the first erasure-encoded block for each group, then the second block of each group, and so on. At a receiver, the blocks are stored on disk as they are received. However, they are segregated by group as they are stored. When reception is complete, each group is read into RAM, decoded, and written back to disk. In another embodiment, the receiver segregates allocated disk space into areas corresponding to sets of groups. Received blocks are then segregated only by set as they are written to disk. One or more RAM buffers can be used in this embodiment. When reception is complete, each set is read into RAM, decoded, and then written back to disk.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: September 22, 2009
    Assignee: Microsoft Corporation
    Inventor: David James Gemmell
  • Patent number: 7594048
    Abstract: Measuring transit time across an asynchronous first-in-first-out (FIFO) memory can include sampling an indication of a value of a read pointer of the FIFO memory at a sampling frequency that exceeds a frequency of a read clock and a write clock of the FIFO memory. An indication of a value of a write pointer of the FIFO memory can be sampled at the sampling frequency. For each sampling period, a measure of occupancy of the FIFO memory can be calculated according to a sampled pair including the indication of the value of the read pointer and the indication of the value of the write pointer. The measure of occupancy can be averaged over a predetermined number of cycles of the sampling frequency. The averaged measure of occupancy can be output as an indication of transit time across the FIFO memory.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: September 22, 2009
    Assignee: Xilinx, Inc.
    Inventors: Gareth David Edwards, David Finlay Taylor, Duncan Andrew Cockburn, Douglas Michael Grant, Stuart Alan Nisbet
  • Publication number: 20090234989
    Abstract: A memory system for an I/O controller which includes a memory with multiple memory blocks, a supply voltage control circuit providing power to each memory block, and control logic. Each memory block retains stored information with reduced power consumption when receiving a reduced voltage level. The control logic allocates buffers in the memory and controls the supply voltage control circuit to provide the full voltage level to at least one memory block of at least one allocated buffer and to provide the reduced voltage level to remaining memory blocks. Each memory block includes one or more buffers. In various embodiments the control logic fully powers each memory block of a buffer or less than all of the memory blocks. A linked buffer structure may be used to reduce the memory blocks of an allocated buffer receiving full power, such as only one memory block in the buffer.
    Type: Application
    Filed: March 11, 2008
    Publication date: September 17, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Michael A. Fischer
  • Patent number: 7590778
    Abstract: Provided are a method, system, and article of manufacture for using operation codes to control a decoder's use of a buffer to generate data from an input data stream into an output data stream. An encoder generates an input data stream for a decoder comprising at least one operation code and compressed data for an output device. The at least one operation code instructs the decoder on how to use a buffer when processing the input data stream. The decoder receives the input data stream, processes the data in the input data stream to perform an operation with respect to the buffer according to the at least one operation code, and decodes the compressed data into decompressed data to send to an output data stream to the output device.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: September 15, 2009
    Assignee: International Business Machines Corporation
    Inventors: Steven G. Ludwig, Joan La Verne Mitchell
  • Patent number: 7590152
    Abstract: A system for monitoring EF-on-EF jitter in a network node having an EP output queue into which EF packets are entered comprises a first counter that counts the packets entering the queue and also a second counter that counts the packets entering the queue when the queue depth is greater than an operator-determined maximum depth, whereby the operator can compare the two counts to determine the proportion of packets that might be subject to jitter corresponding to the maximum depth. Preferably, the system also includes a third counter that counts the number of packets entering the queue when the queue depth exceeds an alarm depth greater than the maximum depth.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: September 15, 2009
    Assignee: Cisco Technology, Inc.
    Inventor: Clarence Filsfils
  • Patent number: 7590764
    Abstract: A system for dynamically allocating buffers between components in a computer system is described. The system uses matched sets of bi-directional buffers to control data flow between the processor and the computer bus. The dynamic buffer allocation system allows simultaneous data transfer from the processor to the buffers, and from the buffers to the computer bus.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: September 15, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Jeffrey Jay Rooney
  • Publication number: 20090228619
    Abstract: A dynamic A-MSDU enabling method is disclosed. The method enables the recipient of an aggregate MAC service data unit (A-MSDU) under a block ACK agreement to reject the A-MSDU. The method thus distinguishes between A-MSDU outside of the block ACK agreement, which is mandatory, from A-MSDU under the block ACK agreement, which is optional. The method thus complies with the 802.11n specification while enabling the recipient to intelligently allocate memory during block ACK operations.
    Type: Application
    Filed: May 12, 2009
    Publication date: September 10, 2009
    Inventor: Solomon Trainin
  • Patent number: 7587521
    Abstract: According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel and assigns the request to access one of two or more independently addressable subchannels within the channel. The transaction assembler combines the request with one or more additional requests to access the two or more independently addressable subchannels within the channel and facilitates a speculative return of data from a subchannel for which a subchannel request is not available.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: September 8, 2009
    Assignee: Intel Corporation
    Inventors: James Akiyama, William H. Clifford
  • Patent number: 7584472
    Abstract: A method and apparatus for processing call signaling messages during burst overloading and sustained overloading of a communications switch include processing that begins by receiving a plurality of call signaling messages, which may be call set-up messages, connect messages, call proceeding messages, call release messages, release complete messages, and/or link layer information. The processing then continues by comparing a queue occupancy level of a call processing queue with a first queue occupancy threshold. If the queue occupancy level compares unfavorably with the first queue occupancy threshold (e.g., the queue is storing more messages than desired), call signaling messages are enqueued into the call processing queue based on the types of the call signaling messages. For example, dispensable call signaling messages are enqueued in a LIFO manner while indispensable and essential messages are enqueued in a FIFO manner.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: September 1, 2009
    Assignee: Alcatel-Lucent Canada Inc.
    Inventors: James S. McCormick, David Furshpan, Jonathan Bosloy, John Burns, Shawn McAllister
  • Patent number: 7581072
    Abstract: A data buffer device that includes a write unit and a read unit, and is disposed between a first interface device and a second interface device is provided. The write unit further includes a first write buffer, a second write buffer and a write controller. The write controller controls the first write buffer and the second write buffer to receive and transmit data from the first interface device to the second interface device alternatively according to the requests of the first interface device and the second interface device. The read unit further includes a first read controller, a first read buffer and a second read buffer. The read controller controls the first read buffer and the second read buffer to receive and transmit data from the second interface device to the first interface device alternatively according to the requests of the first interface device and the second interface device.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: August 25, 2009
    Assignee: Via Technologies, Inc.
    Inventors: Wen-Chung Tsai, Jung-Tsan Hsu
  • Patent number: 7581043
    Abstract: A method and disc drive are disclosed that employ dynamic buffer size allocation for handling multiple data streams, such as time-sensitive audio/video data. The method involves allocating a certain amount of required buffer space for each data stream to be handled without an interruption in recording or playing back the data stream. The method further involves reallocating the amount of required buffer space for each stream including any additional stream when one or more additional streams are to be added to the total number of streams being handled. The method also involves reallocating the amount of required buffer space for each stream including those streams that remain after any of the data streams being handled are terminated.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: August 25, 2009
    Assignee: Seagate Technology LLC
    Inventor: Robert W. Dixon
  • Publication number: 20090210587
    Abstract: A method and system for implementing store buffer allocation for variable length store data operations are provided. The method includes receiving a store address request and at least one store data request and stepping through data operations for each of the store data requests and an address range for the store data requests to determine alignment and data steering information used to select a storage buffer destination for the data in the store data requests. The method further includes determining availability of the storage buffer by maintaining a reservation list for each storage buffer, maintaining a count of the number of available entries for each storage buffer, updating the reservation list to reflect a reservation acceptance for designated available entries, and clearing entries upon completion of the processing of store data operations. The method also includes reserving the selected storage buffer when the number of available entries meets or exceeds the number of entries required for the data.
    Type: Application
    Filed: February 15, 2008
    Publication date: August 20, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian D. Barrick, Vimal M. Kapadia, Chung-Lung Kevin Shum, Aaron Tsai
  • Patent number: 7574539
    Abstract: A dynamic A-MSDU enabling method is disclosed. The method enables the recipient of an aggregate MAC service data unit (A-MSDU) under a block ACK agreement to reject the A-MSDU. The method thus distinguishes between A-MSDU outside of the block ACK agreement, which is mandatory, from A-MSDU under the block ACK agreement, which is optional. The method thus complies with the 802.11n specification while enabling the recipient to intelligently allocate memory during block ACK operations.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: August 11, 2009
    Assignee: Intel Corporation
    Inventor: Solomon Trainin
  • Patent number: 7567508
    Abstract: A method and system for providing delay bound and prioritized packet dropping are disclosed. The system limits the size of a queue configured to deliver packets in FIFO order by a threshold based on a specified delay bound. Received packets are queued if the threshold is not exceeded. If the threshold is exceeded, a packet having a precedence level less than that of the precedence level of the received packet is dropped. If all packets in the queue have a precedence level greater than that of the packet received, then the received packet is dropped if the threshold is exceeded.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: July 28, 2009
    Assignee: Cisco Technology, Inc.
    Inventors: Anna Charny, Christopher Kappler, Sandeep Bajaj, Earl T. Cohen
  • Publication number: 20090187681
    Abstract: The invention provides a new linked structure for a buffer controller and management method thereof. The allocation and release actions of buffer memory can be more effectively processed when the buffer controller processes data packets. The linked structure enables the link node of the first buffer register to point to the last buffer register. The link node of the last buffer register points to the second buffer register. Each of the link nodes of the rest buffers points to the next buffer register in order until the last buffer register. This structure can effectively release the buffer registers in the used linked list to a free list.
    Type: Application
    Filed: April 1, 2009
    Publication date: July 23, 2009
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Murphy Chen, Perlman Hu
  • Patent number: 7565462
    Abstract: A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer field points to one of the DMA command lists. The sequence field holds a sequence value. A DMA engine accesses an entry in the command queue and then accesses the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry. The DMA engine performs the DMA operations specified by the accessed DMA commands. The DMA engine makes available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed. In one embodiment, the command queue is part of the DMA engine.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: July 21, 2009
    Assignee: Broadcom Corporation
    Inventor: Alexander G. MacInnis