Abstract: Systems and methods are described including dynamically configuring a shared buffer to support processing of at least two video read streams associated with different video codec formats. The methods may include determining a buffer write address within the shared buffer in response to a memory request associated with one read stream, and determining a different buffer write address within the shared buffer in response to a memory request associated with the other read stream.

Abstract: A method for allocating resources of a host channel adapter includes the host channel adapter identifying an underlying function referenced in the first resource allocation request received from a virtual machine manager, determining that the first resource allocation request specifies a number of physical collect buffers (PCBs) allocated to the underlying function, allocating the number of PCBs to the underlying function, determining that the first resource allocation request specifies a number of virtual collect buffers (VCBs) allocated to the underlying function, and allocating the number of VCBs to the underlying function. The host channel adapter further receives command data for a command from the single virtual machine, determines that the underlying function has in use at least the number of PCBs when the command data is received, and drops the command data in the first command based on the underlying function having in use at least the number of PCBs.

Abstract: A buffer pool for a database application is maintained in a volatile main memory component. A control portion that corresponds to a block of application data residing on a non-volatile, asymmetric memory component and that includes a reference to a location of the block of application data on the non-volatile, asymmetric memory component is added to the buffer pool maintained in the volatile main memory component. The control portion from the buffer pool maintained in the volatile main memory component that corresponds to the block of application data is accessed and the location of the block of application data on the non-volatile, asymmetric memory component is identified. Based on identifying the location of the block of application data on the non-volatile, asymmetric memory component, the database application is enabled to access the block of application data directly from the non-volatile, asymmetric memory component.

Abstract: A method and system for processing buffer status reports (BSRs) such that when BSR triggering is performed, the size(s) of the necessary sub-header(s) are also to be considered together in addition to the BSR size. The steps of checking whether any padding region is available in a MAC PDU that was constructed, comparing the number of padding bits with the size of the BSR plus its sub-header, and if the number of padding bits is larger than the size of the BSR plus its sub-header, triggering BSR are performed. Doing so allows the sub-header(s) to be inserted or included into the MAC PDU or transport block (TB) or other type of data unit.

Abstract: According to one embodiment, a command management device includes a command buffer, a free address register and a FIFO unit with entries. The command buffer stores commands received from a host. The entries include address sections configured to store addresses of the areas in the command buffer in which the respective commands are stored. The address sections are connected together like a ring. Each of the address sections includes a substitute module configured to substitute either the free address held in the free address register or a second address stored in the address section preceding the each of the address sections for a first address stored in the each of the address sections.

Abstract: The present invention provides techniques for managing ownership (i.e., control) of one or more memory buffer (mbuf) data structures within a network subsystem and a storage subsystem of a storage operating system implemented in a storage system. When the storage system receives data to be written to a storage medium, the network subsystem stores the received data in one or more variable-length chains of mbufs. Unlike conventional approaches, the received data is not subsequently copied out of the mbufs into fixed-sized data buffers for use by the storage subsystem. Instead, the storage subsystem can directly manipulate the received data stored in the mbufs. By eliminating the steps of copying data out of the mbufs and into fixed-sized data buffers, the invention reduces the amount of time and system resources consumed by the storage system when writing blocks of received data to disk storage.

Abstract: A method, system and apparatus for autonomic buffer configuration. In accordance with the present invention, an autonomic buffer configuration method can include monitoring data flowing through buffers in a communications system and recording in at least one buffer profile different data sizes for different ones of the data flowing through the buffers during an established interval of time. An optimal buffer size can be computed based upon a specification of a required percentage of times a buffer must be able to accommodate data of a particular size. Subsequently, at least one of the buffers can be re-sized without re-initializing the at least one resized buffer.

Abstract: Various embodiments include fault tolerant memory apparatus, methods, and systems, including a memory manager for supplying read and write requests to a memory device having a plurality of addressable memory locations. The memory manager includes a plurality of banks. Each bank includes a bank queue for storing read and write requests. The memory manager also includes a request arbiter connected to the plurality of banks. The request arbiter removes read and write requests from the bank queues for presentation to the memory device. The request arbiter includes a read phase of operation and a write phase of operation, wherein the request arbiter preferentially selects read requests for servicing during the read phase of operation and preferentially selects write requests for servicing during the write phase of operation.

Abstract: An apparatus and method for scheduling within a switch is described. A set of input signals is received from input ports. The set of input signals is associated with a set of packets at the input ports. A request for each packet from the set of packets is generated based on the set of input signals. Each request has an input-port indicator, an output-port indicator and a service-level indicator. The packets are scheduled based on the service-level indicator.

Abstract: A method of transmitting information about a buffer size includes transmitting a bit string comprising a first bit string and a second bit string when the buffer size is greater than or equal to a first value, the first bit string indicating a quotient which is acquired by dividing the buffer size by a second value, and the second bit string indicating a value corresponding to a remainder which is acquired by dividing the buffer size by the second value.

Abstract: Techniques are described which simplify and/or automate many of the tasks associated with the configuration, deployment, and management of network resources to support cloud-based services.

Abstract: Methods and apparatus for enhancing efficiency (e.g., reducing power consumption and bus activity) in a data bus. In an exemplary embodiment, methods and apparatus for intelligently trimming (and adding or re-adding) queue heads resident in a host device associated with various client device processes are disclosed. By selectively trimming inactive or dormant queue heads, the host expends less resources and time polling the queue heads during routine operations. Similarly, queue heads which are newly active, or acquired are intelligently added to ensure proper bus operation. Inactive queue heads are brought back into the polling process only when requested, thereby keeping the list of queue heads to be polled or examined as short as possible at all times.

Abstract: Systems and techniques include, in some implementations, a computer implemented method storing a portion of data elements present in a first buffer in a second buffer in response to detecting an overflow condition of the first buffer, wherein the data elements in the first buffer are sorted according to a predetermined order, and inserting a proxy data element in the first buffer to represent the portion of data elements stored to the second buffer.

Abstract: Disclosed are systems and methods for reclaiming posted buffers during a direct memory access (DMA) operation executed by an input/output device (I/O device) in connection with data transfer across a network. During the data transfer, the I/O device may cancel a buffer provided by a device driver thereby relinquishing ownership of the buffer. A condition for the I/O device relinquishing ownership of a buffer may be provided by a distance vector that may be associated with the buffer. The distance vector may specify a maximum allowable distance between the buffer and a buffer that is currently fetched by the I/O device. Alternatively, a condition for the I/O device relinquishing ownership of a buffer may be provided by a timer. The timer may specify a maximum time that the I/O device may maintain ownership of a particular buffer. In other implementations, a mechanism is provided to force the I/O device to relinquish some or all of the buffers that it controls.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal from the input-output device, outputs a result of the control operation to a process, and has a timer unit to be excited at a constant period; and the software part has an information process part, a control process part, and an interrupt control unit to switch over the information process part and control process part one another, in which the interrupt control unit suspends an execution of the information process part to execute the control process part in priority and resume the information process part by switching over to the information process part from the control process part, when the execution of the control process part is terminated.

Abstract: Some of the embodiments of the present disclosure provide a method comprising managing a plurality of buffer addresses in a system-on-chip (SOC); and if a number of available buffer addresses in the SOC falls below a low threshold value, obtaining one or more buffer addresses from a memory, which is external to the SOC, to the SOC. Other embodiments are also described and claimed.

Abstract: A space switch includes a buffer having a plurality of serial inputs, a plurality of de-serializers, each coupled to a respective input, a plurality n of buffers and a media access controller having inputs coupled to the plurality of de-serializers, data outputs coupled to the buffers, and two control outputs coupled to respective buffers for buffering input data at a clock rate one-nth that of the input data and a switch fabric connected to the buffers for matching buffer data throughput with switch data throughput. Preferably the buffer is a bifurcate buffer. This space switch described ensures matching of buffer and switch fabric throughput.

Abstract: An efficient low latency buffer, and method of operation, is described. The efficient low latency buffer may be used as a bi-directional memory buffer in an audio playback device to buffer both output and input data. An application processor coupled to the bi-directional memory buffer is responsive to an indication to write data to the bi-directional memory buffer reads a defined size of input data from the bi-directional memory buffer. The input data read from the bi-directional memory buffer is replaced with output data of the defined size. In response to a mode-change signal, the defined size of data is changed that is read and written from and to the bi-directional memory buffer. The buffer may allow the application processor to enter a low-powered sleep mode more frequently.

Abstract: Techniques are described for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information is stored in coalescing memory buffers. To this end, the write operations may be reduced, utilizing the difference information.

Abstract: In one embodiment, a data storage device comprises a buffer, a buffer manager, and a buffer client. The buffer client is configured to receive data to be stored in the buffer, to compute a difference between a bank boundary address of the buffer and a starting buffer address for the data, to generate a first data burst having a length equal to the computed difference and including a first portion of the data, and to send the first data burst to the buffer manager, wherein the buffer manager is configured to write the first data burst to the buffer.

Abstract: A method for communicating between devices in a network includes creating an I/O tunnel between a first device and a second device through the network. The I/O tunnel is associated with I/O resources in both the first device and the second device, and wherein at least one of the I/O resources comprises a buffer resource. A data transfer operation may be sent between the first device and the second device by consuming at least some of the I/O resources associated with the I/O tunnel. A plurality of commands or a plurality of responses can be aggregated into a single buffer resource. Upon completion of the data transfer operation, the I/O resources that are consumed are automatically renewed.

Abstract: A method, system and article of manufacture are disclosed for registering and deregistering memory pages in a computer system. The method comprises the steps of hoisting register and deregister calls in a given routine where temporal locality is present to overlap computation and communication; using software pipelined registration and deregistration where spatial locality is observed; and using intra-procedural and inter-procedural analysis by a compiler of the computer system to deregister dynamically allocated buffers. The preferred embodiment of the invention is based on an optimizing compiler. The compiler is used to extract information such as addresses of buffers which are being reused repeatedly (temporal locality), preferably in a loop. The compiler may also find information about spatial locality, such as arrays whose indexes are used in a well-defined manner in a series of messages, for example, array pages being accessed in a pre-defined pattern in a loop.

Abstract: A dynamic A-MSDU enabling method is disclosed. The method enables the recipient of an aggregate MAC service data unit (A-MSDU) under a block ACK agreement to reject the A-MSDU. The method thus distinguishes between A-MSDU outside of the block ACK agreement, which is mandatory, from A-MSDU under the block ACK agreement, which is optional. The method thus complies with the IEEE 802.11n specification while enabling the recipient to intelligently allocate memory during block ACK operations.

Abstract: A network device includes a main storage memory and a queue handling component. The main storage memory includes multiple memory banks which store a plurality of packets for multiple output queues. The queue handling component controls write operations to the multiple memory banks and controls read operations from the multiple memory banks, where the read operations for at least one of the multiple output queues alternates sequentially between the each of the multiple memory banks, and where the read operations and the write operations occur during a same clock period on different ones of the multiple memory banks.

Abstract: A RAID controller is disclosed. The controller controls at least one redundant array of physical disks, receives I/O requests for the array from host computers, and responsively generates disk commands for each of the disks. Some commands specify host computer user data, and others specify internally generated redundancy data. The controller executes coalescer code that maintains the commands on a queue for each disk. Whenever a disk completes a command, the coalescer determines whether there are two or more commands on the disk's queue that have the same read/write type and specify adjacent locations on the disk, and if so, coalesces them into a single command, and issues the coalesced command to the disk. The coalescer immediately issues a received command, rather than queuing it, if the number of pending commands to the disk is less than a maximum command depth, which may be different for each disk.

Abstract: A device controller, a peripheral device, and a power control method that enable buffers to be used efficiently and that enable power control to be performed on the basis of data amounts accumulated in the buffers are provided. A novel device controller includes an input buffer for accumulating data output from a host device, an output buffer for accumulating data output to the host device, a data communication section for transferring data between the input and output buffers and the host device, and a data buffer control section for modifying buffer allocation amounts to the input and output buffers on the basis of the data amount accumulated in at least one of the input and output buffers. The data buffer control section causes the data communication section to transition from a normal power consumption mode to a low power consumption mode when the data amount reaches a predetermined value.

Abstract: A receiving circuit includes a frame memory to store received data of one frame, a de-rate matching circuit to generate data before encoding by reading the received data from the frame memory and performing de-rate matching in a reverse manner to rate matching performed on the received data at a transmitting end, and a TTI memory to store the data before encoding.

Abstract: A controller for a host system includes an interface and a buffer. The interface receives a plurality of data units isochronously received from a connected device, and the buffer stores the data units and then output a data block upon the occurrence of at least one condition. Each data unit stores data of a first size and the data block includes data of a second size greater than the first size. The connected device may be a Universal Serial Bus (USB) device or another type of device.

Abstract: In one embodiment, a node in a computer network may receive data of a particular type at a first frequency (e.g., a sensor in a sensor network), and may correspondingly determine whether there is at least one interested subscriber for the data of the particular type, where the interested subscriber desires the data at a second frequency. If there is an interested subscriber, buffered data publishing may be dynamically activated at the node in response to a ratio between the second and first frequencies being less than a configured threshold. In particular, buffered data publishing comprises buffering the received data and transmitting a latest received data to the interested subscriber at the second frequency.

Abstract: A system selectively drops data from queues. The system includes a drop table that stores drop probabilities. The system selects one of the queues to examine and generates an index into the drop table to identify one of the drop probabilities for the examined queue. The system then determines whether to drop data from the examined queue based on the identified drop probability.

Abstract: Techniques are described which simplify and/or automate many of the tasks associated with the configuration, deployment, and management of network resources to support cloud-based services.

Abstract: A controller for a host system includes an interface and a buffer. The interface receives a plurality of data units isochronously received from a connected device, and the buffer stores the data units and then output a data block upon the occurrence of at least one condition. Each data unit stores data of a first size and the data block includes data of a second size greater than the first size. The connected device may be a Universal Serial Bus (USB) device or another type of device.

Abstract: Memory system controllers can include hardware masters, first buffers, and a switch coupled to the hardware masters and to the first buffers. The switch can include second buffers and a buffer allocation management (BAM) circuit. The BAM circuit can include a buffer tag pool. The buffer tag pool can include tags, each identifying a respective first buffer or a respective second buffer. The BAM circuit can be configured to allocate a tag to a hardware master in response to an allocation request from the hardware masters. The BAM circuit can be configured to prioritize allocation of a tag identifying a second buffer over a tag identifying a first buffer.

Abstract: Some of the embodiments of the present disclosure provide a method comprising managing a plurality of buffer addresses in a system-on-chip (SOC); and if a number of available buffer addresses in the SOC falls below a low threshold value, obtaining one or more buffer addresses from a memory, which is external to the SOC, to the SOC. Other embodiments are also described and claimed.

Abstract: In an embodiment, an apparatus comprises a buffer, a plurality of processors, and a processor control module. The processor control module is to manage how many of the plurality of processors are used to process data from the buffer based at least in part on an amount of the data stored in the buffer.

Abstract: A power-saving control circuit and method suitable for circuits including a first-in-first-out (FIFO) register is provided. In the present invention, a logic circuit is disposed between two circuit modules with data transmitted in between. When there is data input into the FIFO register, the logic circuit activates a clock signal of the circuit module in the receiving end for reading the data. When all the data stored in the FIFO register is read, the clock signal is turned off so that the power consumed by the clock signal is reduced without affecting the data transmitting efficiency and the purpose of power-saving is achieved.

Abstract: A tape drive, tape drive recording system, and method are provided for improving tape speed selection during data transfer. The tape drive comprises a buffer, a tape for recording the data to be temporarily stored in the buffer, and a read head. The tape drive further comprises a reading controller that initially sets a tape speed such that a drive transfer rate matches a host transfer rate as closely as possible and that drives the tape at the tape speed. To address backhitching caused by one or more host transfer halts, the reading controller subsequently adjusts the tape speed such that the drive transfer rate is lower than the host transfer rate by recalculating the host transfer rate in consideration of the host transfer and the host transfer halt and setting the tape speed such that the drive transfer rate matches the recalculated host transfer rate as closely as possible.

Abstract: Described embodiments provide a method of transferring, by a media controller, data associated with a host data transfer between a host device and a storage media. A buffer layer module of the media controller segments the host data transfer into one or more data transfer segments. Each data transfer segment corresponds to at least a portion of the data. The buffer layer module allocates a number of physical buffers to a virtual circular buffer for buffering the one or more data transfer segments. The buffer layer module transfers, by the virtual circular buffer, each of the data transfer segments between the host device and the storage media through the allocated physical buffers.

Abstract: A first network device includes a first port to provide first data traffic to a first storage area network, a second port to provide second data traffic to a local area network, and memory shared between the first port and the second port to temporarily store the first data traffic in N first buffers and the second data traffic in M second buffers. A queue control module allocates a first memory space of the N first buffers to the first port and a second memory space of the M second buffers to the second port. An adjustment module adjusts a first amount of the first memory space and a second amount of the second memory space in response to a congestion event is caused by a first data traffic. Up to all of the first memory space and the second memory space is allocated to the N first buffers.

Abstract: Within a serial buffer, request packets are written to available memory blocks of a memory buffer, which are identified by a free buffer pointer list. When a request packet is written to a memory block, the memory block is removed from the free buffer pointer list, and added to a used buffer pointer list. Memory blocks in the used buffer pointer list are read, thereby transmitting the associated request packets from the serial buffer. When a request packet is read from a memory block, the memory block is removed from the used buffer pointer list and added to a request buffer pointer list. If a corresponding response packet is received within a timeout period, the memory block is transferred from the request buffer pointer list to the free buffer pointer list. Otherwise, the memory block is transferred from the request buffer pointer list to the used buffer pointer list.

Abstract: The packet forwarding apparatus of the present invention includes a packet buffer for temporarily storing packets to be forwarded, a timer for measuring the time of every predetermined unit period, a plurality of first queues corresponding to each of a plurality of address groups that form the packet buffer, a plurality of second queues that are provided corresponding to the property of the packets, a first controller for executing the writing of the packets, and a second controller for executing the discarding of the packets. According to this invention, through managing the first queues and the second queues, packets in the packet buffer can be discarded without the packets being read from the packet buffer.

Abstract: A network device allocates a number of blocks of memory in a ternary content-addressable memory (TCAM) of the network device to each database of multiple databases, and assigns unused blocks of memory of the TCAM to a free pool. The network device also detects execution of a run mechanism by the TCAM, and allocates, based on the execution of the run mechanism, one of the unused blocks of memory to a filter or rule of one of the multiple databases.

Abstract: A circuit for controlling a peripheral device interface is to enable a central processing unit to detect a peripheral device. The circuit includes a control chip and first to sixth capacitors. The control chip includes a power supply input pin, first to second differential signal output pins, first to second differential signal input pins, and an expansion pin. The power supply input pin is connected to a power supply and grounded via the first and second capacitors in parallel. The first and second differential signal output pins are connected to the peripheral device interface via the third and fourth capacitors respectively. The first and second differential signal input pins are connected to the peripheral device interface via the fifth and sixth capacitors respectively. The expansion pin is grounded via a resistor.

Abstract: A computer implemented method for writing to a software bound ring buffer. A network adapter may determine that data is available to write to the software bound ring buffer. The network adapter determines that a read index is not equal to a write index, responsive to a determination that data is available to write to the software bound ring buffer. The network adapter writes the data to memory referenced by the hardware write index, wherein memory referenced by the write index is offset according to an offset, and the memory contents comprise a data portion and a valid bit. The network adapter writes an epoch value of the write index to the valid bit. The network adapter increments the write index, responsive to writing the data to memory referenced by the write index. Further disclosed is method to access a hardware bound ring buffer.

Abstract: A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.

Abstract: In one embodiment, an apparatus comprises serializer/deserializer (SERDES) circuits. Each SERDES circuit is configured to transmit data on a respective lane to which the SERDES circuit is are coupled during use. The apparatus further comprises a transmit pipe coupled to the SERDES circuits. The transmit pipe comprises stages, and each stage is configured to process a maximum bandwidth unit (a maximum width of a port that is configurable on the lanes and smaller than a largest packet transmitted on the ports). In another embodiment, the apparatus comprises a transmit command queue; a transmit scheduler coupled to the transmit command queue; and a storage device coupled to the transmit scheduler that stores a scheduling calendar. The transmit scheduler is configured to schedule maximum bandwidth units for transmission on ports configured over the lanes on which packets are transmitted. The maximum bandwidth unit is smaller than a packet and is a maximum width of a port that is configurable on the lanes.

Abstract: A configuration performing processing of dividing a file into a plurality of pieces and transmitting the same even when a size of the file is large in transfer of files (input/output) between computers on a network is provided. A multi-thread file input/output system includes a first module performing processing of reading data from an input file, dividing the data into a plurality of pieces, and transmitting the plurality of pieces to a network by multi-thread processing in a transmitter computer; and a second module performing processing of receiving the plurality of pieces from the network and integrating and writing the same to an output file 5 in a receiver computer.

Abstract: A memory device and a method of managing a memory are provided. The memory device includes a command queue configured to receive a first command from a host to store the first command, and to read and transmit the first command, a controller configured to read, from a storage device, data corresponding to the first command transmitted from the command queue, and to store the data in a buffer memory, and a first memory configured to store a data list of data stored in the buffer memory, wherein, in response to the command queue receiving the first command from the host, the controller updates the data list of data stored in the first memory.

Abstract: According to one embodiment, a buffer management device includes a buffer memory, a current-credit retaining module, a reserved-credit retaining module, a transfer controller, and a subtractor. The buffer memory manages a storage area in a credit unit representing a predetermined data size and temporarily stores data transferred from an external device. The current-credit retaining module retains the number of credits currently available for the buffer memory as a current credit value. The transfer controller registers the number of credits necessary to temporarily store the data in the reserved-credit retaining module as a reserved credit value prior to the transfer of the data from the external device to the buffer memory. The subtractor subtracts the reserved credit value registered in the reserved-credit retaining module from the current credit value retained by the current-credit retaining module and outputs a subtraction result as an available credit value.