Abstract: Provided are methods and systems for adaptive settings for a device. An example method can comprise utilizing a first configuration setting for a feature in a device, detecting a change in a device factor, and utilizing a second configuration setting for the feature in the device in response to the detected change. Another example method can comprise detecting a change in a device factor, activating a device feature, determining whether a change threshold has been exceeded, and updating a configuration setting for a device feature if the change threshold has been exceeded.

Abstract: A method for low-latency data mirroring in a storage system, the method may include receiving, by a compute node of the storage system, a read request for reading a data unit stored at a primary storage block of the storage system; determining, by the compute node and based on primary storage block metadata, whether a content of the primary storage block is consistent; and responding to the determining of whether the content of the primary storage block is consistent. The responding may include (a) when determining that the primary storage block is inconsistent—copying the data unit from the primary storage block to a secondary storage block of the storage system, and updating the primary storage block metadata; and (b) reading the data unit from the primary storage block and sending the data unit to a requesting entity.

Abstract: An analog-digital conversion apparatus may include a control unit configured for receiving an analog-digital (AD) conversion request from a plurality of processing modules; and an analog-digital converter (ADC) configured for performing analog-digital conversion according to the AD conversion request received from the control unit, in which the control unit is configured to integrate the AD conversion request according to periodicity of the AD conversion request and to transfer the integrated AD conversion request to the ADC.

Abstract: A method for blocking external debugger application from analysing code of software program installed on computing device. The method including initializing software program including an application program and an internal debugger application. The software program, upon initialization thereof, instructs internal debugger application to load application program in internal debugger application. The internal debugger application is configured to utilize kernel resources of an operating system of the computing device.

Abstract: Example implementations relate to a database and a data stream query. For example, a computing device may include a processor. The processor may receive a query associated with at least one of a database and a buffer storing streamed data from a data stream, where the database stores database data previously stored in the buffer. The processor may identify at least one postponed command relevant to the query, the at least one postponed command being associated with at least one of the database data and the streamed data. The processor may generate a modified query based on the query and the at least one postponed command, the modified query being a modification of the query to account for the at least one postponed command. The processor may process the modified query and provide a query result of the query based on the modified query being processed.

Abstract: A method of performing an authorization mechanism between a service terminal system (ATM) and a helpdesk system (HD) includes the steps of: sending a request message (RQ) comprising a one-time code (CL), an identifier (CN) for the ATM and a set of access right data (TD) about rights for using the (ATM) by a user (TN); creating a response message (RS) by using the CL, TD, and an ident key (TK) derived from an operation on the CN and a base key (BK), the BK being a common secret of both, the HD and the ATM; sending the RS; creating a reference response message (RS*) by using the CL, the TD, and the TK; and comparing the RS with the RS* to authorize the TN to use the ATM according to the rights being represented by the TD.

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, and wherein the first instruction is configured to utilize a first memory location, begin execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction configured to utilize the first memory location, determining that the first instruction and the second instruction utilize the first memory location, and stalling execution of the second instruction based on the determining.

Abstract: Example implementations relate to a database and a data stream query. For example, a computing device may include a processor. The processor may receive a query associated with at least one of a database and a buffer storing streamed data from a data stream, where the database stores database data previously stored in the buffer. The processor may identify at least one postponed command relevant to the query, the at least one postponed command being associated with at least one of the database data and the streamed data. The processor may generate a modified query based on the query and the at least one postponed command, the modified query being a modification of the query to account for the at least one postponed command. The processor may process the modified query and provide a query result of the query based on the modified query being processed.

Abstract: A method and system for suspending and resuming a virtual machine. The method and system include a hypervisor to provide a guest operating system of a virtual machine with an instruction for the virtual machine to enter a sleep mode. The hypervisor receives, from the guest operating system, a confirmation that the virtual machine is in the sleep mode. Following receipt of confirmation that the virtual machine is in sleep mode, the hypervisor suspends the virtual machine.

Abstract: Embodiments of the present invention utilize a dual buffer size threshold system for raising interrupts that allows DUT testing systems to perform real-time buffer memory allocation procedures in an on demand basis. Using dual interrupt threshold systems in the manner described by embodiments of the present invention, DUT testing systems can reduce the need to decide on a single buffer size threshold when testing a set of DUTs that separately provide different amounts of fail data relative to each other. As such, embodiments of the present invention can minimize the overhead processing spent on interrupt handling while also reducing the amount wait time needed for the data processing module to process fail data for each DUT. Thus, embodiments of the present invention can increase the use of tester resources more efficiently while decrease the amount of time a tester system spends collecting and/or analyzing fail data for a set of DUTs during a testing session.

Abstract: To improve upon some of the characteristics of current storage systems in general and block data storage systems in particular, exemplary embodiments combine state-of-the art networking techniques with state-of-the-art data storage elements in a novel way. To accomplish this combination in a highly effective way, it is proposed to combine networking remote direct memory access (RDMA) technique and storage-oriented memory mapped input output (MMIO) technique in a system to provide direct access from a remote storage client to a remote storage system with little to no central processing unit (CPU) intervention of the remote storage server. In some embodiments, this technique may reduce the required CPU intervention on the client side. These reductions of CPU intervention potentially reduce latency while providing performance improvements, and/or providing more data transfer bandwidth and/or throughput and/or more operations per second compared to other systems with equivalent hardware.

Abstract: An apparatus and method of converting a capacitance measured on a sensor element to a digital value. The apparatus may include a matrix-scanning device including drive lines and sense lines. A sense element is located at an intersection of one of the drive lines and one of the sense lines. The apparatus also includes a modulation circuit coupled to the drive lines and the sense lines, and a switching circuit having first switches controlled by a clock. The modulation circuit is configured to measure a mutual capacitance on the sense element and to convert the measured mutual capacitance to a first digital value. The modulation circuit is configured to measure a self-capacitance on at least one of the drive lines and to convert the measured self-capacitance to a second digital value.

Abstract: An apparatus and method of converting a capacitance measured on a sensor element to a digital value. The apparatus may include a switching capacitor as a sensor element, a modulation circuit coupled to the sensor element, and a switching circuit having a plurality of switches controlled by a variable-period clock. The modulation circuit is configured to measure a capacitance on the sense element and to convert the measured capacitance to a digital value.

Abstract: A serial peripheral interface of an integrated circuit including multiple pins and a clock pin is provided. The pins are coupled to the integrated circuit for transmitting an instruction, an address or a read out data. The clock pin is coupled to the integrated circuit for inputting multiple timing pulses. The plurality of pins transmit the instruction, the address or the read out data at rising edges, falling edges or both edges of the timing pulses.

Abstract: Systems and methods are disclosed for handling a level triggered interrupt generated by a device assigned to a virtual machine running on a host machine. An example system includes a host machine that hosts a virtual machine and a device coupled to the host machine. The device is assigned to the virtual machine and generates one or more interrupts. The example system also includes an interrupt handler that receives an interrupt generated by the device, masks the interrupt, injects the interrupt into the virtual machine, receives an indication that the virtual machine has attempted to access the device, and in response to the indication that the virtual machine has attempted to access the device, unmasks the interrupt from the device.

Abstract: Overall memory requirements are minimized by performing copy on write and collapse on write operations using memory pointers when storing data within memory pages. Multiple memory pointers may refer to a primary page storing a definitive copy of data. When that data is to be modified, a copy on write operation creates a second copy in another memory page which may then be modified and updates memory pointers accordingly. When data within two or more memory pages is identical to data within a primary page, a collapse on write operation updates memory pointers to refer to the primary page and de-allocates the duplicative and now unused memory pages.

Abstract: A computer program product is provided for performing input/output (I/O) processing. The computer program product is configured to perform: generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data discard field; generating an address control structure specifying a local channel memory location of a corresponding ACW; receiving one or more data transfer requests from a network interface that each corresponding address control structure information; accessing an ACW and routing the data transfer request to a host memory location specified in the ACW; and responsive to encountering an error during at least one of the accessing and the routing, discarding the one or more data transfer requests and setting the data discard field to a value configured to instruct a channel to discard any subsequent data transfer requests associated with the ACW.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: In response to receiving a request for a DMA data transfer, a DMA transfer mode may be determined based on based on the size of the requested DMA data transfer and profile data of an I/O adapter. The profile data for the I/O adapter may include a physical location of the I/O adapter or a number of clients supported by the I/O adapter. The DMA transfer mode may also be determined based on a preference of an application or an I/O device. Moreover, the DMA transfer mode may be determined based on a CPU usage metric being outside of a threshold for the CPU usage metric or on a memory usage metric being outside of a threshold for the memory usage metric.

Abstract: An energy efficient Ethernet physical layer (PHY) device including an EEE control module configured to generate a control signal to transition the PHY device into a low power consumption mode based an operating condition, and a pause frame generator module responsive to the control signals to generate a pause frame. The pause frame generator module is configured to send the pause frame to a media access control (MAC) device to reduce an incoming flow of data packets from the MAC device to the PHY device for a pause time duration. In operation, the pause frame generator module generates the pause frame including a pause time indicating the length of time for the PHY device to be in the low power consumption mode. The value of the pause time for each pause frame is determined adaptively based on the amount of data traffic to be transmitted from the PHY device.

Abstract: A universal serial bus (USB) host device and a method of operating the same are provided. The method includes starting a first data transfer in an on-state, entering a suspend state when an idle-delay time elapses after the first data transfer is completed, making a transition from the suspend state to the on-state after performing a resuming operation when a second data transfer is requested, and dynamically controlling the idle-delay time based on a compared result of a current miss rate and at least two predetermined miss rates.

Abstract: In a transmission device: a controller performs a control of reading, from information regarding video specification, first information indicating whether a reception device is capable of intermittent reception of receiving a video signal at a timing that causes certain number of frames to be intermittent, and, when the reception device can perform intermittent reception, multiplexing, to the video signal during a blanking period of the video signal to be updated, an enable signal indicating the present video signal is to be enabled and second information indicating that transmission of the video signal will not resume unless the video signal is updated; and a transmitter transmits the video signal that is to be updated and then does not resume transmission of the video signal unless the video signal is updated.

Abstract: A method and system of a host device hosting multiple workloads for controlling flows of I/O requests directed to a storage device is disclosed. In one embodiment, a type of a response from the storage device reacting to an I/O request issued by an I/O stack layer of the host device is determined. Then, a workload associated with the I/O request is identified among the multiple workloads based on the response to the I/O request. Further, a maximum queue depth assigned to the workload is adjusted based on the type of the response, where the maximum queue depth is a maximum number of I/O requests from the workload which are concurrently issuable by the I/O stack layer.

Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

Abstract: In an information processing device according to an embodiment, a generating unit generates a descriptor including information indicating an area in a storage unit and state information indicating a state of an entry in which the information indicating the area is stored, and an update unit updates the state information according to at least one of writing and reading of data to the area indicated in the entry selected according to the state information by the input/output unit. The generating unit generates the descriptor in advance before at least one of writing and reading of data to/from the storage unit is started.

Abstract: A display controller may include an RGB Interface module and a display port module, which may both use a target-master interface, in which the data receiving module pops pixels from the data sourcing module, and generates the HSync, VSync, and VBI timing signals. A dither module may be instantiated between the RGB interface module and display port module to perform dithering. The dither module may use a source-master interface, in which data signals and data valid signals are issued by the data sourcing module. In order to avoid having to use a large storage capacity FIFO with the dither module, a control unit may issue interface signals to the RGB Interface module and display port module, and clock-gate the dither module, to allow the data signals and data valid signals to properly interface with the RBG interface module and display port module, and provide data flow from the RGB interface module to the dither module to the display port module.

Abstract: A technique for handling stranded file opens for DCOM utility requests in a NSK. In one example embodiment, this is achieved by selecting a source file to be compressed in a disk by the DCOM utility. The source file includes one or more non-contiguous disk file extents and each non-contiguous disk file extent includes multiple blocks. A temporary file is then crated to copy the source file. The multiple blocks in a current non-contiguous disk file extent are then copied from the source file by the DCOM utility by transferring data to the disk as a function of a NSK net transfer data limit size. A current file descriptor of the source file is then stored in an offset field of the temporary file and a current value is then set in the offset field of a source file control block of the source file as a function of whether all of the multiple blocks in the current non-contiguous disk file extent were copied to the disk.

Abstract: A method according to one embodiment includes receiving, at an I/O Handler, an instruction to initiate a backup operation on data associated with an application running on multiple servers; and stretching communication between instances of the application and data storage volumes associated therewith during initiating the backup operation. Additional systems, methods, and computer program products are also disclosed.

Abstract: Techniques are disclosed for managing the flow of IO jobs from a client to a hardware device such that resource starvation is reduced without significantly impacting throughput. Each flow can be assigned an amount of time that a hardware device can deplete completing IO jobs from the client. When the allocated amount of time is used IO jobs associated with the client can be stored in a queue until the client obtains more time.

Abstract: A conversion unit converts a command part of an image inclusion command into an internal command. A first memory unit stores an image non-inclusion command and the internal command converted by the conversion unit. A second memory unit stores an image data part of the image inclusion command. A restart page number memory unit stores restart page number information when a print process being executed is interrupted in order to execute an interruption print process. When restarting the interrupted print process, a control unit executes control to read out the internal command and the image non-inclusion command stored in the first memory unit up to the page indicated by the restart page number information, and from the page indicated by the restart page number, further executes control to read out from the second memory unit the image data part following the internal command read out from the first memory unit.

Abstract: A LAN control unit receives print data from a client device or the like. An input job storage unit registered on a hard disk a series of PDL commands included in the print data received. An input job queue management unit registers print job specifying information specifying a print job represented by the print data received to the end of an input job queue. A PDL interpretation/execution unit successively executes from the head of the series of PDL commands stored on the hard disk device. When it is determined that the PDL command that has been executed is a re-execution unnecessary command, the PDL interpretation/execution unit overwrites the PDL command stored on the hard disk with a NOP command.

Abstract: The present invention concerns a system and a process for acquiring a software code (SW) in a device from a host computer, a host computer and a software transmission process. The system comprises receiving means of at least one code portion of the software code, at least two competing available code portions (Sik) being proposed simultaneously to the device for being downloaded, delaying means sending to the computer for each competing portion, successive negative acknowledgements (NAK), and selecting means of the code portion to be received among the competing available ones, the delaying means stopping sending the negative acknowledgements for the selected portion, so that the receiving means receive only the selected portion.

Abstract: In various embodiments, a computer system may include a computer controller to send and/or receive sideband signals to/from a USB device. In some embodiments, the USB device may include a USB controller to send/receive sideband signals to/from the computer controller. The computer controller and USB controller may allow communications between the computer system and the USB device when either of the computer system or USB device is in a low power state. The sideband signal sent between the computer system and the USB device may trigger the other of the computer system or USB device to enter a normal power state. In some embodiments, the computer controller and/or USB controller may be further coupled to a memory to buffer data to be sent to the computer system or USB device after the computer system or USB device returns to a normal power state.

Abstract: A synchronization device includes a receiver that receives data from at least two synchronization devices establishing synchronization, and extracts synchronization information and register selection information from the received data, a transmitter that transmits data to each of the at least two synchronization devices establishing synchronization among a plurality of synchronization devices, a first and a second receiving state register that each stores the extracted synchronization information, a second receiving state register that stores the extracted synchronization information, and a controller that stores the extracted synchronization information into the first receiving state register and the second receiving state register alternately based on the register selection information, and controls the transmitter to transmit data including the register selection information to each of the at least two synchronization devices when the extracted synchronization information is completed in one of the first a

Abstract: To increase the number of analog inputs at low cost, an analog input system includes: one or more analog slave units each connected to a bus to which a CPU unit is connected, and each including an A/D-conversion device converting an analog value outputted by an external device into a first digital value, a buffer memory buffering a second digital value to be transferred to the CPU unit, and a nonvolatile storage device containing specific information of its own unit; and an analog master unit connected to the bus and including an operation section performing operation processing based on the specific information stored in the storage device with the first digital value being used as an input, to calculate the second digital value, the master unit performing on each of the slave input units the operation processing and processing of transferring the calculated second digital value to the buffer memory.

Abstract: Data received over a shared network interface is directly placed by the shared network interface in a designated memory area of a host. In providing this direct memory access, the incoming data packets are split, such that the headers are separated from the data. The headers are placed in a designated area of a memory buffer of the host. Additionally, the data is stored in contiguous locations within the buffer. This receive and store is performed without interruption to the host. Then, at a defined time, the host is interrupted to indicate the receipt and direct storage of the data.

Abstract: There is provided a content transmission apparatus including a reception unit for performing a receiving process for receiving, from a content output apparatus, a transmission instruction that is based on an output order of pieces of content data, a transmission unit for starting transmission of content data to the content output apparatus in response to the transmission instruction, and a control unit for controlling a time interval for causing the reception unit to perform the receiving process, according to wait information indicating a status of wait until transmission of the content data to the content output apparatus is to be started.

Abstract: This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided.

Abstract: Systems and methods for streaming data are disclosed. In various implementations, the system comprises a hardware device and input streaming interface operably connected to the hardware device. The input streaming interface is configured to inform a data source, based on a determination that a receiving device will accept data transmitted by the hardware device, that the input streaming interface is ready to receive data, and then receive, in response to the detecting the activation of a source signal and a data initiation signal associated with the data source, source data transmitted by the data source over a data bus, and forward the source data to the hardware device.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal from the input-output device, outputs a result of the control operation to a process, and has a timer unit to be excited at a constant period; and the software part has an information process part, a control process part, and an interrupt control unit to switch over the information process part and control process part one another, in which the interrupt control unit suspends an execution of the information process part to execute the control process part in priority and resume the information process part by switching over to the information process part from the control process part, when the execution of the control process part is terminated.

Abstract: A system and method for enabling legacy media access control (MAC) to do energy efficient Ethernet (EEE). A backpressure mechanism is included in an EEE enhanced PHY that is responsive to a detected need to transition between various power modes of the EEE enhanced PHY. Through the backpressure mechanism, the EEE enhanced PHY can indicate to the legacy MAC that transmission of data is to be deferred due to a power savings initiative in the EEE enhanced PHY.

Abstract: A computer program product is provided for performing input/output (I/O) processing at a host computer system. The computer program product is configured to perform: generating an address control structure for each of a plurality of consecutive data transfer requests specified by an I/O operation, each address control structure specifying a location in the local channel memory of a corresponding address control word (ACW) that includes an Offset field indicating a relative order of a data transfer request; generating and storing in local channel memory at least one ACW specifying one or more host memory locations for the plurality of consecutive data transfer requests and including an Expected Offset field indicating a relative order of an expected data transfer request; receiving a transfer request from the network interface and comparing the Offset field and the Expected Offset field to determine whether the data transfer request has been received in the correct order.

Abstract: According to one embodiment, a memory control device includes a controller, a command queue module, a plurality of stage processors, and a skip module. The controller controls a data access command to a nonvolatile memory from a host. The command queue module queues a transfer request command corresponding to the data access command. The stage processors each perform stage processing related to the transfer request command queued by the command queue module. The skip module skips the stage processing by the stage processors in response to a shutdown command from the controller.

Abstract: A disclosed information processing apparatus, which is connected to an output device, detects, from output setting information, an uninterpretable setting that is uninterpretable by the information processing apparatus, according to the output setting information used when performing output and function information relevant to a function executable by the output device; displays a page for selecting an option of an interpretable setting that is interpretable by the information processing apparatus, which interpretable setting corresponds to the detected uninterpretable setting; and makes a correction for changing the uninterpretable setting to be the interpretable setting that is interpretable by the information processing apparatus according to the option selected in the displayed page.

Abstract: A serial peripheral interface of an integrated circuit including multiple pins is provided. The pins are coupled to the integrated circuit. The integrated circuit receives an instruction through only one of the plurality of pins. The integrated circuit receives an address through the plurality of pins. The integrated circuit sends a read out data through the plurality of pins.

Abstract: A DMA transfer control device comprises: a DMA arbiter that performs DMA transfer for each DMA channel formed by a combination of a memory and a plurality of input/output devices and DMA controller circuits that control the DMA arbiter; a judgment unit and a transfer time calculation unit that calculates a next DMA transfer scheduled time based on the DMA transfer size for a DMA transfer request and a judgment time. A timer counter that times the judgment time at a unit time interval, and a comparator that compares the judgment time at which a DMA transfer request arrives with the DMA transfer scheduled time are also provided, and the judgment unit sends the DMA transfer permission to the DMA arbiter when an output of the comparator indicates that the judgment time is not earlier than the DMA transfer scheduled time. The efficiency of data transfer by dynamically controlling DMA transfer is performed.

Abstract: A method and logic circuit for a resource management finite state machine (RM FSM) managing resource(s) required by a protocol FSM. After receiving a resource request vector, the RM FSM determines not all of the required resource(s) are available. The protocol FSM transitions to a new state, generates an output vector, and loads the output vector into an output register. The RM FSM transitions to a state indicating that not all the resources are available and freezes an input register. In a subsequent cycle, the RM FSM freezes the output register and a current state register, and forces the output vector to be seen by the FSM environment as a null token. After determining that the required resource(s) are available, the RM FSM transitions to another state indicating that the resources are available, enables the output vector to be seen by the FSM environment, and unfreezes the protocol FSM.

Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.

Abstract: Method and apparatus for managing item sequence numbers in an item processing system. The invention provides for overrun prevention and management of item sequence numbers, which form a part of an image key. In example embodiments, a buffer is provided to determine how close a current item sequence number (ISN) is permitted to be to an overrun value. When the current ISN reaches the buffer value, new entries of documents are prevented or at least restricted from being processed. In some embodiments, a “force mode” is provided in which a sorter can be made to start a new entry even if the buffer value has been exceeded. In such an embodiment, the system can be set up so that a hard stop is enforced when the ISN is within a certain range of the overrun value.