Input/output Process Timing Patents (Class 710/58)
  • Patent number: 10037443
    Abstract: A simulation environment is provided for running a process simulation used to validate an industrial control program. The simulation environment exposes the I/O module configurations defined in the control program and retrieves module configuration information therefrom. This I/O module configuration information is combined with generic, module-specific I/O module profiles to create a pool of available controller I/O points, which can be selectively associated with I/O points in the simulation to create an I/O point mapping. During control program validation, simulated I/O data is exchanged between the process simulation and the I/O module instances in the controller in accordance with the I/O point mapping. A variation of these techniques for use with cloud-based emulations is also described.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: July 31, 2018
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Francisco P. Maturana, Raymond J. Staron, Danny L. Carnahan, Kenwood H. Hall
  • Patent number: 10025748
    Abstract: A system can include a host device and a remote terminal. The host device can include a host terminal, the host terminal including a host configuration manager to allocate a data lane to an I/O protocol and a protocol multiplexer to carry out allocation of the data lane based on the allocation of the configuration manager. The remote terminal can include a remote configuration manager. The remote configuration manager is to communicate with the remote configuration manager via a control bus to detect connection of an I/O device to an I/O port and to allocate the data lane to the I/O protocol.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Huimin Chen, Dennis M. Bell, Robert A. Dunstan, Duane G. Quiet, Gary A. Solomon
  • Patent number: 9971914
    Abstract: A simulation environment for running a process simulation used to validate an industrial control program. The simulation environment exposes the I/O module configurations defined in the control program and retrieves module configuration information therefrom. This I/O module configuration information is combined with generic, module-specific I/O module profiles to create a pool of available controller I/O points, which can be selectively associated with I/O points in the simulation to create an I/O point mapping. During control program validation, simulated I/O data is exchanged between the process simulation and the I/O module instances in the controller in accordance with the I/O point mapping.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: May 15, 2018
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Francisco P. Maturana, Raymond J. Staron, Danny L. Carnahan, Kenwood H. Hall
  • Patent number: 9916111
    Abstract: System and methods for selectively or automatically migrating resources between storage operation cells are provided. In accordance with one aspect of the invention, a management component within the storage operation system may monitor system operation and migrate components from storage operation cell to another to facilitate failover recovery, promote load balancing within the system and improve overall system performance as further described herein. Another aspect of the invention may involve performing certain predictive analyzes on system operation to reveal trends and tendencies within the system. Such information may be used as the basis for potentially migrating components from one storage operation cell to another to improve system performance and reduce or eliminate resource exhaustion or congestion conditions.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: March 13, 2018
    Assignee: Commvault Systems, Inc.
    Inventors: Srinivas Kavuri, Marcus S. Muller
  • Patent number: 9910716
    Abstract: In one aspect, a method implemented by a first sync controller includes receiving sync information, wherein the sync information (i) identifies a first sync process, (ii) indicates that the first sync controller is not a master controller of the first sync process, and (iii) identifies a group of components executing the first sync process, the group comprising a first processing device; receiving a first sync indication from the first processing device; storing an indication, associated with the first sync process, that the first sync indication was received from the first processing device; determining that a sync indication has been received from all components of the first group of components; and transmitting a second sync indication to a second sync controller.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 6, 2018
    Assignee: KnuEdge Incorporated
    Inventors: Douglas B. Meyer, Andrew White, Jerome V. Coffin, Michael George Creamer
  • Patent number: 9823946
    Abstract: A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: November 21, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Kazushi Kurata, Kazuya Furukawa, Tetsuya Tanaka, Nobuo Higaki, Kunihiko Hayashi, Hiroshi Kadota, Tokuzo Kiyohara, Kozo Kimura, Hideshi Nishida, Shigeki Fujii, Toshio Sugimura
  • Patent number: 9729599
    Abstract: An example implementation may involve a computing system receiving a request from a first media playback system for access to a queue of media items, and a request from a second media playback system for access to the queue of media items. The computing system may grant a first type of access to the first media playback system and a second type of access to the second media playback system. The first type of access and the second type of access may authorize a first set of operations and a second set of operations on the queue of media items, respectively. The computing system may provide an indication that the first media playback system may access the queue as authorized by the first type of access, and an indication that the second media playback system may access the queue as authorized by the second type of access.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: August 8, 2017
    Assignee: Sonos, Inc.
    Inventors: Steven Beckhardt, Andrew J. Schulert, Gregory Ramsperger
  • Patent number: 9465748
    Abstract: A translation lookaside buffer (TLB) configured for use in a multiple operating system environment includes a plurality of storage locations, each storage location being configured to store a page translation entry configured to relate a virtual address range to a physical address range, each page translation entry having an address space identifier (ASID) associated with an operating system. The TLB also includes flush logic configured to receive a TLB flush request from an operating system having an operating system ASID and flush only TLB page translation entries having a stored ASID that matches the operating system ASID.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: October 11, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Prasanta K. Bhowmik, Douglas B. Hunt
  • Patent number: 9448892
    Abstract: System and methods for selectively or automatically migrating resources between storage operation cells are provided. In accordance with one aspect of the invention, a management component within the storage operation system may monitor system operation and migrate components from storage operation cell to another to facilitate failover recovery, promote load balancing within the system and improve overall system performance as further described herein. Another aspect of the invention may involve performing certain predictive analyzes on system operation to reveal trends and tendencies within the system. Such information may be used as the basis for potentially migrating components from one storage operation cell to another to improve system performance and reduce or eliminate resource exhaustion or congestion conditions.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: September 20, 2016
    Assignee: Commvault Systems, Inc.
    Inventors: Srinivas Kavuri, Marcus S. Muller
  • Patent number: 9411630
    Abstract: A method for reducing virtual machine preemption in a virtualized environment is provided. The method includes dispatching a virtual central processing unit (CPU) to run in an emulation mode on a real CPU until the real CPU exits the emulation mode, determining whether the virtual CPU has loaded a wait state, determining whether a remaining time slice of the virtual CPU as a result of the dispatching is below a predefined threshold in an event that the virtual CPU has loaded the wait state and rescheduling the virtual CPU with a full time slice in an event the remaining time slice of the virtual CPU is below the predefined threshold.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: August 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin S. Adams, Mark J. Lorenc, Donald W. Schmidt
  • Patent number: 9330034
    Abstract: In a memory system in which a system clock signal is forwarded from the memory controller to multiple memory devices, the phase of the system clock signal forwarded to the slower memory device is advanced relative to the system clock signal forwarded to the faster memory device by a phase corresponding to the skew on the data links corresponding to the memory devices. This causes the state machine of the slower memory device to change states and advance earlier than the state machine in the faster memory device, and as a result, the data read from both the slower memory device and the faster memory device are unskewed on the data links between the memory controller and the memory devices.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: May 3, 2016
    Assignee: Rambus Inc.
    Inventors: Yohan Usthavia Frans, Simon Li
  • Patent number: 9275733
    Abstract: A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: March 1, 2016
    Assignee: Rambus Inc.
    Inventors: Richard E. Perego, Pradeep Batra, Steven Woo, Lawrence Lai, Chi-Ming Yeung
  • Patent number: 9172755
    Abstract: A building-facility information storage stores data sizes of process data to be collected from building-side communicating devices. A schedule generating unit generates a collection schedule of the process data from the building-side communicating devices so that, in a collection period including a plurality of unit periods continuous in terms of time, a first communication load representing a total data volume received from the building-side communicating devices per unit period and second communication loads each representing a data volume transmitted from each of the building-side communicating devices per unit period are balanced among the unit periods. A network communicating unit collects the process data from the building-side communicating devices in accordance with the collection schedule.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: October 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshio Ito, Yu Kaneko, Shigeo Matsuzawa
  • Patent number: 9167470
    Abstract: A method of handling signaling congestion for a machine type communication (MTC) device and/or a MTC server in a wireless communication system is disclosed. The method comprises receiving system information from a network; and stopping a triggering operation in a communication window according to the system information, wherein the system information indicates occurrence of a signaling congestion situation in the network.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: October 20, 2015
    Assignee: HTC Corporation
    Inventor: Ching-Yu Liao
  • Patent number: 9134356
    Abstract: In processing devices, in particular in measuring, test or control units for the drivetrain or components thereof, it is often necessary to combine signals or data of different synchronization sources with one another or to process them whilst maintaining the original temporal relation. In order to achieve this, the signals or data have hitherto often been synchronized to a specific clock source, but this is frequently not possible. Therefore, a method and a device are specified which enable the processing of data or signals with different synchronization sources in a processing device by virtue of the fact that a dedicated time level is introduced for each synchronization source in the processing device, the temporal reference of the associated data and signals being retained in the time levels. The signals and data are processed in the time levels with the temporal original reference being maintained.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: September 15, 2015
    Assignee: AVL List GmbH
    Inventors: Dietmar Peinsipp, Peter Priller
  • Patent number: 9092160
    Abstract: Selective enablement of operating modes or features of a storage system via host transfer rate detection enables, in some situations, enhanced performance. For example, a Solid-State Disk (SSD) having a serial interface compatible with a particular serial interface standard selectively enables coalescing of status information for return to a host based on detecting a particular host transfer rate capability. Some hosts are not fully compliant with the particular standard, being unable to properly process the coalesced status information. The selective enablement disables status coalescing for a non-compliant host and enables status coalescing for at least some compliant hosts, without the SSD having prior knowledge of coupling to a noncompliant/compliant host. The SSD conservatively determines the host is non-compliant/compliant based on a negotiated speed of the serial interface, and selectively disables/enables status coalescing in response to the negotiated speed.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: July 28, 2015
    Assignee: Seagate Technology LLC
    Inventor: Andrew John Tomlin
  • Patent number: 9026689
    Abstract: An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement word associated with an I/O response block. In a further aspect, the stored data may have a resolution of approximately one-half microsecond.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventors: Scott M. Carlson, Greg A. Dyck, Tan Lu, Kenneth J. Oakes, Dale F. Riedy, Jr., William J. Rooney, John S. Trotter, Leslie W. Wyman, Harry M. Yudenfriend
  • Patent number: 9015381
    Abstract: A method is described that involves detecting the presence of a pairing partner. Prior to establishing a paired relationship with the pairing partner, a user is prompted to verify himself/herself. In response to the user properly verifying himself/herself, the paring partner is paired with. The pairing includes invoking a remote storage protocol that contemplates a network between the partners to establish on a first of the partners access to non volatile storage resources for general use. The non volatile storage resources are located on a second of the partners. The second of the partners is a handheld device that provides wireless cell phone service, wireless Internet service and music playback service.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: April 21, 2015
    Assignee: Apple Inc.
    Inventors: Mitch Adler, Jonathan Jay Andrews
  • Patent number: 9009368
    Abstract: A system and method for finding the sources of increased interrupt latencies. An interrupt controller includes monitoring logic for measuring and storing latencies for servicing interrupt requests. The interrupt controller determines a measured latency is greater than an associated threshold and in response sends an indication of a long latency. The interrupt controller may send the indication to firmware, a device driver, or other software. The interrupt controller stores associated information with the measured latency for debug purposes. Additionally, the monitoring logic may perform statistical analysis in place of, or in addition to, software.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: April 14, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Sean T. White
  • Patent number: 9009378
    Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: April 14, 2015
    Assignee: Vetra Systems Corporation
    Inventor: Jonas Ulenas
  • Patent number: 8996763
    Abstract: An electronic device executes a certain process when first data for instructing the electronic device to begin the certain process has been received from an external apparatus, and stops the certain process when the external apparatus has not been detected as a certain apparatus and when a first time has elapsed since the certain process was executed, even if second data for instructing the electronic device to stop the certain process has not been received.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: March 31, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hidetaka Koizumi
  • Patent number: 8996764
    Abstract: Some of the embodiments of the present disclosure provide a method comprising categorizing each data packet of a plurality of data packets into one of at least two priority groups of data packets; and controlling transmission of data packets of a first priority group of data packets during a first off-time period such that during the first off-time period, data packets of the first priority group of data packets are prevented from being transmitted to a switching module from one or more server blades. Other embodiments are also described and claimed.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: March 31, 2015
    Assignee: Marvell International Ltd.
    Inventor: Martin White
  • Publication number: 20150089097
    Abstract: An I/O processing control apparatus integrates, from among a plurality of unprocessed I/O requests, two or more I/O requests, which are for the same type of I/O process and have two or more noncontiguous areas as I/O destinations, into one I/O request targeted at one continuous area comprising the above-mentioned two or more noncontiguous areas, and executes I/O processing in relation to the storage device on the basis of the integrated I/O request.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 26, 2015
    Applicant: HITACHI, LTD.
    Inventors: Yuya ISODA, Atsushi TOMODA
  • Patent number: 8984181
    Abstract: According to one embodiment, a video sender comprises: a video processor and a communication module. The video processor creates video. The communication module is configured to communicate with a video receiver. The communication module comprises: a receiver and a transmitter. The receiver receives, from the video receiver, specific information specifying which one of a color signal and a frame rate takes precedence over the other one in transmission. The transmitter converts the video created by the video processor into video in which one of the color signal and the frame rate takes precedence over the other one in accordance with the specific information, and transmit the video thus converted to the video receiver.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Minemura, Nobuaki Suzuki, Takashi Doi, Hideki Miyasato
  • Patent number: 8972631
    Abstract: The defined architecture allows for format-efficient data storage on bit-patterned media, while allowing for typical variations in the drive, such as reader to writer gap variations. The defined BPM architecture relaxes some timing requirements on real-time signaling from the formatter to the channel, while enabling bit-accurate alignment between data accesses and the media.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Seagate Technology LLC
    Inventors: Jimmie Ray Shaver, Barmeshwar Vikramaditya
  • Patent number: 8949476
    Abstract: Techniques for providing an interface between a UICC and a processor, included in an access terminal, that supports asynchronous command processing by the UICC, are described. A first complex command, with a first processing time, may be received from the processor. An initial response to the first command, including a token, may be sent to the processor. The first command may be processed for the first processing time. At least one additional command, having a processing time shorter than the first processing time, may be received from the processor. Processing of the first command may be completed. Processing of a current one of the at least one additional command, which was being processed before, during, or after completion of the processing of the first command, may be completed. A response to the current one of the at least one additional command, including the token, may be sent to the processor.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: February 3, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Michele Berionne, Jose Alfredo Ruvalcaba, Younghwan Kang, Nicholas Matthias Beckmann
  • Patent number: 8949490
    Abstract: Disclosed herein is a data reception circuit including a clock generation block configured to divide a first clock based on clock information, the first clock being the clock of a transmission stream targeted to transmit video data between apparatuses, the clock information indicating a cyclical relationship between the first clock and a second clock serving as the clock of predetermined data, the clock generation block further outputting the divided clock as the second clock.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: February 3, 2015
    Assignee: Sony Corporation
    Inventor: Atsuhiro Naka
  • Patent number: 8943351
    Abstract: A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure (such as a clock carrier signal) containing information about a distributed clock frequency and phase and outputting a decoded carrier signal; and circuitry for receiving the decoded carrier signal, for generating a software interrupt upon receipt of a predefined data packet (such as a SOF packet) and for passing the software interrupt to the USB microcontroller; wherein the USB microcontroller is configured to respond to the software interrupt (such as with an interrupt service routine provided therein) by generating an output signal adapted to be used as a synchronization reference signal.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 27, 2015
    Assignee: Chronologic Pty. Ltd.
    Inventor: Peter Graham Foster
  • Patent number: 8918560
    Abstract: A controller for a storage device is connected to a host system and the storage device. A buffer memory includes first and second storage areas. A timer counts a preset given time in response to an instruction to start counting and sends a deadline notification when A given time is elapsed. A command responding portion, when receiving a read command from the host system, instructs the timer to start counting and thereafter outputs a read instruction to read data from the storage system. A data processing portion, in response to the read instruction by the command responding portion, reads specified data from the storage device and holds the read data in the second storage area of the buffer memory. A read control portion sends the host system the data held in the second storage area of the buffer memory when the deadline notification is received from the timer.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: December 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Nishikawa, Keiji Yamamoto, Yoshiki Namba, Taichi Tashiro, Kohta Nakamura
  • Patent number: 8914563
    Abstract: An integrated circuit includes a shared synchronization bus having a plurality of channels assigned to one or more of a plurality of peripheral modules. The integrated circuit further includes a first peripheral module of the plurality of peripheral modules including a control output coupled to the shared synchronization bus and configured to communicate event timing data to an input of a second peripheral module of the plurality of peripheral modules through a selected one of the plurality of channels.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: December 16, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Bradley Martin, Thomas Saroshan David, Alan Lee Westwick
  • Patent number: 8909817
    Abstract: A signal associated with multiple haptic effects is received, each haptic effect from the multiple haptic effects being associated with a time slot from multiple time slots. Each haptic effect from the multiple haptic effects is associated with an effect slot from multiple effect slots at least partially based on the time slot associated with that haptic effect. An output signal is sent for each effect slot from the multiple effect slots, when the associated haptic effect is scheduled for its time slot.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: December 9, 2014
    Assignee: Immersion Corporation
    Inventors: Juan Manuel Cruz-Hernandez, Henrique D. Da Costa, Danny A. Grant, Robert A. Lacroix
  • Patent number: 8904082
    Abstract: Operation based polling in a memory system. A device manager is provided to perform efficient polling by utilizing the effective bandwidth of the memory system, in a controller coupled to a communication end point. The device manager includes a detection module for detecting a type of operation sent to the communication end point. The device manager also includes a storage module for storing a polling interval value based on a time period of the type of operation in a polling counter of the controller. Further, the device manager includes a controlling module for controlling a polling operation of the controller in such a way that the controller polls the communication end point after a wait period according to the polling interval value.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: December 2, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sandeep Brahmadathan, Bikram Banerjee
  • Patent number: 8904121
    Abstract: A storage tiered that satisfies desired performance is configured by recognizing the type and capacity of storage media of a storage apparatus, which are held by a user, and using the storage media.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 2, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Anna Naito, Wataru Okada, Hirokazu Ikeda
  • Patent number: 8898354
    Abstract: Devices and methods for generating timing signals at a rate that matches a rate of remotely generated timing signals are provided. In some embodiments, a host generates timing signals in accordance with a USB specification, such as keep-alives, start-of-frame packets, or ITPs. An upstream facing port transmits the timing signals over a network to a downstream facing port. The downstream facing port generates and transmits timing signals to a USB device at a predetermined rate, and alters the predetermined rate based on an analysis of the rate at which timing signals are received from the upstream facing port.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: November 25, 2014
    Assignee: Icron Technologies Corporation
    Inventor: Keith Kejser
  • Patent number: 8893146
    Abstract: A method and system of a host device hosting multiple workloads for controlling flows of I/O requests directed to a storage device is disclosed. In one embodiment, a type of a response from the storage device reacting to an I/O request issued by an I/O stack layer of the host device is determined. Then, a workload associated with the I/O request is identified among the multiple workloads based on the response to the I/O request. Further, a maximum queue depth assigned to the workload is adjusted based on the type of the response, where the maximum queue depth is a maximum number of I/O requests from the workload which are concurrently issuable by the I/O stack layer.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: November 18, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kishore Kumar Muppirala, Narayanan Ananthakrishnan Nellayi, Sumanesh Samanta
  • Patent number: 8886845
    Abstract: A method, computer program product, and computing system for associating a first I/O scheduling queue with a first process accessing a storage network. The first I/O scheduling queue is configured to receive a plurality of first process I/O requests. A second I/O scheduling queue is associated with a second process accessing the storage network. The second I/O scheduling queue is configured to receive a plurality of second process I/O requests.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: November 11, 2014
    Assignee: EMC Corporation
    Inventors: Roy E. Clark, Michel F. Fisher, Humberto Rodriguez
  • Patent number: 8886855
    Abstract: An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a replica distribution network, a bit lag control element, and a synchronous lag receiver. The replica distribution network receives a first signal, and generates a second signal, where the replica distribution network comprises replicated propagation characteristics of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: November 11, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: Vanessa S. Canac, James R. Lundberg
  • Patent number: 8874812
    Abstract: A method for communicating media between a host and a display system. In one embodiment the method comprises acquiring, by the host and via a wireless connection between the host and the display system, display information of the display system; generating, by the host, an image sequence at a resolution and a frame rate, the resolution and the frame rate determined from the display information; communicating, from the host to the display system and via the wireless connection, an encoding of the image sequence; and displaying, by the display system, a decoding of the encoding.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: October 28, 2014
    Assignee: Teradici Corporation
    Inventors: David Victor Hobbs, Ian Cameron Main
  • Publication number: 20140317321
    Abstract: A signal processing device includes an operation control unit configured to control a timing of an operation process executed by an operation unit; and a transfer control unit configured to control a timing of transferring data that is a target of the operation process, such that the data that is the target of the operation process is loaded by the operation unit according to the timing of the operation process controlled by the operation control unit.
    Type: Application
    Filed: May 20, 2014
    Publication date: October 23, 2014
    Inventor: Noboru KOBAYASHI
  • Patent number: 8856408
    Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the circuitry including at least one input for receiving transaction requests; at least one output for outputting transaction requests; at least one path for transmitting the transaction requests between the input and the output. Control circuitry routes received transaction requests from the input to the output in response to a barrier transaction request. An ordering of at least some transaction requests is maintained with respect to the barrier transaction request within a stream of transaction requests passing along one of the at least one paths, by not allowing reordering of at least some of the transactions requests. The control circuitry includes a response signal generator, the response signal generator is responsive to receipt of the barrier transaction request to issue a response signal.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: October 7, 2014
    Assignee: ARM Limited
    Inventors: Peter Andrew Riocreux, Bruce James Mathewson, Christopher William Laycock, Richard Roy Grisenthwaite
  • Patent number: 8848532
    Abstract: A data processing method and system and relevant devices are provided to improve the processing efficiency of cores. The method includes: storing received packets in a same stream sequentially; receiving a Get_packet command sent by each core; selecting, according to a preset scheduling rule, packets for being processed by each core among the stored packets; receiving a tag switching command sent by each core, where the tag switching command indicates that the core has finished a current processing stage; and performing tag switching for the packets in First In First Out (FIFO) order, and allocating the packets to a subsequent core according to the Get_packet command sent by the subsequent core after completion of the tag switching, so that the packet processing continues until all processing stages are finished. A data processing system and relevant devices are provided. With the present invention, the processing efficiency of cores may be improved.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: September 30, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Lingyun Zhi, Linhan Li, Fei Song, Zuolin Ning
  • Patent number: 8843794
    Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: September 23, 2014
    Assignee: Intel Corporation
    Inventors: Christopher J. Nelson, Tak M. Mak, David J. Zimmerman, Pete D. Vogt
  • Publication number: 20140281061
    Abstract: The defined architecture allows for format-efficient data storage on bit-patterned media, while allowing for typical variations in the drive, such as reader to writer gap variations. The defined BPM architecture relaxes some timing requirements on real-time signaling from the formatter to the channel, while enabling bit-accurate alignment between data accesses and the media.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Jimmie Ray Shaver, Barmeshwar Vikramaditya
  • Patent number: 8838841
    Abstract: A data storage device accepts read and write commands with absolute command completion times based on queue-depth-of-one (qd=1) execution and stores them in an unsequenced commands memory. These commands are requests to access the data storage device and contain both locations on the storage medium where the data is located and whether the requested operation is read or write. For each pair of first and second commands in the memory, the time between execution of the first command and the second command is calculated and stored. A command selector then reads data from the memory based on a resequencing NCQ algorithm which inserts one or more commands from the command memory into the original qd=1 sequence whenever this insertion will not affect the execution time of commands in the original qd=1 sequence. The resequencing algorithm of the present invention increases IOPS and reduced read head actuator travel and wear.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: September 16, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Cyril Guyot, Timothy K. Tsai
  • Patent number: 8830992
    Abstract: The fabric card includes at least one fabric card chip and at least two fabric card connector groups, where each fabric card connector group of the at least two fabric card connector groups includes at least two fabric card connectors, the number of fabric card chips is less than the number of at least two fabric card connector groups, each fabric card chip of the at least one fabric card chip connects to all fabric card connectors in at least one fabric card connector group, all fabric card connectors in the fabric card connector group that connect to the fabric card chip exchange data using the fabric card chip. This fully utilizes an exchange capability of the fabric card chip and saves system resources.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: September 9, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Guoqiang Ma
  • Patent number: 8832487
    Abstract: In embodiments of a high-speed I/O data system, a first computer chip includes a data transmission system, and a second computer chip includes a data reception system. A data channel communicates an NRZ data signal, and a clock channel communicates a forwarded clock signal, from the data transmission system to the data reception system. The data transmission system includes a first differential serializing transmitter to generate the NRZ data signal from pulsed data, and further includes a second differential serializing transmitter to generate a forwarded clock signal. A first multi-phase transmit clock generator generates transmit clock signals for the first and second differential serializing transmitters. The data reception system includes a data receiver and a de-serializer to receive and de-serialize the NRZ data signal, and includes a multi-phase receive clock generator to generate receive clock signals from the forwarded clock signal for the de-serializing data receiver.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: September 9, 2014
    Assignee: Microsoft Corporation
    Inventor: Alan S. Fiedler
  • Patent number: 8832335
    Abstract: According to an embodiment, a control device includes a receiving unit configured to receive an interrupt request requesting an interrupt process to be executed by a processing device that executes one or more processes; a storage unit configured to store therein the interrupt request; a determining unit configured to determine a state of the processing device; a sending unit configured to send the interrupt request to the processing device; and a control unit configured to store the interrupt request received by the receiving unit in the storage unit when the processing device is determined by the determining unit to be in an idle state in which the processing device is not executing the processes and a predetermined condition is not satisfied, and to control the sending unit to send the interrupt request stored in the storage unit to the processing device when the predetermined condition is satisfied.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Shibata, Koichi Fujisaki, Tetsuro Kimura, Tatsunori Kanai, Haruhiko Toyama, Satoshi Shirai, Masaya Tarui, Hiroyoshi Haruki
  • Patent number: 8825924
    Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A plurality of read lines (18), write lines (20) and data lines (22) interconnect the computers (12). When one computer (12) sets a read line (18) high and the other computer sets a corresponding write line (20) then data is transferred on the data lines (22). When both the read line (18) and corresponding write line (20) go low this allows both communicating computers (12) to know that the communication is completed. An acknowledge line (72) goes high to restart the computers (12).
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: September 2, 2014
    Assignee: Array Portfolio LLC
    Inventor: Charles H. Moore
  • Patent number: 8825949
    Abstract: A method for regulating I/O requests in a RAID storage system may comprise: receiving a first request to access a first set of one or more logical block addresses (LBAs) of a RAID volume; receiving a second request to access at least one of the first set of one or more LBAs of the RAID volume; and queuing the second request. A system for regulating I/O requests in a RAID storage system may comprise: means for receiving a first request to access a first set of one or more logical block addresses (LBAs) of a RAID volume; means for receiving a second request to access at least one of the first set of one or more LBAs of the RAID volume; and means for queuing the second request.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: September 2, 2014
    Assignee: LSI Corporation
    Inventor: Kapil Sundrani
  • Patent number: 8825978
    Abstract: A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: September 2, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Meng Chaung, Chun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Nai-Ping Kuo