Abstract: A system and method for performing speculative writestream transactions in a computing system. A computing system including a plurality of subsystems has a requesting subsystem configured to initiate a writestream ordered (WSO) transaction to perform a write operation to an entire coherency unit by conveying a WSO request to a home subsystem of the coherency unit. The requester is configured to perform the write operation without first receiving a copy of the coherency unit and complete WSO transactions initiated in the order in which they are initiated. The home subsystem is configured to process multiple WSO transactions directed to a given coherency unit in the order in which they are received. When the requester initiates a WSO transaction to a given coherency unit, the coherency unit is locked. Responsive to receiving the WSO request, the home subsystem conveys a pull request for the write data to the requester.

Abstract: A data transfer control system includes a buffer controller that controls access to a data buffer and a transfer controller that controls data transfer between a PC connected to a BUS1 and the logical units LUN1 and LUN2 connected to a BUS2. The transfer controller includes: a command processing section that starts data transfer to or from the LUN1 based on a command indicated by an ORB for the LUN1 when the ORB is received, and starts data transfer to or from the LUN2 based on a command indicated by an ORB for the LUN2 when the ORB is receive; and a wait processing section that waits the processing of the ORB for the LUN2, when a bus reset occurs during the processing of the ORB for the LUN1 and the ORB for the LUN2 is received after the bus reset has occurred.

Abstract: Various types of resources of the disk array device are divided for respective users and communications resources used in remote copying are appropriately assigned to the users so that functional interference between the split units is prevented and stable remote copying is realized. SLPRs which are dedicated regions for the respective users are set inside the disk array device 10. Each SLPR is constituted by dividing various types of resources of ports, cache memories, logical units and the like, and cannot be accessed by an unauthorized host computer 1. Furthermore, a manager of one of the SLPRs likewise cannot refer to or alter the constructions of the other SLPRs. During remote copying, the amount of transfer within the unit time is detected for each of the SLPRs. If the amount of transfer within the unit time exceeds the maximum amount of transfer, a response to the host computer 1 from this SLPR is deliberately delayed, so that the inflow of data from the host computer 1 is restricted.

Abstract: A computer capable of playing real time applications includes a processing circuit configured to operate in a first power state, a second power state, and a third power state where the processing circuit consumes less power in the second state than in the first state, and less power in the third state than in the second state; and a real time subsystem coupled to the processing circuit, wherein the real time subsystem includes a buffer. The buffer is further configured to store data and output the data to an output device thereby enabling the processing circuit to enter the third power state while the buffer is outputting said data.

Abstract: An interrupt control device for issuing interrupts to a central processing unit (CPU) includes an object acquiring unit for acquiring data or resource(s) for use by the CPU and an interrupt issuing unit for issuing interrupts to the CPU. The interrupt issuing unit issues each interrupt to the CPU before the object acquiring unit actually acquires the data or the resource, but the interrupt indicates that the data or the resource is available. The interrupt control device further includes a use delay unit for delaying the use of the data or resource by the CPU unit until the object acquiring unit acquires the data or the resource if the CPU which has received the interrupt requests the use of the data or the resource before the object acquiring unit acquires the data or the resource. By adjusting the exact timing of the issuance of the interrupt according to the actual delays experienced by the CPU, the overall delays associated with interrupt handling are minimized.

Abstract: A system, method, and product are disclosed in a data processing system for serializing hardware reset requests in a software communication request queue in a processor card. The processor card processes software communication requests utilizing the queue in a serial order. A hardware reset request is received by the processor card and put in the queue. The hardware reset request is processed from the queue in the serial order with all requests from the queue that are currently being serviced have completed being serviced.

Abstract: The disclosed embodiments relate generally to remote server management technology. More particularly, the embodiments relate to improving the ability of remote server management tools to snoop large amounts of data, including graphical video data, from a communication bus. When snooping the communication bus for data, there is a risk that a storage device gathering the data will be overrun when the volume of relevant data snooped is high. The embodiments relate to a method and apparatus for passively throttling the communication bus to prevent overrun of devices storing snooped data.

Abstract: A processor disclosed herein comprises a clock configured to drive clock signals and a processor pipeline having a plurality of stages. The processor includes processor idling circuitry, which is configured within the stages and is responsive to an idle_request signal. A first stage comprises a device for stopping incoming instruction values from being further processed when the idle_request signal is received. Also, at least two of the remaining stages comprise idle_flag logic configured to receive the idle_request signal, the idle_flag logic further configured to transmit an idle_flag through the processor pipeline.

Abstract: The present invention describes a method and system for adjusting the rate of data transfer between a high-speed multi-channel tape drive and a slower-capability network interface. The present invention allows for selectively enabling/disabling active channels to adjust the data throughput to match the data transfer capabilities of the network interface. Such an adjustment optimizes the rate of data transfer between the system and the tape drive by reducing the amount of stop and start operations normally present in an environment where the network interface cannot support the high-speed data transfer rates of a tape drive. Such an enablement/disablement adjustment system allows for a greater range of varying data rates within the transfer.

Abstract: Disclosed is a technique for throttling data transfer. An amount of resources that are in use is determined. When the amount of resources reaches a high threshold, one or more primary control units are notified to temporarily stop sending data. When the amount of resources reaches a low threshold, each previously notified primary control unit is notified to resume sending data.

Abstract: A client driver requests data packet transfers from a peripheral device through a protocol stack and a host controller. The protocol stack receives the data transfer request and allocates the request into the host controller schedule. The host controller schedule requests the data of the peripheral device, and directs the received data into previously allocated buffers. The host controller then sends a signal to the client driver that the respective buffers are filled. The host controller can then deactivate the instructions in the host controller schedule until further notice so that the instructions do not need to be deleted from the schedule. The client driver extracts the data from the buffer, and sends a signal to the host controller that the buffer can be used again. The request in the host controller schedule can then be reactivated without having to necessarily re-insert new instructions into the host controller schedule.

Abstract: A system and method for pacing writes to a legacy peripheral device includes a control block configured to trap on the address of the legacy peripheral device and slows the rate that the CPU posts writes to avoid backpressure.

Abstract: A controller for a data recorder controls data recording to prevent buffer overrun errors. The data recorder emits a laser beam against a recording medium to record data. The data has a level that determines the power of the laser beam. When there is a possibility of a buffer overrun, the controller interrupts data recording. The controller interrupts data recording when the power of the laser beam is a low level and restarts data recording with the laser beam generated at the low level.

Abstract: A data recorder for writing data to a recording medium that prevents buffer underrun errors. An optical head generates a laser beam at a high power level when writing data on the recording medium and at a low power level when reading data from the medium. The writing of data is interrupted when there is a possibility of a buffer underrun error. When restarting data writing from where the interruption occurred, the laser beam is shifted from the low power level to the high power level before reaching the location at which the interruption occurred. This guarantees that the laser beam has the required power level when writing is restarted.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with the associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: A method and system for completing pending I/O device reads by periodically stalling the issuance of I/O device accesses by a program in a multiple-processor computer system.

Abstract: A data recording equipment that accurately restarts the writing of data to an optical disc after data recording is interrupted. The equipment interrupts recording when detecting an external shock or when predicting the occurrence of a buffer underrun error. The equipment includes a counter, which counts execution of recording data on the optical disc and generates a count value indicating the amount of data that is recorded, and a control unit, which is connected to the counter to hold the count value of the counter immediately before an interruption when the recording of data is interrupted. The unit re-irradiates a position on the optical disc, on which data prior to the data recorded immediately before the interruption is recorded. The init controls restart of the recording based on the held count value while recognizing the position of the data on the optical disc.

Abstract: A system and method for distributing a portion of the processing of a received packet among a plurality of service threads. When an ISR or similar process retrieves a packet from a communication interface via a receive descriptor ring, it places the packet on one of a plurality of service queues. Each queue has an associated service thread or process that initiates upper layer protocol processing for queued packets. The ISR may select a particular service queue based on the packet's communication flow or connection. Alternatively, the ISR may use a processor identifier provided by the communication interface to select a queue (e.g., in a multi-processor computer system). Or, other information provided by the interface may be used.

Abstract: A system and methods are shown for generating a transport stream. An application reads a transport stream file stored in memory. The application provides access to the transport stream file to a graphics card using a multimedia peripheral port (MPP). The MPP is used to provide data from the transport stream file to a transport stream demultiplexer. The application determines a desired transmission rate from the data present between program clock references in the transport stream file. The application suspends transmissions to the transport stream demultiplexer to allow a transmission bit-rate to match the desired bit-rate. The application also suspends transmission when the receiving transport demultiplexer determines its buffers are nearly full.

Abstract: Various types of resources of the disk array device are divided for respective users and communications resources used in remote copying are appropriately assigned to the users so that functional interference between the split units is prevented and stable remote copying is realized. SLPRs which are dedicated regions for the respective users are set inside the disk array device 10. Each SLPR is constituted by dividing various types of resources of ports, cache memories, logical units and the like, and cannot be accessed by an unauthorized host computer 1. Furthermore, a manager of one of the SLPRs likewise cannot refer to or alter the constructions of the other SLPRs. During remote copying, the amount of transfer within the unit time is detected for each of the SLPRs. If the amount of transfer within the unit time exceeds the maximum amount of transfer, a response to the host computer 1 from this SLPR is deliberately delayed, so that the inflow of data from the host computer 1 is restricted.

Abstract: In a system controller in which a plurality of CPUs connected through a shared bus are connected to a plurality of memory units or IO devices through a bus for separate transfer of a read instruction from a read data return, a CPU which has issued a new instruction and the destination of the instruction, and a CPU which has issued an instruction being suspended and the destination of the instruction are held, the issue order of the return data and the transfer instruction is maintained based on the held contents in a read time, and transfers, which are first serialized and transferred through the shared bus, are issued in parallel using a plurality of connection paths. Thus, the performance of the system controller using a plurality of CPUs can be successfully improved.

Abstract: System and method for transferring data to a device using double buffered data transfers. A host computer system couples to a data acquisition device. The device includes a first read buffer and a second read buffer for storing output data received from the host computer. The device reads first data from the computer and stores it in the first read buffer. The first data is transferred out from the first read buffer while the device reads second data from the computer and stores it in the second read buffer. The second data is transferred out from the second read buffer (after the transfer of the first data) while the device reads third data from the host computer and stores the third data in the first read buffer. Thus, the data acquisition device successively reads data into one read buffer concurrently with transferring data out from the other buffer, respectively.

Abstract: A system with a set of modules having synchronized timing. The synchronized timing of the modules enables precise coordination of measurements and stimuli for an arbitrary number of modules. The modules communicate and maintain time synchronization using a communication mechanism that may be adapted to localized positioning of modules and/or widely dispersed positioning of modules with no change to the underlying functionality in the modules.

Abstract: A method and apparatus is provided which dynamically alters SDRAM memory interface timings to provide minimum read access latencies for different types of memory accesses in a memory subsystem of a computer system. The dynamic alteration of the SDRAM memory interface timings is based on workload and is determined with information from the memory controller read queue.

Abstract: A method and device for parameter independent buffer underrun prevention in a data communication system includes a buffer for compensating for a difference in the rate of flow of data having a write port and a read port. After a commencement of writing data into the buffer, a predetermined delay time occurs. When the delay time has passed, reading data out from the buffer starts. Then the length of a time gap between the completion of writing data into the buffer and completion of reading data out from the buffer is determined. Finally, the length of the predetermined delay time is decreased by a first value if the length of the time gap is larger than a specified tolerance value and the length of the predetermined delay time is increased by a second value if the length of the time gap is smaller than the specified tolerance value. The provided method and device advantageously adjusts to systems having dynamically varying parameters, e.g.

Abstract: The invention relates to an operating method for a data bus for several parties with flexible, timed access. According to the method, the parties are synchronized, the bus messages are sent from the parties in a hierarchical sequence and are sent at least in part, only if necessary. A logic element is provided between the parties and the data bus which only gives bus access to each party when said party is allowed to send and for the duration of the send operation.

Abstract: A load on a CPU which controls the entire disk array device in an audio/video server which controls hard disk drives inside the disk array device is reduced. A recording/reproduction apparatus includes a plurality of recording/reproduction devices; a control device for issuing a command which instructs a recording/reproduction operation of each of the plurality of recording/reproduction devices and for setting information which specifies the enable/disable of an interrupt in such a manner as to correspond to each issued command; and a communication processing device for performing communication which transmits the command issued by the control device with each of the recording/reproduction devices and, after the communication for each command is terminated, for sending an interrupt indicating the termination of the communication to the control device under the condition in which the information which is set in such a manner as to correspond to the command specifies interrupt enable.

Abstract: In an image forming apparatus for forming an image in accordance with control codes stored in a plurality of memory media, when the control codes stored in the plurality of memory media to control the image forming apparatus is rewritten, rewrite execution codes adapted to execute rewrite of the control codes are transferred to predetermined one of the plurality of memory media from an external apparatus, and rewrite of the control codes is performed in accordance with the transferred rewrite execution codes.

Abstract: A structure and method for entering data into an electronic device (110). A deterministic data input element (130) coupled to the electronic device (110) is operable to accept a user-selected data input. Modulation of a motion of a non-deterministic data input element (140) coupled to the electronic device (11) is operable to select a varying precision of data input choices. A feedback element (120) coupled to one or more of the deterministic data input element (130) and the non-deterministic data input element (140) presents the data input choices to the user. The user enters data into electronic device (110) using one of the deterministic input element (130) and the non-deterministic input element (140) and the feedback element (120) displays a sequence of data choices to the user. The user then navigates a tree of possible data completions in order to select a particular data completion to be entered into the electronic device (110).

Abstract: An I/O control device that transfers data according to transfer control information, comprising a transfer control information memory means that stores transfer control information, a state detecting means that detects the processed state of the transfer control information stored in the transfer control information memory means, and a transfer control information memory control means by which new transfer control information is stored in the transfer control information memory means in place of the transfer control information upon completion of transfer control information-dependent transfer processing as a result of the detection by the state detecting means.

Abstract: In order to analyze the conditions leading to a stall or a wait state in a digital signal processing unit, READY signals, that are typically applied to the execution unit of a central processing unit, are applied to external conductors. The external conductors are applied to input terminals of a logic “AND” gate. The output terminals of the logic “AND” gate provided a logic “1” in a no-stall condition and a logic “0” in a stall condition. The output signals of the logic “AND” gate are stored in a memory unit and can be retrieved to determine when a stall condition occurred. The external conductors also apply the READY signal to a stall analyzer unit. The stall analyzer unit identifies the specific condition causing the stall condition by which external conductor has the logic “0” signal applied thereto. An indicia of this stall condition is stored in the memory unit.

Abstract: The use of enqueue operations to append multi-buffer packets to the end of a queue includes receiving a request to place a string of linked buffers in a queue, specifying a first buffer in the string and a queue descriptor associated with the first buffer in the string, updating the buffer descriptor that points to the last buffer in the queue to point to the first buffer in the string, and updating a tail pointer to point to the last buffer in the string.

Abstract: According to one aspect of the present invention, a method is provided in which a transmitting agent transfers data to a receiving agent at a specified transfer rate. Information relating to data transfer pauses requested by the receiving agent is maintained. The data transfer rate is dynamically adjusted based upon the pause information maintained.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with the associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: An information-processing device includes a bus, a plurality of processors connected to the bus, and a bus-control unit which detects whether an excessively retried address transaction is present. Each of the processors includes an issuing unit which issues address transactions, a monitoring unit which communicate with the bus-control unit, and a retry-control unit which controls the issuing unit to suspend or restrain issuance of address transactions, other than the excessively retried address transaction, and to put an already issued address transaction in a status of compulsory retry if the monitoring unit is informed of a presence of the excessively retried address transaction by the bus-control unit.

Abstract: The present invention is characterized by first performing the necessary rendering in the frame period, then during the remaining time of that frame period, rewriting the texture data in the texture buffer memory. The image rendering process for each frame is performed first, then after the rendering process has been completed for the frame, if there is remaining time, that time is used to rewrite the texture data. Therefore, the rendering process is not interrupted, the displayed image is not interrupted or frozen, and it is possible to rewrite the texture data in the small-capacity texture buffer memory and make it possible to use virtually a lot of texture data to render one scene.

Abstract: A digital system has a host processor 200 with a bus controller 210 and peripherals 220(0)-220(31) interconnected by an interconnect bus 230. 32 peripherals are share a common strobe line (nSTROBE[0]) on an embodiment of the interconnect bus in a first subdomain. Additional sub-domains, such as sub-domain 260, can be likewise connected to interconnect bus 230. Additional strobe lines nSTROBE(n) are used to select a particular sub-domain in response to an address presented to bus controller 210 by CPU 200. An interconnect bus transaction is synchronized in background so that a current cycle is not delayed. A first write cycle 1500 is completed as a no-wait state transaction, while immediately following second write cycle 1510 is delayed while synchronization circuit 1400 completes the synchronization of the first write cycle. nSTROBE pulse 1520 indicates first write transaction 1500 while nREADY pulse 1530 indicates the completion of a no-wait state first write transaction 1500.

Abstract: A method and apparatus for controlling the flow of information (e.g., graphics primitives, display data, etc.) to an input/output unit within a computer controlled graphics system. The system includes a processor having a first-in-first-out (FIFO) buffer, a separate input/output unit with its FIFO buffer, and a number of intermediate devices (with FIFO buffers) coupled between the input/output unit and the processor for moving input/output data from the processor to the input/output unit. Mechanisms are placed within an intermediate device which maintain an accounting of the number of input/output data sent to the input/output unit, but not yet cleared from the input/output unit's buffer. These mechanisms regulate data flow to the input/output unit. The system also includes an efficient return channel to minimizine the amount of data transfer bandwidth required in returning status information on the FIFO buffer of the input/output unit.

Abstract: In a network system in which a request of executing a process is sent from the higher level system to the lower level system, a time period of not executing a requested job is assured in the lower level system while assuring an asynchronism between the both systems and a certainty of the requested job. The higher level system transmits a pair of signals (a preparatory signal and an execution signal) to the lower level system in a predetermined interval after it holds a processing request to be sent to the lower system. The higher level system then resumes transmission of the processing request a predetermined time after transmitting the pair of signals.

Abstract: A microcomputer with a built-in flash memory includes a flash controller for controlling writing/erasing of the flash memory in accordance with a command from a CPU. The flash controller produces a CPU rewriting mode designating signal and a busy signal during writing/erasing of the flash memory. In response to the two signals, awaiting mode controller implements a waiting mode by outputting a control signal to open and close an AND gate using the control signal, thereby halting a supply of a clock signal to the CPU in the waiting mode. The microcomputer can reduce the load on software for writing/erasing of the flash memory, and the load on developing software.

Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. Interrupts are classified and processed accordingly when the processor is stopped by a debug event. While suspended for a debug event, a frame counter keeps track of interrupt debug state if multiple interrupts occur. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. Read/write transactions are qualified by an expected frame count to maintain correspondence between test host software and multiple debug/interrupt events.

Abstract: An improved microprocessor is provided having a program control unit for storing and then decoding instructions, a program address generation unit for generating addresses used to obtain instructions, an address register arithmetic unit for generating addresses for data, an arithmetic logic unit for performing operations on data, a shifter unit for shifting data in response to a predetermined instruction, a multiplier unit for performing multiplication of two input values; and a plurality of registers of which at least a portion are individually selectively associated with one or more of said units as a function of an instruction.

Abstract: A method and apparatus for reducing power consumption within a pipelined processor. In one embodiment, the method of the invention comprises defining an instruction which invokes a “sleep mode” within the processor and pipeline; inserting the instruction into the pipeline; decoding and executing the instruction, stalling the pipeline in response to the sleep mode instruction; disabling memory in response to the sleep mode instruction; and awaking the core from sleep mode based on the occurrence of a predetermined event. Methods for structuring core pipeline logic and extension instructions to reduce core power consumption under various conditions are described. Methods and apparatus for synthesizing logic implementing the aforementioned methodology are also disclosed.

Abstract: A process device couples to a process control loop. The process device receives process signals. A memory in the process device contains a nominal parameter value and a rule. Computing circuitry calculates a statistical parameter of the process signal and operates on the statistical parameter and the stored nominal value based upon the stored rule and responsively provides an event output based upon the operation. Output circuitry provides an output in response to the event output. The statistical parameter can be used in statistical process control systems.

Abstract: A SCSI bus phase status register is included in a parallel SCSI host adapter integrated circuit. Initially, the SCSI bus phase status register has a predefined value. When the parallel SCSI host adapter integrated circuit must wait for assertion of a request signal by a target device, e.g., an active request signal is expected by the host adapter integrated circuit, an on-chip sequencer executes a SCSI bus phase status register read instruction. When the SCSI bus phase status register is read and has the predefined value, an active pause signal is sent to the on-chip sequencer that causes the sequencer to suspend execution of the read instruction. When an active request signal is received from the target device, the SCSI bus phase status register is loaded automatically with a current SCSI bus phase a predefined period of time after the assertion of the request signal provided that an active parity error signal is not generated by the host adapter integrated circuit within the predefined period of time.

Abstract: A multiprocessor computer includes a processor disabling scheme which disables a processor that has been designated to boot the computer but fails to boot the computer. For computers having voltage regulator modules (VRMs) to power each processor, a control device directs a VRM associated with the failed boot processor to cease supplying power in response to the processor's failure. For computers without VRMs, a transistor controls the delivery of power from the power supply to each respective processor. If a designated boot processor fails to boot the system, the control device turns off the appropriate transistor to disable the failed processor.

Abstract: A controller interrupts and restarts writing data from a buffer memory to a medium and prevents buffer underrun errors. The controller includes an address memory for storing a recording medium address or a buffer memory address, which indicate the location of the data when the interruption occurred. A synchronizing circuit sequentially reads data from the recording medium and data from the buffer memory prior to the interruption while synchronizing the written data and the stored data. A restart circuit restarts writing data when the recording medium address or the buffer memory address matches the address stored in the address memory.

Abstract: A digital system has a host processor 200 with a bus controller 210 and peripherals 220(0)-220(31) interconnected by an interconnect bus 230. 32 peripherals are share a common strobe line (nSTROBE [0]) on an embodiment of the interconnect bus in a first subdomain. Additional sub-domains, such as sub-domain 260, can be likewise connected to interconnect bus 230. Additional strobe lines nSTROBE(n) are used to select a particular sub-domain in response to an address presented to bus controller 210 by CPU 200. A FIFO is provided on a peripheral device to reduce data transfer access time. When the FIFO is almost empty, a FIFO management state machine requests a DMA transfer by asserting the nDMA_REQ signal on the interconnect bus, thus transitioning from idle state 2300 to transfer state 2310 along arc 2301. The DMA controller transfers several data words until the FIFO becomes full, as indicated by word_cpt=FIFO_size.

Abstract: The present invention increases data transfer rate and reduces interrupt latency while avoiding a concomitant increase in interrupts to the host, by pacing the data flow between the UART and DSP using burst modes and wait modes.

Abstract: A method for sending a message from an application in one networked multi-tasking, paged computer to an application in another networked multi-tasking computer using programmed I/O. A communication link is first established between the two applications. The sending application then begins polling the communication link to determine when the communication link is available to send a message. When the communication link is available, the hardware associated with the sending application receives bytes of information until the application has been swapped out by an operating system or until the entire message has been received. If the entire message has been received, then it is sent to the other application. However, when the application is swapped out, the hardware sends the portion of the message that has already been received to the other application and continues retrieving information when the application is swapped back in.