Operation Scheduling Patents (Class 710/6)
  • Patent number: 10846098
    Abstract: An apparatus and method of data processing are provided. The apparatus comprises at least two execution pipelines, one with a shorter execution latency than the other. The execution pipelines share a write port and issue circuitry of the apparatus issues decoded instructions to a selected execution pipeline. The apparatus further comprises at least one additional pipeline stage and the issue circuitry can detect a write port conflict condition in dependence on a latency indication associated with a decoded instruction which it is to issue. If the issue circuitry intends to issue the decoded instruction to the execution pipeline with the shorter execution latency then when the write port conflict condition is found the issue circuitry will cause use of at least one additional pipeline stage in addition to the target execution pipeline to avoid the write port conflict.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: November 24, 2020
    Assignee: Arm Limited
    Inventors: Cédric Denis Robert Airaud, Luca Nassi, Damien Robin Martin, Xiaoyang Shen
  • Patent number: 10817181
    Abstract: An apparatus comprises a host device configured to communicate over a network with a storage system comprising a plurality of storage devices. The host device comprises a multi-path input-output driver configured to schedule input-output operations for delivery to the storage system over the network. The multi-path input-output driver is further configured to measure latencies of respective ones of a plurality of paths from the host device to the storage system, to schedule particular ones of the input-output operations for delivery to the storage system over particular ones of the paths based at least in part on the measured latencies, and to control transmission of the particular input-output operations over the particular paths in accordance with the scheduling.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: October 27, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Sanjib Mallick, Vinay G. Rao, Subin George, Arieh Don
  • Patent number: 10776753
    Abstract: Updating a data storage unit using tenant specific update policies is disclosed. In an embodiment, a plurality of application events from an events publisher is received at a data pipeline manager. The plurality of application events are associated with data at a source data storage unit and are stored at a data pipeline data storage unit. An update process is initiated, based on an update policy associated with a particular tenant. During the update process, one or more application events associated with the particular tenant are selected from among the plurality of application events stored at the data pipeline data storage unit. Data associated with the one or more selected application events is selected from the source data storage unit. Data selected from the source data storage unit is stored at a target data storage unit.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: September 15, 2020
    Assignee: XACTLY CORPORATION
    Inventors: Vasudev Krishnamoorthy, Tony Wang, Denis Gefter, Ron Rasmussen
  • Patent number: 10564895
    Abstract: An infrastructure, method and controller card for managing flash memory in a storage infrastructure. A system is provided that includes flash memory; and a controller that includes: an I/O request handler for handling standard read and write (R/W) operations requested from a host; a garbage collection (GC) system that performs a GC process on the flash memory in response to a threshold condition, wherein the GC process includes GC-induced R/W operations; and a scheduler that interleaves standard R/W operations with GC-induced R/W operations, wherein the scheduler calculates minimum and maximum boundaries for GC-induced R/W operations for a GC process based on an estimated GC latency.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: February 18, 2020
    Assignee: SCALEFLUX, INC.
    Inventors: Qi Wu, Duy Nguyen, Prathamesh Amritkar, Qing Li
  • Patent number: 10423414
    Abstract: In an embodiment, a device including a processor, a plurality of hardware accelerator engines and a hardware scheduler is disclosed. The processor is configured to schedule an execution of a plurality of instruction threads, where each instruction thread includes a plurality of instructions associated with an execution sequence. The plurality of hardware accelerator engines performs the scheduled execution of the plurality of instruction threads. The hardware scheduler is configured to control the scheduled execution such that each hardware accelerator engine is configured to execute a corresponding instruction and the plurality of instructions are executed by the plurality of hardware accelerator engines in a sequential manner. The plurality of instruction threads are executed by plurality of hardware accelerator engines in a parallel manner based on the execution sequence and an availability status of each of the plurality of hardware accelerator engines.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: September 24, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ajit Deepak Gupte, Mahesh Mehendale, Navin Acharya, Mel Alan Phipps
  • Patent number: 10394728
    Abstract: A processor includes a core and an interrupt controller. The interrupt controller includes logic to read interrupt data from a memory, the interrupt data including a timestamp, an allowable delay value, and at least one interrupt vector. The interrupt controller also includes a delay-comparison circuit to determine a time lapse based on the timestamp and a system clock signal and to compare the time lapse to the allowable delay value. Further, the interrupt controller includes a second logic to determine whether to invoke an interrupt handler based on the comparison of the time lapse to the allowable delay value.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventor: Yen Hsiang Chew
  • Patent number: 10387036
    Abstract: A semiconductor memory device according to the present disclosure includes: a memory cell array including a plurality of planes; a command processing unit configured to generate an internal command to be executed by at feast one plane among the plurality of planes on the basis of external commands received from an external controller; a status register configured to store status information of the external commands by a tag included in the external command according to results of performing the internal command.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventor: Beom Ju Shin
  • Patent number: 10348796
    Abstract: A processor performing functions of a video client may measure an occupancy of a video buffer, select a video chunk having a first video encoding bitrate based upon the occupancy, and provide a deadline for a delivery of the video chunk to a multipath transport layer module. The processor may further activate a deadline aware scheduler of the module when the occupancy exceeds a first threshold and when the deadline aware scheduler was previously disabled, and deactivate the deadline aware scheduler when the occupancy falls below a second threshold and when the deadline aware scheduler was previously enabled. The module may request packets of the video chunk from a video server and select at least one active interface for the video server to send each packet. The deadline aware scheduler may select whether a secondary network interface is to be an active interface or a non-active interface.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: July 9, 2019
    Assignees: AT&T Intellectual Property I, L.P., Indiana University Research and Technology Corporation
    Inventors: Bo Han, Lusheng Ji, Vijay Gopalakrishnan, Feng Qian
  • Patent number: 10338830
    Abstract: The invention introduces a method for accessing a solid state disk for QoS (Quality of Service), performed by a processing unit, including at least the following steps: obtaining execution histories of VMs (virtual machines); selecting one of the FIFO (First-In-First-Out) queues according to the execution histories and QoS; obtaining a first data access request, which was entered earliest in the selected FIFO queue; and directing a storage device to complete a data access operation according to the first data access request.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: July 2, 2019
    Assignee: SHANNON SYSTEMS LTD.
    Inventors: Zhen Zhou, Ningzhong Miao
  • Patent number: 10270861
    Abstract: The various embodiments herein provide a method and system for dual role handling between at least two devices in a wireless environment. The method comprises seeking, by a first device, at least one device with a specified connection topology, establishing a connection with a second device having a same connection topology, establishing an Application service platform (ASP) session with the second device once the connection is established between the first device and the second device, sending, by the first device, a role negotiation message comprising a request for role change to the second device, wherein the role negotiation message corresponds to a WSB message, receiving a custom message for confirmation, if the second device accepts the role change, and changing the connection topology between the first device and the second device once the role negotiation between the first device and the second device is completed.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: April 23, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Mayuresh Madhukar Patil, Venkateswar Jeedigunta, Jong-Hyo Lee, Karthik Srinivasa Gopalan
  • Patent number: 10241835
    Abstract: A storage resource scheduling method and a storage and computing system, where the storage and computing system has a computing system and a storage system, the computing system has at least one computing unit, and the storage system has at least one storage unit. The method executed by the computing system includes: identifying a task type of a computing unit in the at least one computing unit; sending task type information to the storage system, where the task type information carries the task type; acquiring a scheduling policy of the task type according to the task type information; and scheduling, according to the scheduling policy, a storage unit corresponding to the computing unit. In the method, different tasks of a computing unit are perceived, and resource scheduling is performed according to a task type, thereby implementing scheduling and management on different tasks of a same storage unit.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: March 26, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Li Wang
  • Patent number: 10209990
    Abstract: A conditional fetch-and-phi operation tests a memory location to determine if the memory locations stores a specified value and, if so, modifies the value at the memory location. The conditional fetch-and-phi operation can be implemented so that it can be concurrently executed by a plurality of concurrently executing threads, such as the threads of wavefront at a GPU. To execute the conditional fetch-and-phi operation, one of the concurrently executing threads is selected to execute a compare-and-swap (CAS) operation at the memory location, while the other threads await the results. The CAS operation tests the value at the memory location and, if the CAS operation is successful, the value is passed to each of the concurrently executing threads.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: February 19, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David A. Wood, Steven K. Reinhardt, Bradford M. Beckmann, Marc S. Orr
  • Patent number: 10191691
    Abstract: Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage platform includes one or more data storage modules each comprising storage drives coupled over a Peripheral Component Interconnect Express (PCIe) fabric with at least one processing module that receives storage operations directed to the one or more data storage modules over one or more network interfaces. The processing module is configured to assign service levels in a queue to the storage operations that are received over the one or more network interfaces. Based at least on the service levels, the processing module is configured to service the storage operations from the queue with the one or more data storage modules over the PCIe fabric.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: January 29, 2019
    Assignee: Liqid Inc.
    Inventors: Phillip Clark, James Scott Cannata, Jason Breakstone
  • Patent number: 10169948
    Abstract: Storage operation requests from any device of a computing environment can be numerous and frequent. In particular, if there is a high frequency initiation of storage operation requests to store, retrieve, or modify data, then targeted storage systems have to easily and quickly decide in which order to satisfy the storage operation requests, such as when two requests occur to retrieve identical data. Storage operation requests can be prioritized at the end device instead of any intermediary device or enabling a complex ordering algorithm. Moreover, the storage on a cloud model consists of similar storage services which serve consumers of different needs. Some applications/users can afford longer service time than other applications/users. Differentiation in required service time allows price differentiation. The solution will serve premium customers faster than it serves customers who paid less.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mudi M Fluman, Yaacov Frank, Janice M Girouard, Yehuda Shiran
  • Patent number: 10163135
    Abstract: Data storage devices and methods to combine user content with supplemental content at a data storage device are disclosed. The data storage device includes a host interface, a controller coupled to the host interface, a first storage area coupled to the controller, and a second storage area coupled to the controller. The host interface is configured to enable the data storage device to receive one or more user content items from a host device when the data storage device is operationally coupled to the host device. The controller is configured to store the one or more user content items in the first storage area. The controller is also configured to combine a particular supplemental content item stored in the second storage area with a particular user content item from among the one or more user content items.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: December 25, 2018
    Assignee: SANDISK IL LTD.
    Inventor: Rafi Ben-Rubi
  • Patent number: 10146695
    Abstract: An apparatus includes a memory and a processor coupled to the memory. The processor is configured to perform the steps of: receiving a first head link for a page invalidation chain, the page invalidation chain including a plurality of page invalidation tables (PITs); receiving a second head link for an active real page table (RPT) chain, the active RPT chain including a plurality of RPTs; accessing a PIT, wherein the PIT includes a first data structure and a second data structure; invalidating the one or more RPTs, whereas the one or more RPTs are invalidated simultaneously in a batch; and releasing the one or more RPTs to a free RPT chain, the free RPT chain includes a plurality of released RPTs.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: December 4, 2018
    Assignee: UNISYS CORPORATION
    Inventors: David W Schroth, Kerry M Langsford, Max J Heimer, Michael J Rieschl
  • Patent number: 10067888
    Abstract: Providing I/O operations to a storage device includes selecting a portion of original I/O operations based on a first set of criteria, determining whether to subdivide each of the portion of original I/O operations that are selected according to a second set of criteria different than the first set of criteria, and converting each of the original I/O operations selected for subdivision into a plurality of subdivided I/O operations for different portions of data for a corresponding one of the original I/O operations, where at least two of the different portions are from a single track of data on the storage device. The first set of criteria may include whether the I/O operations are for multiple tracks of data and whether the storage device supports subdividing a single track. The second set of criteria may include determining a measured amount of performance improvement for previous subdivision operations.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: September 4, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Douglas E. LeCrone, Paul A. Linstead
  • Patent number: 10055253
    Abstract: A method includes, in a processor, receiving first and second operations for periodic execution with respective specified time periods. Respective actual time periods having no common divisor are derived from the specified time periods. The first and second operations are executed periodically with the respective actual time periods.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: August 21, 2018
    Assignee: Mellanox Technologies, Ltd.
    Inventor: Itai Baz
  • Patent number: 10055170
    Abstract: A method for execution by a dispersed storage and task (DST) execution unit includes generating low-load prediction data, which includes selecting a time period corresponding to a predicted low-load, based on a plurality of historical load samplings. Maintenance task scheduling data is generated based on the low-load prediction data. Generating the maintenance task scheduling data includes assigning a maintenance task to a scheduled time that is within the time period corresponding to the predicted low-load. The maintenance task is executed at the scheduled time.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason K. Resch, Ethan S. Wozniak
  • Patent number: 10027969
    Abstract: A parallel decoder for decoding compressed video picture data including inter-coded picture item data with motion vector data. A decoding module decodes picture data stored in a temporary storage. The decoding module includes an inter-prediction module that uses inter-prediction item data to decode an inter-coded picture item by referring to already decoded reference picture item data. The structure of inter-prediction item data in the temporary storage is a function of the positions of corresponding reference picture items. The decoding order of stored inter-prediction item data by the inter-prediction module is prioritized as a function of a decoding order of reference picture item data.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: July 17, 2018
    Assignee: NXP USA, INC.
    Inventors: Hongzhang Yang, Chaofan Huang, Peng Zhou
  • Patent number: 10007438
    Abstract: A computing device having interface, memory, and processing module, transmits write requests for a set of encoded data slices to storage units (SUs) of a dispersed storage network (DSN) based on a write request process and to receive proposal records for a subset of the set of encoded data slices from at least some of the SUs. The computing device interprets the proposal records to determine whether it or any another computing device has a threshold number of its respective write requests in a first priority position in the ordered list of pending write requests. When no computing device has the threshold number, the computing device determines whether any computing device can be blacklisted and/or eliminated and whether a winner of the ballot can be determined after such determination. When a winner is determined, the computing device transmits finalize commands to the storage units.
    Type: Grant
    Filed: June 25, 2016
    Date of Patent: June 26, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Greg R. Dhuse, Ravi V. Khadiwala, Ethan S. Wozniak
  • Patent number: 9990137
    Abstract: Providing I/O operations to a storage device includes selecting a portion of original I/O operations based on a first set of criteria, determining whether to subdivide each of the portion of original I/O operations that are selected according to a second set of criteria different than the first set of criteria, and converting each of the original I/O operations selected for subdivision into a plurality of subdivided I/O operations for different portions of data for a corresponding one of the original I/O operations. The first set of criteria may include whether the I/O operations are for multiple tracks of data. The second set of criteria may include determining a measured amount of performance improvement for previous subdivision operations. Performance of subdivided I/O operations may be monitored. A number of subdivided I/O operations may be limited by a number of available parallel I/O routes.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: June 5, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Douglas E. LeCrone, Paul Linstead
  • Patent number: 9983831
    Abstract: A system and method for providing consistent performance in a storage device, such as a solid state drive. A threshold value for command execution time for a command in a category of command (e.g., a read command or a write command) and a command size, is stored in the storage device. When a host command in the category (e.g., a read command) and corresponding size is received, the storage device executes the command, and if it completes execution of the command in a time that is less than the threshold value, the solid state drive waits until an amount of time equal to the threshold value has elapsed before sending the command completion.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: May 29, 2018
    Assignee: NGD SYSTEMS, INC.
    Inventors: Joao Alcantara, Ricardo Cassia, Kamyar Souri, Vladimir Alves, Guangming Lu
  • Patent number: 9986576
    Abstract: Network devices are steered to preferred access points using a probability function. A probe request for connection is received from a network device. The probe request can be from a network device attempting to use a wireless network (e.g., a IEEE 802.11-type network or other suitable type of network). A probability function that defines a likelihood of granting the network device a connection is used to determine whether to accept or deny the response. The probe response is then sent to the network device.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: May 29, 2018
    Assignee: Fortinet, INC
    Inventors: Sung-Wook Han, Mohan Ram
  • Patent number: 9910524
    Abstract: An electronic device detects a change in intensity of an input on an input element that includes detecting an increase in intensity followed by a decrease in intensity, and recognizes at least a portion of the change in intensity of the input as a first input event that is associated with a first operation, for example a single click operation. After recognizing the first input event, the device delays performance of the first operation while monitoring subsequent changes in intensity of the input for a second input event, wherein the delay is limited by a default delay time period. If the second event is recognized before default delay time period has elapsed, a second operation is performed and the first operation is not performed. However, if early-confirmation criteria for the first input event are met before the default delay period elapses, the first operation is performed.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: March 6, 2018
    Assignee: APPLE INC.
    Inventors: Nicole M. Wells, Leah M. Gum, Kenneth L. Kocienda, Camille Moussette, Jean-Pierre M. Mouilleseaux, Joshua B. Kopin, Jules K. Fennis
  • Patent number: 9906062
    Abstract: Methods, systems, and apparatuses for charging a host device from a charging source through an accessory are described. Upon detecting an input power signal from the charging source, an accessory may send an identification request to the host device and authenticate the host device based on the identification information received from the host device. Upon authenticating the host device, the accessory may enable a power path between the charging source and the host device to supply a charging current to charge the host device.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: February 27, 2018
    Assignee: APPLE INC.
    Inventors: Jeffrey J. Terlizzi, Jonathan J. Andrews, Alexei Kosut, James M. Hollabaugh, Zachary C. Rich, Daniel J. Fritchman
  • Patent number: 9891866
    Abstract: Methods and systems are described herein to provide efficient data retrieval in a data storage system. Specifically, in cases where users of a data storage system are not overly sensitive to data retrieval time, such as the case for backup and archival data storage systems, random read requests may be fulfilled as part of sequential reads to reduce I/O operations. A data storage system may be divided into data storage zones. Sequential reads may be performed for data stored in those data storage zones with pending data retrieval requests. Data retrieval requests may be fulfilled based at least in part on the sequentially-read data.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: February 13, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Colin L. Lazier, Kestutis Patiejunas
  • Patent number: 9870414
    Abstract: Methods, systems, and computer program products are provided for performing a secure delete operation in a wide area network (WAN) including a cache site and a home site. A method includes identifying a file for deletion at the cache site, determining whether the file has a copy stored at the home site, detecting a location of the copy at the home site prior to a disconnection event of the cache site from the home site, deleting the file from the cache site during the disconnection event, and in response to the secure deletion of the file not being complete during the disconnection event, indicating on a table a remote inode number assigned to the copy associated with the file at the home site, a name under which the copy is saved, and a list of data chunk tuples specifying selected data of the copy to undergo secure deletion.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: January 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence C. Blount, Deepak R. Ghuge, Shah Mohammad R. Islam, Sandeep R. Patil, Riyazahamad M. Shiraguppi, Renu Tewari
  • Patent number: 9811574
    Abstract: Various of the disclosed embodiments present systems and methods for generating consolidated job postings from disparate originating sources and formats. Applying an Extraction Transform Load (ETL) framework to the incoming data, a parallel and asynchronous as well as scalable approach to distributing job posting information is presented. “Extraction” may involve the recognition of salient information in the disparate formats (e.g., in employment listings on company webpages). During “transformation”, the information may be reformatted into a universal format or into a format suitable for use at a given destination system. During “loading”, the reformatted data may be supplied to a suitable destination system, e.g., the Application Programming Interface (APIs) of a job board system. Applications in related domains and various optimizations are also discussed.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: November 7, 2017
    Assignee: Work4Labs, Inc.
    Inventors: Maxime Verger-Del Bove, Paul Clais, Olivier Le Floch
  • Patent number: 9811283
    Abstract: A system includes: input-output devices including a first input-output device having a first input-output characteristic and a second input-output device having a second input-output characteristic, and a control device. The control device is configured to when jobs include a first job in which a ratio between reading and writing included in the first job is more suitable for the first input-output characteristic than the second input-output characteristic, a second job having a dependency relationship with the first job and in which a ratio between reading and writing included in the second job is more suitable for the second input-output characteristic than the first input-output characteristic, and a third job having a dependency relationship with neither the first job nor the second job, control submitting order of the jobs into nodes, coupling the input-output devices and the nodes, and copying of execution result data by the jobs between the input-output devices.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: November 7, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Takatsugu Ono
  • Patent number: 9792059
    Abstract: An apparatus, method and computer program in a distributed cluster storage network comprises storage control nodes to write data to storage on request from a host; a forwarding layer at a first node to forward data to a second node; a buffer controller at each node to allocate buffers for data to be written; and a communication link between the buffer controller and the forwarding layer at each node to communicate a constrained or unconstrained status indicator of the buffer resource to the forwarding layer. A mode selector selects a constrained mode of operation requiring allocation of buffer resource at the second node and communication of the allocation before the first node can allocate buffers and forward data, or an unconstrained mode of operation granting use of a predetermined resource credit provided by the second to the first node and permitting forwarding of a write request with data.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: October 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Carlos F. Fuente, John E. Lindley, William J. Scales
  • Patent number: 9792051
    Abstract: An input output scheduler. The scheduler runs in user space and is associated with one core of a multi-core central processing unit. Applications submit input output commands to the scheduler, which queues the input output commands and submits them in batches to a mass storage device. The input output scheduler may include a plurality of command queues with different batching strategies configured to provide, e.g., different performance characteristics as measured, for example, by latency or input output throughput.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: October 17, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Fei Liu, Yang Seok Ki, Aakanksha Pudipeddi
  • Patent number: 9794316
    Abstract: Disclosed are a method and a system for content management, the method comprises: a master control server allocates, for contents to be issued, one or more merged file blocks and a storage location of each content in its corresponding merged file block according to a received content issue request, and sends to a media storage-and-forward server a content download request containing one or more names of the one or more merged file block and the storage location of each content; the media storage-and-forward server downloads the content to be issued according to the content download request, and stores each downloaded content in the corresponding storage location of the corresponding merged file block. The solutions save the storage space of the file system, improve the storage efficiency of the file system, and reduce the storage cost of the file system.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: October 17, 2017
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO. LTD
    Inventor: Li Dong
  • Patent number: 9779003
    Abstract: Methods, apparatus and computer program products implement embodiments of the present invention that include detecting, by a storage system, a change in a mapping of a logical volume to one or more host ports of a host computer communicating with the storage system via a storage area network (SAN). Subsequent to detecting the change, first and second input/output (I/O) requests for the logical volume are received from a given host port, and a first unit attention message is conveyed to the given host port in response to the first I/O request. A second unit attention message is conveyed to the given host port upon determining that the storage system received the second I/O request within a specific time period commencing upon receiving the first I/O request. However, the second I/O request can be performed if the storage system received the second I/O request subsequent to the specific time period.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: October 3, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oren Li-On, Orit Nissan-Messing, Assaf Nitzan, Eyal Perek
  • Patent number: 9720601
    Abstract: A technique for load balancing uses heuristic-based algorithms with respect to input/output (I/O) latency of workloads destined to storage devices, e.g., solid state drives (SSDs), of a storage array attached to a storage system. Illustratively, “front-end” requests received from a host result in a back-end workload as those requests are processed by a storage I/O stack of the storage system and stored on the storage array. Accordingly, the technique maintains a consistent latency for the host requests (front-end) to control latency for the back-end workload. The load balancing technique illustratively load balances fixed (back-end) workloads having similar I/O sizes and I/O patterns. Illustratively, the technique balances the workloads across a plurality of storage ports over one or more I/O paths to the SSDs. Access to the SSDs may then be distributed among the storage ports.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: August 1, 2017
    Assignee: NetApp, Inc.
    Inventors: Anish Gupta, Samiullah Mohammed, Jamie Nguyen, Hung Lu
  • Patent number: 9710302
    Abstract: According to one exemplary embodiment, a method for dynamically timing out a first process within a plurality of suspended processes is provided. The method may include determining that a second process is attempting to suspend. The method may also include determining if a number of suspended processes plus one is less than a threshold value. The method may then include selecting the first process within the plurality of suspended processes to prematurely time out based on determining that the number of suspended processes plus one is not less than the threshold value. The method may further include timing out the selected first process. The method may also include suspending the second process.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: July 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Andrew P. Bates, Fraser P. Bohm, Pradeep Gohil, Anthony P. Papageorgiou
  • Patent number: 9703597
    Abstract: According to one exemplary embodiment, a method for dynamically timing out a first process within a plurality of suspended processes is provided. The method may include determining that a second process is attempting to suspend. The method may also include determining if a number of suspended processes plus one is less than a threshold value. The method may then include selecting the first process within the plurality of suspended processes to prematurely time out based on determining that the number of suspended processes plus one is not less than the threshold value. The method may further include timing out the selected first process. The method may also include suspending the second process.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Andrew P. Bates, Fraser P. Bohm, Pradeep Gohil, Anthony P. Papageorgiou
  • Patent number: 9684494
    Abstract: A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: June 20, 2017
    Assignee: ROCKETICK TECHNOLOGIES LTD.
    Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher, Ronen Gal
  • Patent number: 9672067
    Abstract: A data processing system comprises a storage device, an interface module and a scheduler. The interface module is configured to dispatch a non-prioritized request via a first data path, and to transfer application-level information of an application via a second data path. The scheduler, coupled to the first and second data path, is configured to enable an access to the storage device according to the non-prioritized request and the application-level information respectively received from the first and second data paths.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: June 6, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ye-Jyun Lin, Hsiang-Pang Li, Shang-Xuan Zou, Chia-Lin Yang
  • Patent number: 9524307
    Abstract: Systems and methods perform asynchronous error checking on a structured document. In accordance with the systems/methods, a first thread, such as a main application thread of a document editor, parses the document to identify one or more new elements included therein and create copies of the one or more new elements. A second thread, such as a background thread, applies error checking to the copies of the one or more new elements to generate error results corresponding to the one or more new elements. The first thread the uses the error results to indicate errors in association with the one or more new elements.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 20, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Mikhail Arkhipov
  • Patent number: 9477586
    Abstract: Memory controller circuitry may process the memory access requests by reordering the sequence of requests. Reordering the sequence of requests may decrease the power consumption of the memory controller and system memory associated with the memory controller. The memory controller may operate in at least an unconstrained power mode, a priority mode, and a constrained power mode. In the unconstrained power mode, the memory controller may process memory access requests at elevated and power consumption levels. In the priority mode, the memory controller may process memory access requests from select sources with reduced power consumption. In the constrained power mode, the memory controller may process all memory access requests at reduced power consumption levels. Capacitive-model based power monitoring circuitry may be used to monitor the interactions between the memory controller and the system memory to dynamically adjust the operating mode of the memory controller.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: October 25, 2016
    Assignee: Altera Corporation
    Inventors: Sam Hedinger, Philip Clarke
  • Patent number: 9477595
    Abstract: Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: October 25, 2016
    Assignee: Virident Systems Inc.
    Inventors: Vijay Karamcheti, Ashish Singhai, Shibabrata Mondal, Ajith Kumar
  • Patent number: 9378052
    Abstract: Improved techniques of implementing range lock involve granting a sleeping thread access to an address range when no conflicts exist with earlier pending requests as well as with already granted requests. Along these lines, a current child thread that has a conflict with a parent thread that currently holds a range lock on a range of bytes during a read/write operation will be awoken from waiting state when the parent thread has completed its access and releases its lock. In response, the processor compares the range to which the current child thread request access with the ranges to which other sleeping threads request access. However, the comparisons are only performed in connection with (i) requests that arrived prior to the current child thread and (ii) other granted requests.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: June 28, 2016
    Assignee: EMC Corporation
    Inventors: Ruiling Dou, Feng Zhang, Ying Hu, Gong Chen, Hao Pan
  • Patent number: 9323663
    Abstract: Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: April 26, 2016
    Assignee: Virident Systems Inc.
    Inventors: Vijay Karamcheti, Ashish Singhai, Shibabrata Mondal, Ajith Kumar
  • Patent number: 9256521
    Abstract: A controller comprising a transport layer, an internal memory, and a link list manager block. The internal memory stores pending instruction entries. The link list manager block is configured to read instructions stored in an external memory, update an active vector, the active vector for storing indications of instructions from the external memory; update the pending instruction entries in the internal memory; and update the instructions stored in the external memory. The link list manager block configured to dispatch a instruction from the pending instruction entries in the internal memory to the transport layer.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: February 9, 2016
    Assignee: PMC-Sierra US, Inc.
    Inventors: Raymond Lam, Ivy Chow
  • Patent number: 9224077
    Abstract: A control apparatus includes an operation section, a correction section, and a controller. The operation section performs an operation for forming an image having a predetermined density. The correction section corrects a value of the density. In a case where an image formation condition is switched from a first image formation condition to a second image formation condition, when image formation under the second image formation condition is to be performed on at least a predetermined number of recording media or to be performed for at least a predetermined period, the controller performs control so that the correction section executes a process of correcting the value. When the image formation is not to be performed on at least the predetermined number of recording media or not to be performed for at least the predetermined period, the controller performs control so that the correction section does not execute the process.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: December 29, 2015
    Assignee: FUJI XEROX CO., LTD.
    Inventor: Satoshi Tanaka
  • Patent number: 9223579
    Abstract: In one embodiment, the present invention includes a method for receiving a non-coherent atomic request from a device coupled to an agent via a non-coherent link, accessing a mapping table of the agent to convert the non-coherent atomic request into a coherent atomic request, and transmitting the coherent atomic request via a coherent link to a second agent coupled to the agent to cause the second agent to be a completer of the non-coherent atomic request. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventor: Ramakrishna Saripalli
  • Patent number: 9182923
    Abstract: The storage system includes a progress status detection unit that detects respective progress statuses representing proportions of the amounts of processing performed by respective processing units to the amount of processing performed by the entire storage system, each of the processing units being implemented in the storage system and performing a predetermined task; a target value setting unit that sets target values of processing states of the processing units, based on the detected progress statuses of the respective processing units and ideal values of the progress statuses which are preset for the respective processing units; and a processing operation controlling unit that controls the processing states of the processing units such that the processing states of the processing units meet the set target values.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: November 10, 2015
    Assignee: NEC CORPORATION
    Inventors: Piotr Skowron, Marek Biskup, Lukasz Heldt, Cezary Dubnicki
  • Patent number: 9143403
    Abstract: Example embodiments relate to autonomous metric tracking and adjustment. In some examples, a computing node may include a processor to run a main operating system and an application that runs on top of the main operating system. The computing node may include a hardware-level controller that dynamically adjusts individual hardware components of the computing node via control signals that do not pass through the main operating system. The adjustments may be based on a target metric from a scheduling service external to the computing node and individual performance metrics from the computing node.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: September 22, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paolo Faraboschi, Dejan S Milojicic, Dwight L Barron
  • Patent number: 9128796
    Abstract: A system and method for updating an accessory device are described. A software upgrade for upgrading an accessory device is received from a wireless network at a wireless device. In response, it is automatically determined at the wireless device whether the accessory device is in communication with the wireless device. Upon determining that the accessory device is in communication with the wireless device, the software upgrade is forwarded from the wireless device to the accessory device to enable upgrade of the accessory device according to the software upgrade.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 8, 2015
    Assignee: Cellco Partnership
    Inventors: Monica Chitre, Yoganand Rajala