Input/output Command Process Patents (Class 710/5)
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Patent number: 11689915Abstract: Systems and methods for 5G telecommunication call event timestamping to assist in debugging the flow of call events, such as during roaming, handover operations, or when user equipment (UE) accesses a different network slice. Specifically, a system for the provision of wireless telecommunication services can include a core network having a first UDR and a first UDM. The first UDM, upon receiving communication from one or more network functions, can communicate a first message to the first UDR. The first message can include a first timestamp indicating to the first UDR a first time that the first message was transmitted.Type: GrantFiled: March 9, 2021Date of Patent: June 27, 2023Assignee: T-Mobile Innovations LLCInventors: Anil Kumar Mariyani, Rajil Malhotra, Anuj Sharma
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Patent number: 11681550Abstract: Systems and methods for threaded computing systems using allocated command identifier pools for command management are described. Command requests for different processing threads are received. Based on the thread assigned to process the command request, command identifiers are assigned from different pools of command identifiers for each thread, where each pool contains non-overlapping sets of command identifiers. The command identifiers are returned to the same pool that the command identifier came from upon completion of each command.Type: GrantFiled: February 16, 2021Date of Patent: June 20, 2023Assignee: Western Digital Technologies, Inc.Inventors: Albert Vainer, Itay Presiado, Ido Naveh
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Patent number: 11678017Abstract: Disclosed is an electronic device capable of increasing a recognition rate of an external device. The electronic device includes an interface circuitry configured to be connected to an external device; and a processor configured to: identify a characteristic of the connected external device; obtain identification information of the connected external device based on the identified characteristic of the connected external device and a recognition model learning a relation between characteristics of a plurality of external devices and identification information of the plurality of external devices; and perform an operation based on the identification information of the connected external device.Type: GrantFiled: November 5, 2020Date of Patent: June 13, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Byuksun Kim
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Patent number: 11675541Abstract: A memory device includes a command interface configured to receive a command from a host device via multiple command address bits. The memory device also includes a centralized command decoder configured to receive the command and to determine whether the command matches a bit pattern corresponding to multiple command types, such as a write command and a read command. The centralized command decoder is also configured to, in response to the command matching the bit pattern, asserting a latch signal. The memory device also includes a latch configured to capture the multiple command address bits based at least in part on assertion of the latch signal.Type: GrantFiled: October 20, 2021Date of Patent: June 13, 2023Assignee: Micron Technology, Inc.Inventor: Liang Chen
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Patent number: 11669470Abstract: The present disclosure provides a storage system including a first storage device (e.g., a main storage device) and one or more additional storage devices (e.g., sub storage devices). The first storage device includes a host interface for communicating with a host device and is directly connected to the host device. The additional storage devices may be directly connected to the first storage device and may communicate with the host device through the host interface included in the first storage device. The storage system thus has a total combined capacity of both the capacity of the first storage device and the capacity of the one or more additional storage devices. Further, the one or more additional storage devices may be added or removed to increase or decrease the total capacity of the storage system, and the one or more additional storage devices may not necessarily themselves include a host interface.Type: GrantFiled: March 24, 2021Date of Patent: June 6, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sungwon Jeong, Jinhyuk Lee, Younghoi Heo, Jaeshin Lee
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Patent number: 11651677Abstract: In response to a detected presence of an intended target appliance within a logical topography of controllable appliances identity information associated with the intended target appliance is used to automatically add to a graphical user interface of a controlling device an icon representative of the intended target appliance and to create at a Universal Control Engine a listing of communication methods for use in controlling corresponding functional operations of the intended target appliance. When the icon is later activated, the controlling device is placed into an operating state appropriate for controlling functional operations of the intended target appliance while the Universal Control Engine uses at least one of the communication methods to transmit at least one command to place the intended target appliance into a predetermined operating state.Type: GrantFiled: August 30, 2021Date of Patent: May 16, 2023Assignee: Universal Electronics Inc.Inventors: Paul D. Arling, Brian Barnett
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Patent number: 11645062Abstract: A software update device includes a reception unit that receives update data from the server; an update unit that updates software using the update data; a communication interface that communicates with the other software update devices; an update timing reception unit that receives from the server an update timing in which conditions for updating the software including a reception of an update trigger are described; a notification information reception unit that receives notification information including conditions for transmitting the update trigger to another software update device; an update trigger notification unit that transmits the update trigger to the other software update devices; an update trigger reception unit that receives the update trigger from the other software update devices; and an update start determination unit that causes the update unit to update the software when it is determined that all the conditions described in the update timing are satisfied.Type: GrantFiled: October 26, 2017Date of Patent: May 9, 2023Assignee: Clarion Co., Ltd.Inventors: Kyouichi Nakaguma, Hidetoshi Teraoka, Tomochika Ozaki, Hiroshi Kodaka, Tsuneo Sobue
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Patent number: 11644981Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security locks are implemented to control access to secure functions of the memory devices. In one embodiment, the memory device detects a predetermined signal directed to the memory device. The predetermined signals may include one or more commands directed to the memory device, an operating parameter of the memory device, or both. The memory device may track instances of the predetermined signals to compare with a threshold stored in the memory device. If the memory device determines that the predetermined signals satisfy the threshold, the memory device prohibits access to the secure functions.Type: GrantFiled: September 25, 2020Date of Patent: May 9, 2023Assignee: Micron Technology, Inc.Inventors: Nathaniel J. Meier, Brenton P. Van Leeuwen
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Patent number: 11614986Abstract: A NVM switch has been designed that allows multiple hosts to simultaneously and independently access a single port NVM device. While this active-active multi-host usage configuration allows for a variety of uses of lower cost single port NVM device, an issue with one of the hosts can delay or block transactions between the other host and the NVM device. The NVM switch includes logic that isolates activity of the multiple hosts despite logic of the switch being shared across the hosts. When the switch detects an issue with one host (“error host”), the switch clears the in-flight commands of the error host and flushes data of the error host. Likewise, the NVM switch ensure proper communication of error reporting from attached NVM devices to the multiple hosts.Type: GrantFiled: August 5, 2019Date of Patent: March 28, 2023Assignee: Marvell Asia Pte LtdInventors: Liping Guo, Yingdong Li, Scott Furey, Salil Suri
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Patent number: 11599305Abstract: A data storage device configured to access a magnetic tape comprising a plurality of data tracks is disclosed, wherein the data storage device comprises at least one head configured to access the magnetic tape. A mapping table is generated having a predetermined number of segment entries per data track, wherein each segment entry corresponds to a data segment of the data track, each segment entry comprises a first logical address corresponding to a first logical data block stored in the corresponding data segment, and at least one of the data segments stores multiple logical data blocks. A target segment entry in the mapping table corresponding to a logical address of a read command is located, and the head is positioned at a beginning of a target data segment of a target data track corresponding to the target segment entry in order to execute the read command.Type: GrantFiled: May 11, 2021Date of Patent: March 7, 2023Assignee: Western Digital Technologies, Inc.Inventor: Robert L. Horn
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Patent number: 11599391Abstract: A method of requesting data items from storage. The method comprising allocating each of a plurality of memory controllers a unique identifier and assigning memory transaction requests for accessing data items to a memory controller according to the unique identifiers. The data items are spatially local to one another in storage. The data items are requested from the storage via the memory controllers according to the memory transaction requests and then buffered if the data items are received out of order relative to an order in which the data items are requested.Type: GrantFiled: October 3, 2019Date of Patent: March 7, 2023Assignee: Arm LimitedInventor: Graeme Leslie Ingram
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Patent number: 11586569Abstract: A method, computer program product, and computing system for assigning a first set of interrupts for exclusive processing by a first set of central processing units (CPU) cores. A second set of interrupts may be assigned for processing by a second set of CPU cores. The first set of interrupts may be processed using the first set of CPU cores. The second set of interrupts may be converted to a set of polling operations, thus defining a set of converted polling operations. The set of converted polling operations may be processed using the second set of CPU cores.Type: GrantFiled: July 23, 2021Date of Patent: February 21, 2023Assignee: EMC IP Holding Company, LLCInventors: Leonid Ravich, Eldad Zinger, Amit Engel
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Patent number: 11550589Abstract: A calculation processing apparatus includes a decoder that decodes memory access instructions including a store instruction and a load instruction; a first queue that stores the decoded memory access instructions; a second queue that stores store data related to the store instruction; a storage circuit that stores target address information of the store instruction for which the first queue is reserved but the second queue is not reserved; and an inhibitor that inhibits execution of the load instruction when address information matching target address information of the load instruction is stored in the storage circuit when the load instruction is being processed. This configuration inhibits switching of the order of a store instruction and a load instruction.Type: GrantFiled: November 27, 2019Date of Patent: January 10, 2023Assignee: FUJITSU LIMITEDInventors: Takekazu Tabata, Yasunobu Akizuki, Sota Sakashita
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Patent number: 11550270Abstract: A method for creating a redundant automation system, a computer program and a computer-readable medium, wherein the redundant automation system includes at least one automation installation to be controlled that is installed at an installation location and two control applications that are communicatively interconnected via a synchronization path, and includes a plurality of communication hubs and communication paths connecting these to one another, where one of the control applications operates as the master and the other control application operates as a reserve, such that when the control application operating as the master fails, the control application operating as the reserve function as the master, and where the locations of the computing resources for the control applications are selected such that the control applications are connected to the at least one automation installation via two different communication paths preferably having no or a minimal number of common communication hubs.Type: GrantFiled: October 2, 2020Date of Patent: January 10, 2023Assignee: SIEMENS AKTIENGESELLSCHAFTInventor: Thomas Grosch
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Patent number: 11545199Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.Type: GrantFiled: March 12, 2021Date of Patent: January 3, 2023Assignee: Micron Technology, Inc.Inventors: Gary Howe, Eric J. Stave, Thomas H. Kinsley, Matthew A. Prather
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Patent number: 11544187Abstract: A distributed storage system node is disclosed. The distributed storage system node may include at least one storage device, which may act as the primary replica for data subject to an Input/Output (I/O) request. A cost analyzer may calculate a local estimated time required to complete the I/O request at the primary replica, and a remote estimated time required to complete the I/O request at a secondary replica of the data. An I/O redirector may direct the I/O request to either the primary replica or the secondary replica based on the local estimated time required and the one remote estimated time required.Type: GrantFiled: June 24, 2020Date of Patent: January 3, 2023Inventors: Vikas K. Sinha, Gunneswara Rao Marripudi, Jianjian Huo, Ajit Yagaty
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Patent number: 11544012Abstract: A distributed storage system and a data synchronization method are used with a network. The system includes a first network host and a second network host. A first file system directly writes data generated by the first network host into a first software-simulated persistent memory. The data in the first software-simulated persistent memory is stored into a first remote block device and cached, respectively. The cached data is stored into a first persistent storage by asynchronous writeback mechanisms. The first remote block device transmits the received data to the second software-simulated persistent memory through the network. The data transmitted to the second software-simulated persistent memory is cached, and the cached data is stored into a second persistent storage by asynchronous writeback mechanisms. The second network host replaces the first network host to provide services when the first network host is out of service.Type: GrantFiled: October 13, 2021Date of Patent: January 3, 2023Assignee: QNAP SYSTEMS, INC.Inventor: Chin-Hsing Hsu
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Patent number: 11537472Abstract: A method for striping based on evaluated rules, the method may include determining a compatibility, with a storage system utilization policy, of storing stripes under evaluated rules; wherein the evaluated rules define a stripe size, a number of parity chunks per stripe, and maximal numbers of chunks within a stripe per different failure domains of different size ranges; checking whether the storing of the stripes is compatible with the storage system utilization policy; when finding that the storing of the stripes is not compatible then searching for one or more changes of one or more of the maximal numbers that yields compliant one or more maximal numbers that once applied results in a compliance with the storage system utilization policy; applying the compliant one or more maximal numbers when finding the compliant one or more maximal numbers; and determining that the evaluated failure domain rules are non-compliant when failing to find the compliant one or more maximal numbers.Type: GrantFiled: October 14, 2021Date of Patent: December 27, 2022Assignee: VAST DATA LTD.Inventors: Yogev Vaknin, Renen Hallak, Lior Klipper, Eli Malul
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Patent number: 11533349Abstract: Disclosed is a computing system capable of performing a method that involves receiving, from a first device, a first indication that a peripheral device associated with the first device is available for sharing; sending, to a second device, a second indication that the peripheral device is available for sharing; receiving, from the second device, a request to access the peripheral device; and based at least in part on receipt of the request, causing a peer-to-peer connection to be established between the second device and the first device, the peer-to-peer connection enabling communication between the second device and the peripheral device. The peer-to-peer connection may, for example, enable direction of the peripheral device to the second device so that the peripheral device is a virtual device of the second device.Type: GrantFiled: October 19, 2021Date of Patent: December 20, 2022Assignee: Citrix Systems, Inc.Inventors: Yedong Yu, Jiandong Hong, Yajun Yao, Mingming Ren, Yuan Zhang, Juanjuan Chen, Qiaofei Zhu
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Patent number: 11531618Abstract: A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.Type: GrantFiled: January 25, 2021Date of Patent: December 20, 2022Inventors: Kyungsoo Kim, Jinin So, Jong-Geon Lee, Yongsuk Kwon, Jin Jung, Jeonghyeon Cho
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Patent number: 11520728Abstract: In providing USB communication functionality over a non-USB-compliant extension medium, increased latency and processing delays may be introduced, including during configuration of endpoints. In some embodiments of the present disclosure, an upstream facing port device (UFP device) and a downstream facing port device (DFP device) are used to extend USB communication across an extension medium. In some embodiments, the UFP device extracts information from packets sent between a host device and a USB device during configuration of an endpoint. In some embodiments, the UFP device sends a synthetic NRDY packet to the host device in response to a STATUS Transaction Packet to provide the UFP device and DFP device additional time to complete configuration for servicing the endpoint.Type: GrantFiled: July 21, 2021Date of Patent: December 6, 2022Assignee: Icron Technologies CorporationInventors: Mohsen Nahvi, Robert John Daniel Butt
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Patent number: 11513687Abstract: Accessing additional storage space of a storage system includes reading a physical data fragment that is an incremental subset of a physical storage unit of the storage system, accessing metadata corresponding to logical blocks stored on the physical data fragment to determine a sidebar storage portion of the physical data fragment that is unused by the logical blocks, and accessing data of the sidebar storage portion. Accessing data of the sidebar storage portion may include providing data from the sidebar storage portion to a calling process. Accessing data of the sidebar storage portion may include modifying a portion of data from the physical data fragment and writing the physical data fragment back to the physical storage device. The physical data fragment may be locked prior to reading the physical data fragment and the physical data fragment may be unlocked after writing the physical data fragment.Type: GrantFiled: October 29, 2020Date of Patent: November 29, 2022Assignee: EMC IP Holding Company LLCInventors: Douglas E. LeCrone, Jeremy J. O'Hare, Paul A. Linstead
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Patent number: 11513609Abstract: Aspects of the present disclosure are directed towards responding to a touch gesture at a touch-enabled computing device. An interface control element may be presented at a first computing environment provided by a computing device. A touch gesture may be received at a touchscreen of the computing device, and it may be determined whether at least a portion of the touch gesture occurred at the interface control element. Based, at least in part, on whether at least a portion of the touch gesture occurred at the interface control element, a display of the first computing environment may be adjusted or information corresponding to the touch gesture may be transmitted to a second computing environment. The interface control element may be a preview pane.Type: GrantFiled: December 14, 2021Date of Patent: November 29, 2022Assignee: Citrix Systems, Inc.Inventors: Lin Cao, Ian Russell Wesley, Bassam El Faourie, Dimitri Tyryshkin, Venu Gopal Nathani
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Patent number: 11487685Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.Type: GrantFiled: May 8, 2021Date of Patent: November 1, 2022Assignee: AyDeeKay LLCInventor: Scott David Kee
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Patent number: 11488645Abstract: Disclosed are methods for reading data from a storage buffer. One such method may include retrieving a first set of data during a first period of time. The method may also include delaying data retrieval during a second period of time after the first period of time. The method may include outputting at least a portion of the first set of data during the first period of time and the second period of time. The first period of time is substantially similar to the second period of time.Type: GrantFiled: April 27, 2018Date of Patent: November 1, 2022Assignee: Micron Technology, Inc.Inventor: Parthasarathy Gajapathy
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Patent number: 11481296Abstract: A computing system detects an input/output (I/O) device configuration error. The computing system includes at least one I/O device installed with firmware configured to control an I/O function, and a plurality of I/O ports installed on the at least one I/O device. At least one I/O port outputs a request to perform a current I/O configuration initialization and generates current I/O configuration data corresponding to the current I/O configuration initialization. A memory unit is configured to store the current I/O configuration data and previously generated I/O configuration data. The I/O device compares the current I/O configuration data to the previously generated I/O configuration data, and detects the I/O device configuration error in response to determining a mismatch between the current I/O configuration data and the previously generated I/O configuration data.Type: GrantFiled: September 10, 2018Date of Patent: October 25, 2022Assignee: International Business Machines CorporationInventors: Muthulakshmi P. Srinivasan, Asha Kiran Bondalakunta, Sameer K. Sinha, Ayush Nair
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Patent number: 11460821Abstract: A method for controlling one or more scent delivery units includes maintaining one or more scheduled events, maintaining one or more scheduled anti-events, and generating, based on the one or more scheduled events and the one or more scheduled anti-events, command data to be communicated to the one or more scent delivery units to control their activation and deactivation. Generating the command data includes identifying a conflicting period of time during which control specified by the one or more scheduled events differs from control specified by the one or more scheduled anti-events and also includes generating command data that gives priority to control specified by the one or more scheduled anti-events. Control for the one or more scent delivery units during the conflicting period of time is in accordance with control logic of the one or more scheduled anti-events and not the one or more scheduled events.Type: GrantFiled: January 13, 2020Date of Patent: October 4, 2022Assignee: ScentAir Technologies, LLCInventors: John Thurston Chandler, Chad Alan Morton
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Patent number: 11442852Abstract: Aspects of a storage device including a master chip controller and a slave chip processor and memory including a plurality of memory locations are provided which allow for simplified processing of descriptors associated with host commands in the slave chip based on an adaptive context metadata message from the master chip. When the controller receives a host command, the controller in the master chip provides to the processor in the slave chip a descriptor associated with a host command, an instruction to store the descriptor in the one of the memory locations, and the adaptive context metadata message mapping a type of the descriptor to the one of the memory locations. The processor may then process the descriptor stored in the one of the memory locations based on the message, for example, by refraining from identifying certain information indicated in the descriptor. Reduced latency in command execution may thereby result.Type: GrantFiled: June 25, 2020Date of Patent: September 13, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Todd Lindberg, Robert Ellis, Kevin O'Toole, Vivek Shivhare
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Patent number: 11431818Abstract: Disclosed is a method and system for a single broadband portal where all content may be delivered to users of varied electronic devices. An example embodiment (i) provides a user interface for enabling user selection of media contents per varied electronic devices, each varied electronic device having a respective platform, the user interface indicating one or more different possible media contents; (ii) accepts from a user requests for distribution service to any of the varied electronic devices of the user, the requests specifying a user desired media content; (ii) locates the user desired media content from a plurality of storage modules; (iv) transmits the user desired media content to at least one of the varied electronic devices of the user; and (v) tracks the transmission of the user desired media content for billing purposes.Type: GrantFiled: July 15, 2019Date of Patent: August 30, 2022Assignee: CUFER ASSET LTD. L.L.C.Inventors: Gene S. Fein, Edward Merritt
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Patent number: 11429546Abstract: A communications interface for interfacing between a host system and a state machine includes an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.Type: GrantFiled: April 5, 2021Date of Patent: August 30, 2022Assignee: Imagination Technologies LimitedInventors: Bert Hindle, Ben Fletcher
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Patent number: 11410542Abstract: In response to a detected presence of an intended target appliance within a logical topography of controllable appliances identity information associated with the intended target appliance is used to automatically add to a graphical user interface of a controlling device an icon representative of the intended target appliance and to create at a Universal Control Engine a listing of communication methods for use in controlling corresponding functional operations of the intended target appliance. When the icon is later activated, the controlling device is placed into an operating state appropriate for controlling functional operations of the intended target appliance while the Universal Control Engine uses at least one of the communication methods to transmit at least one command to place the intended target appliance into a predetermined operating state.Type: GrantFiled: July 14, 2021Date of Patent: August 9, 2022Assignee: Universal Electronics Inc.Inventors: Paul D. Arling, Brian Barnett
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Patent number: 11403636Abstract: A computer-implemented method for processing blockchain-based transactions, the computer-implemented method including: receiving a target transaction initiated by a member node device in a blockchain, wherein the target transaction comprises a unique identifier of the target transaction; querying a transaction idempotent table on the block chain to determine whether the transaction idempotent table has stored a transaction idempotent record corresponding to the unique identifier of the target transaction; and in response to determining that the transaction idempotent table has not stored the transaction idempotent record corresponding to the unique identifier of the target transaction, recording the target transaction in a candidate block on the blockchain.Type: GrantFiled: June 17, 2021Date of Patent: August 2, 2022Assignee: Advanced New Technologies Co., Ltd.Inventors: Jiyuan Wang, Huabing Du, Xuebing Yan
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Patent number: 11372782Abstract: A computing system includes a host, a first electronic device connected to the host, and a second electronic device that communicates with the host through the first electronic device. The first electronic device requests a command written in a submission queue of the host based on a doorbell transmitted from the host, stores the command transmitted from the host, requests write data stored in a data buffer of the host, and stores the write data of the data buffer transmitted from the host.Type: GrantFiled: March 6, 2020Date of Patent: June 28, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Uk Kim, Yohan Ko, Insoon Jo
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Patent number: 11372783Abstract: According to an embodiment, a memory system includes a controller which includes an interface connectable with a host with cache coherency kept. The controller is configured to: before the host writes a command to an I/O submission queue, read the I/O submission queue; after the reading, detect via the interface an invalidation request, the invalidation request being based on writing of the command by the host to the I/O submission queue; and in response to the invalidation request, acquire the command in the I/O submission queue.Type: GrantFiled: March 11, 2021Date of Patent: June 28, 2022Assignee: Kioxia CorporationInventor: Kenta Yasufuku
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Methods and systems for enabling publish-subscribe message transmission in a distributed environment
Patent number: 11363099Abstract: Messaging systems and methods for routing messages between network nodes of a distributed computing system are disclosed. The messaging system includes a plurality of network nodes. Each network node includes a shared memory comprising a shared memory region configured to store messages, a publisher, and a first bridge module. The first bridge module determines if a subscriber for a shared memory region of that network node exists on a remote network node, where the remote network node does not include the publisher. Upon determining that the subscriber exists on the remote network node, the first bridging module reads a plurality of messages from the shared memory region, and transmits the plurality of messages to a second bridge module of the remote network node. The second bridge module is configured to write the plurality of messages to a remote memory region on the remote network node.Type: GrantFiled: November 13, 2020Date of Patent: June 14, 2022Assignee: Argo AI, LLCInventor: Randall Nortman -
Patent number: 11341070Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.Type: GrantFiled: November 20, 2020Date of Patent: May 24, 2022Assignee: Rambus, Inc.Inventors: Frederick A. Ware, Ely Tsern, John Eric Linstadt, Thomas J. Giovannini, Kenneth L. Wright
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Patent number: 11327925Abstract: Disclosed herein are system, method, and computer program product embodiments for modular fragmentation and messaging across different web applications. An example system may include at least one computer processor, a memory, and a first database, the first database comprising a first procedure specification of at least one first procedure, and a first data field configured to store a data item, the first data field comprising a first logical link within a first data structure of the first database, the first logical link comprising a respective first set of first link specifications, and the first procedure being configured to retrieve the data item stored in the first data field upon execution by the processor. Semantic links between procedure specifications may be determined from matches with logical links. A linked data item stored in one field may be transferred to another field that has a matching logical link.Type: GrantFiled: June 19, 2019Date of Patent: May 10, 2022Assignee: SAP SEInventor: Dominik Held
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Patent number: 11329924Abstract: In one embodiment, a method includes determining, by a first network component, a sender shaper drop value based on the following: a maximum sequence number; a minimum sequence number; and a sender sequence counter number associated with the first network component. The method also includes determining, by the first network component, a wide area network (WAN) link drop value based on the sender sequence counter number associated with the first network component and a receiver sequence counter number associated with a second network component. The method further includes determining, by the first network component, whether to adjust a sender shaper rate based on the sender shaper drop value and the WAN link drop value.Type: GrantFiled: June 3, 2020Date of Patent: May 10, 2022Assignee: CISCO TECHNOLOGY, INC.Inventors: Hongbo Xia, Xiaorong Wang, Yu Zhang, Changhong Shen
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Patent number: 11317759Abstract: A cooking management system is described that identifies a customer and orders a product for the customer based at least on current temporal data. The cooking management system identifies customers associated with previous product requests that occurred during a predetermined range of time based at least on a comparison of current temporal data with temporal data associated with the previous product requests. The cooking management system causes presentation of identifiers of the identified customers on a display. Responsive to determining that the identifier for a particular customer has been selected, the cooking management system automatically causes a cooking device to prepare a product for the particular customer based at least on customer data associated with the particular customer.Type: GrantFiled: July 2, 2020Date of Patent: May 3, 2022Assignee: Starbucks CorporationInventors: Randy Hulett, Izaak Koller, Brian Shay
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Patent number: 11315519Abstract: The invention provides a control method for improving network performance, comprising: each upstream device issues corresponding playing commands and performs filtering to the playing commands to obtain first available playing commands; a downstream device switches to a route where the first available playing commands is located, and then issues vendor command parameters; an implementation module receives the vendor command parameters, then enables a timer, and sets identification information; during the preset timer time period, the implementation module filters the first available playing commands to obtain second available playing commands; when the preset timer time period ends, the implementation module turns off the timer and resets the identification information; and the downstream device receives the second available playing commands and switches to a route where the second available playing commands is located.Type: GrantFiled: October 24, 2019Date of Patent: April 26, 2022Assignee: AMLOGIC (SHANGHAI) CO., LTD.Inventors: Jinping Wang, Wei Wang, Jing Liu, Wei Yu
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Patent number: 11301263Abstract: A method, computer program product, and computing system for receiving a plurality of input/output (IO) commands for a plurality of configuration objects of a storage system. A modification command for a configuration object of the plurality of configuration objects may be received. The configuration object may be suspended in response to receiving the modification command. One or more IO commands directed to the suspended configuration object from the plurality of IO commands may be processed before the configuration object is modified.Type: GrantFiled: October 30, 2019Date of Patent: April 12, 2022Assignee: EMC IP HOLDING COMPANY, LLCInventors: Eldad Zinger, Ran Anner
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Patent number: 11294832Abstract: A method for executing device management commands includes providing a device management command queue indication. The method also includes receiving, from a host in response to providing the device management command queue indication, device management commands and a respective command type for each device management command. The method also includes determining a command execution order for the device management commands based on the command types corresponding to respective device management commands and queueing, in a device management command queue, the device management commands based on the command execution order. The method also includes executing the device management commands according to the device management command queue. The method also includes communicating, to the host, a command execution indication responsive to executing the device management commands.Type: GrantFiled: March 20, 2020Date of Patent: April 5, 2022Assignee: Western Digital Technologies, Inc.Inventors: Doron Ganon, Edris Abzakh, Tomer Spector
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Patent number: 11294585Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.Type: GrantFiled: December 21, 2020Date of Patent: April 5, 2022Assignee: Micron Technology, Inc.Inventors: David Aaron Palmer, Sean L. Manion, Jonathan Scott Parry, Stephen Hanna, Qing Liang, Nadav Grosz, Christian M. Gyllenskog, Kulachet Tanpairoj
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Patent number: 11288157Abstract: A controller controlling a memory device includes an elapsed time calculator receiving a plurality of absolute times from a host when a state of a memory system including the memory device is changed between an active state and an inactive state, the plurality of absolute times including first, second, and third absolute times, calculating an average hibernation time interval between the first and second absolute times, and calculating a system time based on the third absolute time and the average hibernation time interval. The controller further includes a flash translation layer calculating expected usage of the memory device during a monitoring time interval based on the system time, calculating excess usage based on actual usage of the memory device during the monitoring time interval and the expected usage, and controlling the memory device to program data in a single level cell mode until the excess usage is fully consumed.Type: GrantFiled: December 19, 2019Date of Patent: March 29, 2022Assignee: SK hynix Inc.Inventor: Youn-Won Park
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Patent number: 11276431Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media comprising a plurality of data tracks, wherein each data track comprises a plurality of data sectors. A plurality of access commands are stored in a command queue, and an access command is selected from the command queue. When the selected access command is a write command to a target data track and at least part of a first data track proximate the target data track needs to be refreshed, a refresh read command is executed to read data from at least part of the first data track prior to executing the write command to the target data track.Type: GrantFiled: March 17, 2021Date of Patent: March 15, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Zarko Popov, Shad H. Thorstenson, Andrew E. Larson, Gregory M. Frees
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Patent number: 11270307Abstract: A computer-implemented method for processing blockchain-based transactions, the computer-implemented method including: receiving a target transaction initiated by a member node device in a blockchain, wherein the target transaction comprises a unique identifier of the target transaction; querying a transaction idempotent table on the block chain to determine whether the transaction idempotent table has stored a transaction idempotent record corresponding to the unique identifier of the target transaction; and in response to determining that the transaction idempotent table has not stored the transaction idempotent record corresponding to the unique identifier of the target transaction, recording the target transaction in a candidate block on the blockchain.Type: GrantFiled: May 29, 2019Date of Patent: March 8, 2022Assignee: Advanced New Technologies Co., Ltd.Inventors: Jiyuan Wang, Huabing Du, Xuebing Yan
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Patent number: 11249929Abstract: A logical device for implementing a service can be dynamically assigned to an available real device. A real device assignment request relating to a registered service program is transmitted to a real device assignment determination section (112) under the control of a registration management section (1111) of a service program management section (111). An assignment of a logic device relating to the service program to a real device is determined based on logic device information, real device interface assignment information, and real device information relating to an available real device under the control of the real device assignment determination section (112). Based on the assignment information, communication processing of a control command and data between the logic device relating to the service program and the real device to which the logic device is assigned.Type: GrantFiled: March 7, 2019Date of Patent: February 15, 2022Assignee: Nippon Telegraph and Telephone CorporationInventors: Masahiko Tsuji, Shinichiro Eitoku, Yukihisa Katayama
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Patent number: 11216364Abstract: A system includes a volatile memory having buffers and a processing device. A command generation processor receives, from a host, a read request with a logical block address (LBA) and creates a first logical transfer unit (LTU), including the first LBA, that is to be mapped to a physical address. The command generation processor reads a flag to determine that the first LTU is associated with a zone of LBA address space, the zone including sequential LBAs that are sequentially mapped to sequential physical addresses. The command generation processor generates command tags that are to direct the processing device to retrieve the data from the memory device and store the data in a set of the buffers, where the command tags include a first command tag associated with the physical address and a second command tag associated with a second physical address that sequentially follows the physical address.Type: GrantFiled: February 18, 2020Date of Patent: January 4, 2022Assignee: Micron Technology, Inc.Inventors: Chandra M. Guda, Johnny A. Lam
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Patent number: RE49366Abstract: Systems are provided for logging transactions in heterogeneous networks that include a combination of one or more instrumented components and one or more non-instrumented components. The instrumented components are configured to generate impersonated log records for the non-instrumented components involved in the transaction processing hand-offs with the instrumented components. The impersonated log records are persisted with other log records that are generated by the instrumented components in a transaction log that is maintained by a central logging system to reflect a complete flow of the transaction processing performed on the object, including the flow through the non-instrumented component(s).Type: GrantFiled: November 16, 2021Date of Patent: January 10, 2023Assignee: Microsoft Technology Licensing, LLCInventors: David Christopher Wright, Arijit Chatterjee, Qingqing Yuan, Praveen Kumar Barli, Basaveshwar S. Hiremath, Nosheen M. Syed, Autumn Lee Johnson
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Patent number: RE49496Abstract: A semiconductor device includes: various types of memories; an interface configured to transmit memory characteristic information of the memories to a host, receive information needed to control operations of the memories from the host, and perform interfacing between the host and the memories; and a controller configured to control operations of the memories in response to information received from the host, and control an operation of the interface.Type: GrantFiled: April 27, 2020Date of Patent: April 18, 2023Assignee: SK hynix Inc.Inventor: Hyuk Choong Kang