Input/output Command Process Patents (Class 710/5)
  • Patent number: 11327925
    Abstract: Disclosed herein are system, method, and computer program product embodiments for modular fragmentation and messaging across different web applications. An example system may include at least one computer processor, a memory, and a first database, the first database comprising a first procedure specification of at least one first procedure, and a first data field configured to store a data item, the first data field comprising a first logical link within a first data structure of the first database, the first logical link comprising a respective first set of first link specifications, and the first procedure being configured to retrieve the data item stored in the first data field upon execution by the processor. Semantic links between procedure specifications may be determined from matches with logical links. A linked data item stored in one field may be transferred to another field that has a matching logical link.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: May 10, 2022
    Assignee: SAP SE
    Inventor: Dominik Held
  • Patent number: 11329924
    Abstract: In one embodiment, a method includes determining, by a first network component, a sender shaper drop value based on the following: a maximum sequence number; a minimum sequence number; and a sender sequence counter number associated with the first network component. The method also includes determining, by the first network component, a wide area network (WAN) link drop value based on the sender sequence counter number associated with the first network component and a receiver sequence counter number associated with a second network component. The method further includes determining, by the first network component, whether to adjust a sender shaper rate based on the sender shaper drop value and the WAN link drop value.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: May 10, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Hongbo Xia, Xiaorong Wang, Yu Zhang, Changhong Shen
  • Patent number: 11317759
    Abstract: A cooking management system is described that identifies a customer and orders a product for the customer based at least on current temporal data. The cooking management system identifies customers associated with previous product requests that occurred during a predetermined range of time based at least on a comparison of current temporal data with temporal data associated with the previous product requests. The cooking management system causes presentation of identifiers of the identified customers on a display. Responsive to determining that the identifier for a particular customer has been selected, the cooking management system automatically causes a cooking device to prepare a product for the particular customer based at least on customer data associated with the particular customer.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: May 3, 2022
    Assignee: Starbucks Corporation
    Inventors: Randy Hulett, Izaak Koller, Brian Shay
  • Patent number: 11315519
    Abstract: The invention provides a control method for improving network performance, comprising: each upstream device issues corresponding playing commands and performs filtering to the playing commands to obtain first available playing commands; a downstream device switches to a route where the first available playing commands is located, and then issues vendor command parameters; an implementation module receives the vendor command parameters, then enables a timer, and sets identification information; during the preset timer time period, the implementation module filters the first available playing commands to obtain second available playing commands; when the preset timer time period ends, the implementation module turns off the timer and resets the identification information; and the downstream device receives the second available playing commands and switches to a route where the second available playing commands is located.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: April 26, 2022
    Assignee: AMLOGIC (SHANGHAI) CO., LTD.
    Inventors: Jinping Wang, Wei Wang, Jing Liu, Wei Yu
  • Patent number: 11301263
    Abstract: A method, computer program product, and computing system for receiving a plurality of input/output (IO) commands for a plurality of configuration objects of a storage system. A modification command for a configuration object of the plurality of configuration objects may be received. The configuration object may be suspended in response to receiving the modification command. One or more IO commands directed to the suspended configuration object from the plurality of IO commands may be processed before the configuration object is modified.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 12, 2022
    Assignee: EMC IP HOLDING COMPANY, LLC
    Inventors: Eldad Zinger, Ran Anner
  • Patent number: 11294832
    Abstract: A method for executing device management commands includes providing a device management command queue indication. The method also includes receiving, from a host in response to providing the device management command queue indication, device management commands and a respective command type for each device management command. The method also includes determining a command execution order for the device management commands based on the command types corresponding to respective device management commands and queueing, in a device management command queue, the device management commands based on the command execution order. The method also includes executing the device management commands according to the device management command queue. The method also includes communicating, to the host, a command execution indication responsive to executing the device management commands.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: April 5, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Doron Ganon, Edris Abzakh, Tomer Spector
  • Patent number: 11294585
    Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: David Aaron Palmer, Sean L. Manion, Jonathan Scott Parry, Stephen Hanna, Qing Liang, Nadav Grosz, Christian M. Gyllenskog, Kulachet Tanpairoj
  • Patent number: 11288157
    Abstract: A controller controlling a memory device includes an elapsed time calculator receiving a plurality of absolute times from a host when a state of a memory system including the memory device is changed between an active state and an inactive state, the plurality of absolute times including first, second, and third absolute times, calculating an average hibernation time interval between the first and second absolute times, and calculating a system time based on the third absolute time and the average hibernation time interval. The controller further includes a flash translation layer calculating expected usage of the memory device during a monitoring time interval based on the system time, calculating excess usage based on actual usage of the memory device during the monitoring time interval and the expected usage, and controlling the memory device to program data in a single level cell mode until the excess usage is fully consumed.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: March 29, 2022
    Assignee: SK hynix Inc.
    Inventor: Youn-Won Park
  • Patent number: 11276431
    Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media comprising a plurality of data tracks, wherein each data track comprises a plurality of data sectors. A plurality of access commands are stored in a command queue, and an access command is selected from the command queue. When the selected access command is a write command to a target data track and at least part of a first data track proximate the target data track needs to be refreshed, a refresh read command is executed to read data from at least part of the first data track prior to executing the write command to the target data track.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: March 15, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zarko Popov, Shad H. Thorstenson, Andrew E. Larson, Gregory M. Frees
  • Patent number: 11270307
    Abstract: A computer-implemented method for processing blockchain-based transactions, the computer-implemented method including: receiving a target transaction initiated by a member node device in a blockchain, wherein the target transaction comprises a unique identifier of the target transaction; querying a transaction idempotent table on the block chain to determine whether the transaction idempotent table has stored a transaction idempotent record corresponding to the unique identifier of the target transaction; and in response to determining that the transaction idempotent table has not stored the transaction idempotent record corresponding to the unique identifier of the target transaction, recording the target transaction in a candidate block on the blockchain.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 8, 2022
    Assignee: Advanced New Technologies Co., Ltd.
    Inventors: Jiyuan Wang, Huabing Du, Xuebing Yan
  • Patent number: 11249929
    Abstract: A logical device for implementing a service can be dynamically assigned to an available real device. A real device assignment request relating to a registered service program is transmitted to a real device assignment determination section (112) under the control of a registration management section (1111) of a service program management section (111). An assignment of a logic device relating to the service program to a real device is determined based on logic device information, real device interface assignment information, and real device information relating to an available real device under the control of the real device assignment determination section (112). Based on the assignment information, communication processing of a control command and data between the logic device relating to the service program and the real device to which the logic device is assigned.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: February 15, 2022
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Masahiko Tsuji, Shinichiro Eitoku, Yukihisa Katayama
  • Patent number: 11216364
    Abstract: A system includes a volatile memory having buffers and a processing device. A command generation processor receives, from a host, a read request with a logical block address (LBA) and creates a first logical transfer unit (LTU), including the first LBA, that is to be mapped to a physical address. The command generation processor reads a flag to determine that the first LTU is associated with a zone of LBA address space, the zone including sequential LBAs that are sequentially mapped to sequential physical addresses. The command generation processor generates command tags that are to direct the processing device to retrieve the data from the memory device and store the data in a set of the buffers, where the command tags include a first command tag associated with the physical address and a second command tag associated with a second physical address that sequentially follows the physical address.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Chandra M. Guda, Johnny A. Lam
  • Patent number: 11212209
    Abstract: A network switching environment includes a network switch coupled to a port extension module by one or more network cables, and a management resource coupled to the switch and the port extension module. The configurations of the network switch and the port extension module may be dynamically controlled by a management resource to adjust to changes in the maximum bandwidth provided by the one or more network cables. The management resource may implement the network switch and port extension module configurations according to a predetermined target configuration and the connection configuration of the network switch and the port extension module.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: December 28, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: David Kasperson, Robert Teisberg, Charles S. Greenidge, Alexander Kramer
  • Patent number: 11210219
    Abstract: Servicing I/O operations directed to a dataset that is synchronized across a plurality of storage systems, including: receiving, by a follower storage system, a request to modify the dataset; sending, from the follower storage system to a leader storage system, a logical description of the modification to the dataset; receiving, from the leader storage system, information describing the modification to the dataset; processing, by the follower storage system, the request to modify the dataset; receiving, from the leader storage system, an indication that the leader storage system has processed the request to modify the dataset; and acknowledging, by the follower storage system, completion of the request to modify the dataset.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: December 28, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Deepak Chawla, David Grunwald, Steven Hodgson, Tabriz Holtz, Ronald Karr
  • Patent number: 11210243
    Abstract: The invention provides a system capable of remotely controlling electronic apparatus, which includes a cloud management platform and at least one electronic apparatus. The electronic apparatus includes at least one operation element, and a data storage device having a network communication function. The data storage device includes a first transmission interface, a second transmission interface, a data storage unit, and an operation management unit. Via the first transmission interface, data stored in the data storage unit can be read or data can be written into the data storage unit. The operation management unit of the data storage device transmits a specific operation instruction to the operation element via the second transmission interface after receiving the specific operation instruction sent from the cloud management platform, such that the operation element can execute a corresponding operation according to the specific operation instruction.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: December 28, 2021
    Assignee: Innodisk Corporation
    Inventor: Chih-Ching Wu
  • Patent number: 11209910
    Abstract: Aspects of the present disclosure are directed towards responding to a touch gesture at a touch-enabled computing device. An interface control element may be presented at a first computing environment provided by a computing device. A touch gesture may be received at a touchscreen of the computing device, and it may be determined whether at least a portion of the touch gesture occurred at the interface control element. Based, at least in part, on whether at least a portion of the touch gesture occurred at the interface control element, a display of the first computing environment may be adjusted or information corresponding to the touch gesture may be transmitted to a second computing environment.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: December 28, 2021
    Assignee: Citrix Systems, Inc.
    Inventors: Lin Cao, Ian Russell Wesley, Bassam El Faourie, Dimitri Tyryshkin, Venu Gopal Nathani
  • Patent number: 11182101
    Abstract: A storage system and method for stream management in a multi-host virtualized storage system are provided. In one embodiment, a method for stream management is provided that is performed in a storage system in communication with a host comprising a plurality of virtual hosts. The method comprises: receiving, from the host, identification of each virtual host of the plurality of virtual hosts; analyzing usage history of each virtual host of the plurality of virtual hosts; and assigning streams to a subset of the plurality of virtual hosts based on the usage history, wherein a maximum number of streams assignable by the storage system is less than a total number of virtual hosts in the plurality of virtual hosts. Other embodiments are provided.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: November 23, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alexander Bazarsky, Ariel Navon, Shay Benisty, Judah Gamliel Hahn
  • Patent number: 11163708
    Abstract: Communicating between a first device and a second device includes the first device generating command mode control words for communication with the second device, the first device converting the command mode control words into transport mode control words prior to transmitting the control words to the second device, the first device receiving transport mode control words from the second device, and the first device converting the transport mode control words received from the second device into received command mode control words. An application running on the first device may generate command mode control words for communication with the second device. The application may directly provide command mode control words to an ssch or channel subsystem layer. The first device may convert the command mode control words into transport mode control words using an ssch or channel subsystem layer. The first device may be a host computing system.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: November 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Douglas E. LeCrone, Paul A. Linstead
  • Patent number: 11163652
    Abstract: A first storage device capable of performing peer-to-peer communications with a second storage device includes a first submission queue for storing a first operation code; a first completion queue for storing a first indication signal; and a first controller configured to, read the first operation code stored in the first submission queue, create a command including a second operation code based on the first operation code, issue the command to the second storage device, and receive and processes a second completion signal transmitted from the second storage device.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Bum Park, Ho Jun Shim
  • Patent number: 11158284
    Abstract: An electronic apparatus includes: a signal output circuit configured to connect with an external apparatus connected to a display apparatus, a processor configured to control the electronic apparatus to: obtain information about a first image format supported in the display apparatus from the external apparatus, output a content signal having the first image format to the external apparatus through the signal output circuit to the display apparatus based on identifying that the external apparatus supports an interface protocol capable of transmitting the content signal having the first image format, and output a content signal having a second image format different from the first image format to the external apparatus through the signal output circuit based on identifying that the external apparatus does not support the interface protocol.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: October 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sungbo Oh
  • Patent number: 11157350
    Abstract: There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the L0 state. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Daniel S. Froelich, Debendra Das Sharma, Fulvio Spagna, Per E. Fornberg, David Edward Bradley
  • Patent number: 11134553
    Abstract: A lighting memory device and a memory module are provided. A lighting control circuit receives at least one lighting mode selection signal through lighting mode control pins and controls luminous characteristics of a plurality of light sources according to a lighting control mode corresponding to the lighting mode selection signal.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: September 28, 2021
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Hung-Cheng Chen, Tse-Hsien Liao
  • Patent number: 11134297
    Abstract: In the described examples, a video integrated circuit (IC) chip includes a video input port (VIP) that receives a video stream. The video IC chip also includes a processing unit coupled to a non-transitory memory and is configured to detect the presence of a data stream provided to the VIP, cause the VIP to switch a target partition for the data stream from a given partition in the memory to another partition in the memory and to write the data stream to the other partition in the memory.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: September 28, 2021
    Assignee: Texas Instruments Incorporated
    Inventor: Christopher James Broadhurst
  • Patent number: 11119851
    Abstract: Provided are a computer program product, system, and method for using a machine learning module to determine when to perform error checking of a storage unit. Input on attributes of at least one storage device comprising the storage unit are provided to a machine learning module to produce an output value. An error check frequency is determined from the output value. A determination is made as to whether the error check frequency indicates to perform an error checking operation with respect to the storage unit. The error checking operation is performed in response to determining that the error checking frequency indicates to perform the error checking operation.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Karl A. Nielsen, Clint A. Hardy, Lokesh M. Gupta
  • Patent number: 11112972
    Abstract: A method includes: receiving, at an acceleration platform manager (APM) from an application service manager (ASM), application function processing information; allocating, by the APM, a first storage processing accelerator (SPA) from a plurality of SPAs, wherein at least one SPA of the plurality of SPAs comprises a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs comprising n SPEs, enabling the plurality of SPEs in the first SPA, wherein once enabled, the at least one SPE of the plurality of SPEs in the first SPA is configured to process data based on the application function processing information; determining, by the APM, if data processing is completed by the at least one SPE of the plurality of SPEs in the first SPA; and sending, by the APM, a result of the data processing by the SPEs of the first SPA, to the ASM.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: September 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ramdas P. Kachare, Vijay Balakrishnan, Stephen G. Fischer, Fred Worley, Anahita Shayesteh, Zvi Guz
  • Patent number: 11113102
    Abstract: A data storage device with a controller using a central processing unit (CPU) in a multi-stage architecture is shown. The processing systems of the different stages communicate with each other. In a first processing system, a command controller is provided to implement the first processing system as a transmitting end, and the command controller includes a plurality of command queues. When a first command is queued in a first command queue for transmission, a first processor of the first processing system fills a second command into a second command queue for transmission.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: September 7, 2021
    Assignee: SILICON MOTION, INC.
    Inventor: Jyun-Han Wu
  • Patent number: 11103204
    Abstract: A medical X-ray system and a method perform radiological examinations of patients. In order to allow particularly efficient operation of the medial X-ray device, a data processing system of the X-ray system processes data processing processes in parallel and has multiple user interfaces that are used to provide a data input and/or data output option for respective different data processing processes at the same time.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: August 31, 2021
    Assignee: Siemens Healthcare GmbH
    Inventors: Clemens Joerger, Gudrun Roth-Ganter
  • Patent number: 11093425
    Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: August 17, 2021
    Assignee: Apple Inc.
    Inventors: Nachiappan Chidambaram Nachiappan, Jaideep Dastidar, Yiu Chun Tse, Ripudaman Singh, Shawn Munetoshi Fukami, Benjamin K. Dodge, Vinodh R. Cuppu
  • Patent number: 11093170
    Abstract: Techniques are provided for splitting a computer dataset between multiple storage locations based on a workload footprint analysis of that dataset. As a computer accesses data storage, its input/output (I/O) access can be monitored, as well as a working dataset of that dataset. The I/O access patterns can be used to determine an application of the computer that is generating the I/O. The application and the working dataset can be used to determine a split for the dataset across multiple storage locations. The dataset can then be split according to the determined split.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: August 17, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Alexey Fomin, Yuri Zagrebin, Nickolay Dalmatov
  • Patent number: 11061587
    Abstract: According to one embodiment, the memory system includes a memory and a memory controller. After the memory controller determines that a plurality of first commands including addresses have been received from a host device in a first sequence, when a plurality of second commands including addresses are received from the host device in a second sequence, the memory controller stores the addresses included in the plurality of the second commands in a memory; converts the address stored in the memory into a first password; and restricts or does not restrict execution of the first command and the second command from the host device after the memory system is started up, and removes the restriction of the execution or restricts the execution of the first command and the second command from the host device after the first password is matched with a predetermined second password.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: July 13, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Matsukawa
  • Patent number: 11055250
    Abstract: An apparatus to is provided, to be used with an interconnect comprising a home node. The apparatus includes general-purpose storage circuitry and specialised storage circuitry. Transfer circuitry performs a non-forwardable transfer of a data item from the general-purpose storage circuitry to the specialised storage circuitry. Transmit circuitry transmits an offer to the home node, at a time of the non-forwardable transfer, to transfer the data item to the home node. The apparatus is inhibited from forwarding the data item from the specialised storage circuitry to the home node.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: July 6, 2021
    Assignee: Arm Limited
    Inventors: Phanindra Kumar Mannava, Bruce James Mathewson, Klas Magnus Bruce, Damien Guillaume Pierre Payet, Jamshed Jalal, Alex James Waugh
  • Patent number: 11055499
    Abstract: A card device according to an aspect of the present disclosure includes: a first interface that connects the card device with a host device. The card device notifies, through the first interface, the host device of whether or not the card device includes a second interface different from the first interface.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: July 6, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yoshihisa Inagaki, Tadashi Ono, Isao Kato
  • Patent number: 11042874
    Abstract: A computer-implemented method for processing blockchain-based transactions, the computer-implemented method including: receiving a target transaction initiated by a member node device in a blockchain, wherein the target transaction comprises a unique identifier of the target transaction; querying a transaction idempotent table on the block chain to determine whether the transaction idempotent table has stored a transaction idempotent record corresponding to the unique identifier of the target transaction; and in response to determining that the transaction idempotent table has not stored the transaction idempotent record corresponding to the unique identifier of the target transaction, recording the target transaction in a candidate block on the blockchain.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: June 22, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventors: Jiyuan Wang, Huabing Du, Xuebing Yan
  • Patent number: 11030008
    Abstract: The present technology includes a controller including an allocation manager configured to determine whether a host identification (ID) output from a host is an allocable ID, an address manager configured to perform an allocation operation using the host ID to select logical blocks corresponding to the host ID when the host ID is received from the allocation manager, and output an address of the logical blocks as an allocation address, and a map table component configured to store a map table in which logical block addresses and physical block addresses are respectively mapped, select a logical block address corresponding to the allocation address, and output the physical block address mapped to the selected logical block address, a memory system including the controller, and a method of operating the memory system.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: June 8, 2021
    Assignee: SK hynix Inc.
    Inventors: Duk Joon Jeon, Changhwan YouN
  • Patent number: 11029893
    Abstract: A storage device includes a nonvolatile memory device; and a controller configured to, sequentially receive first read commands and a first write command, the first write command being associated with first write data, slice the first write command to generate a plurality of sub-commands, slice the first write data to generate a plurality of sub-data elements, and alternately transmit, to the nonvolatile memory device, at least one read command of the first read commands, and one sub-command of the plurality of sub-commands and one sub-data element of the plurality of sub-data elements.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jesuk Yeon, Seontaek Kim, Young-Ho Park, Eun Ju Choi, Yonghwa Lee
  • Patent number: 11017188
    Abstract: A high speed tabletop and industrial printer is disclosed with integrated high speed RFID encoding and verification at the same time. The industrial printer simultaneously prints on and electronically encodes/verifies RFID labels, tags, and/or stickers attached to a continuous web. The industrial printer comprises a lighted sensor array for indexing the printing to the RFID tags; and a cutter powered from the industrial printer for cutting the web that the RFID tags are disposed on. The industrial printer comprises two RFID reader/writers that are individually controlled. Specifically, one of the RFID reader/writers comprises the ability to electronically encode the RFID tags while the web is moving; and the second RFID reader/writer uses an additional RFID module and antenna on the printer for verifying the data encoded to the RFID tags. The printer provides for successive writes to various memory blocks and optimizes the communication sequence between the interrogator and tag.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 25, 2021
    Assignee: Avery Dennison Retail Information Services, LLC
    Inventors: Jeanne F. Duckett, Lance D. Neuhard, David J. Wimmers, Richard D. Wirrig, Larri B. Williams, James A. Makley, Jan M. Watson, Andrew R. Evans
  • Patent number: 11016664
    Abstract: A first computing device is part of a distributed electronic storage system (DESS) that also comprises one or more second computing devices. The first computing device comprises client process circuitry and DESS interface circuitry. The DESS interface circuitry is operable to: receive, from client process circuitry of the first computing device, a first client file system request that requires accessing a storage resource on one or more of the second computing devices; determine resources required for servicing of the first client file system request; generate a plurality of DESS file system requests for the first file system request; and transmit the plurality of DESS file system requests onto the one or more network links. How many such DESS file system requests are generated is determined based on the resources required for servicing the first client file system request.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: May 25, 2021
    Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel, Kanael Arditti, Tomer Filiba
  • Patent number: 11010355
    Abstract: The present disclosure discloses a file access method of a virtualization instance, including performing union on some image subfiles in a host operating system (host OS) and mounting a united directory to a union directory, and when an application in a library operating system instance needs to access a file in the union directory, causing a central processing unit to generate an exit event such that a hypervisor captures and processes the exit event, and during processing, converts an access request that is from the instance into an access request based on a system call of the host OS, and performs access.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: May 18, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Lei Ye, Qixuan Wu, Lei Dai
  • Patent number: 11005744
    Abstract: A method and apparatus for determining a port rate determines a channel transmission rate of an SAS port including N physical channels. The method includes: determining M different negotiated rates of the N physical channels; separately determining M total port bandwidths corresponding to the M different negotiated rates; and determining a negotiated rate corresponding to a largest total port bandwidth in the M total port bandwidths as a channel transmission rate of the port. A lowest negotiated rate is no longer used as the channel transmission rate of the port, but the negotiated rate corresponding to the largest total port bandwidth is determined as the channel transmission rate of the port.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: May 11, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xu Wei, Yuanting Long
  • Patent number: 10999791
    Abstract: [Object] To provide a communication apparatus, a communication method, and a program, each of which is capable of flexibly controlling operation of the communication apparatus in accordance with a change in communication environment while reducing power consumption. [Solution] A communication apparatus includes: a control module configured to control operation of the communication apparatus; and a communication module configured to determine whether or not information obtained by reception from another communication apparatus has been changed and control state transition of the control module in a case where it is determined that the information obtained by the reception has been changed.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: May 4, 2021
    Assignee: SONY CORPORATION
    Inventor: Tatsuo Nagamatsu
  • Patent number: 10990567
    Abstract: Techniques for processing I/O operations may include: receiving, an I/O operation including a tag value denoting a process of a database application that issued the I/O operation; determining, in accordance with the tag value, whether the I/O operation is directed to a data file storing content of a database or a log file of recorded operations of the database; and responsive to determining the I/O operation is directed to a data file storing content of the database, performing processing including: determining a current configuration setting of the database that indicates whether the database is configured for use with the database application as an in-memory database; and determining, in accordance with current configuration setting of the database, a first service level objective for the I/O operation, wherein the first service level objective for the I/O operation is a default service level objective or a revised service level objective.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: April 27, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Drew P. Tonnesen, Yaron Dar, Felix Shvaiger, Arieh Don
  • Patent number: 10965753
    Abstract: A method for enforcing data integrity in an RDMA data storage system includes flushing data write requests to a data storage device before sending an acknowledgment that the data write requests have been executed. An RDMA data storage system includes a node configured to flush data write requests to a data storage device before sending an acknowledgment that a data write request has been executed.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: March 30, 2021
    Assignee: NetApp Inc.
    Inventor: Dhananjoy Das
  • Patent number: 10964360
    Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: March 30, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Ji Kim, Jung-June Park, Jeong-Don Ihm, Byung-Hoon Jeong, Young-Don Choi
  • Patent number: 10956102
    Abstract: In an information processing apparatus, a processor firstly acquires all device port names registered in a memory, and instructs the operating system to register new device information indicating a new device. The processor secondly acquires, in response to determining that the operating system completes registering the new device information, all device port names including the new device port name associated with the new device information from the memory. The processor identifies the new device port name which is included in the secondly acquired device port names but excluded from the firstly acquired device port names by comparing the firstly acquired device port names with the secondly acquired device port names, and registers in the operating system the new device port name and the software to be correlated with each other so that the software can communicate with the new device through the new device port.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: March 23, 2021
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventor: Po Chun Chew
  • Patent number: 10956154
    Abstract: A signal processing apparatus includes a memory; a processor comprising arithmetic logic units (ALUs); and a hardware accelerator configured to perform an arithmetic logic operation by using shared ALUs that are not used by the processor among the ALUs.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: March 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-jae Lee, Jae-hyun Kim
  • Patent number: 10944400
    Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: March 9, 2021
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 10936495
    Abstract: Implementations disclosed herein include a system and method of storing one or more data and program data in a memory, temporarily storing the one or more data and the program data in a cache, managing the one or more data from the memory and the cache in a read data register and a read cache register, and managing the program data from the memory and the cache in a program data register and a program cache register, wherein each of the read data register and the read cache register are separate from the program data register and the program cache register. Read operations are performed only with the read data register and the read cache register. Program operations are performed only with the program data register and the program cache register.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: March 2, 2021
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventor: Sachin Sudhir Jagtap
  • Patent number: 10901524
    Abstract: A system is described that mitigates the unintentional triggering of action keys on keyboards. The system detects and interprets first and second keyboard input events. If the first keyboard input event is interpreted as a character input and the second keyboard input event is interpreted as an action input, the system performs a pattern analysis based at least on an elapsed time between the first and second keyboard input events. If the second keyboard input is determined to be unintentional, the system may mitigate the unintentional triggering of the second keyboard input event by ignoring it or by interpreting the second keyboard input event as something other than the action input. If the second keyboard input is determined to be intentional, then the second keyboard input is accepted as the action input.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: January 26, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Claes-Fredrik U. Mannby
  • Patent number: 10896094
    Abstract: The disclosure facilitates rerouting data traffic of applications. A failover request is received by a failover application including an application identifier of a main application, the failover application indicating at least one sub-application and a target data source. The failover application selects a configuration data set of the main application based on the application identifier, wherein the selected configuration data set defines an address mask of the target data source associated with the at least one sub-application. The failover application generates failover instructions for activating data traffic routing of the at least one sub-application to the target data source based on the address mask of the target data source. The failover application provides the generated failover instructions to a data traffic manager associated with the main application, whereby data traffic of the at least one sub-application is routed to the target data source by the data traffic manager.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: January 19, 2021
    Assignee: MASTERCARD INTERNATIONAL INCORPORATED
    Inventor: Adam Miedziejewski
  • Patent number: 10884661
    Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Victor Y. Tsai, Danilo Caraccio, Daniele Balluchi, Neal A. Galbo, Robert Warren