Input/output Command Process Patents (Class 710/5)
  • Patent number: 10403332
    Abstract: Provided are a memory device and a memory system including the same. The memory device may include a first memory rank including at least one first memory chip, a memory controller configured to provide a command to the first memory rank, at least one data buffer configured to buffer data input to the at least one first memory chip or being output from the at least one first memory chip, and a second memory rank connected to the first memory rank and comprising at least one second memory chip. The first memory rank may provide training data and a data strobe signal to the second memory rank based on a data training command from the memory controller without the training data and the data strobe signal passing through the data buffer. The second memory rank may determine a delay of the data strobe signal based on the training data being detected by the second memory rank.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Geun Lee, Young Jin Cho, Hee Hyun Nam, Hyo Deok Shin, Young Kwang Yoo
  • Patent number: 10402288
    Abstract: A universal serial bus (USB) testing method includes selecting a selected test mode from test modes, creating a USB communication link between a USB device and a testing fixture board, generating, by the testing fixture board, a test-triggering instruction corresponding to the selected test mode according to the selected test mode, sending the test-triggering instruction to the USB device with the USB communication link, generating, by the USB device, a testing packet corresponding to the selected test mode according to the test-triggering instruction, and outputting the testing packet repeatedly from at least one external port of the USB device.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: September 3, 2019
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventors: Huang-Wen Su, Shi-Tsan Lin
  • Patent number: 10385796
    Abstract: A downlink communication data DND from a main control circuit section to a combination control circuit section is divided into first and second downlink data, high-speed communication using a downlink clock signal and a transmission start instruction signal is performed, a high-speed load which has been directly driven from the main control circuit section is indirectly driven at high speed from the combination control circuit section by the first downlink data, a low-speed analog input signal ANL which has been indirectly inputted to the combination control circuit section is inputted to a specific input channel of a multi-channel converter through an indirect multiplexer, and channel selection is made by the downlink communication data.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: August 20, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuki Iwagami, Junji Tada, Tomoki Yamamoto
  • Patent number: 10381087
    Abstract: Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yafeng Zhang, Liang Qiao, Chunyuan Hou, Jun Xu
  • Patent number: 10365929
    Abstract: A Spin Loop Delay instruction. The instruction has a field associated therewith that indicates one or more conditions to be checked. Dispatching of the instruction is initially delayed. The instruction is subsequently dispatched based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fadi Y. Busaba, Christian Jacobi, Anthony Saporito, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 10365826
    Abstract: A command from a host is received via a port of a storage system. The port is assigned a current port revision identifier. The current port revision identifier of the port is associated with the command. Responsive to a status change associated with the port, an updated port revision identifier is assigned to the port to replace the current port revision identifier of the port and execution of the command is aborted responsive to determining that the current port revision identifier associated with the command is different than the updated port revision identifier of the port.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Duncan, Terry M. Cronin
  • Patent number: 10353613
    Abstract: When mounting hardware which is coupled to another portion by a plurality of paths with different applications, despite the hardware being a single device, and a failure occurs in any of the paths, there is a risk that the failure may propagate to other components unless the other paths are also blocked. In order to solve the problem described above, in a storage apparatus to which a device coupled by a plurality of coupling paths with different applications can be mounted, the present invention determines a block range at the time of an occurrence of a failure to be a device and a plurality of coupling paths coupled to the device, manages the block range, and upon an occurrence of a failure, executes failure handling which involves blocking an appropriate block range determined in advance by referring to the information.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: July 16, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Akihiko Araki, Yusuke Nonaka, Masanori Takada, Naoya Okada
  • Patent number: 10346362
    Abstract: Techniques herein are for accessing non-materialized blocks of a sparse file. A method involves a storage system receiving a storage command to access a sparse file. A combined content of a set of materialized blocks and a header that identifies one or more non-materialized blocks is assembled. The combined content does not comprise a content of the one or more non-materialized blocks. Responsive to the assembling, the combined content is transferred between the storage system and a computer system.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: July 9, 2019
    Assignee: Oracle International Corporation
    Inventors: Zuoyo Tao, Nilesh Choudhury, Scott Martin, Mingmin Chen, Jia Shi, Alexander Tsukerman, Kothanda Umamageswaran
  • Patent number: 10338950
    Abstract: Quality of service is provided to prioritized VMs and applications, based on the varied quality of different shared computing resources. Each VM or application has an associated priority. A quality rating is dynamically assigned to each shared computing resource. Requests for shared computing resources made by specific VMs or applications are received. For each specific received request, the current priority of the requesting VM or application is identified. In response to each received request, a specific shared computing resource is assigned to the specific requesting VM or application. This assignment is made based on the current priority of the requesting VM or application and the current quality rating of the shared computing resource, thereby providing quality of service to the requesting VM or application corresponding to its current priority.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 2, 2019
    Assignee: Veritas Technologies LLC
    Inventors: Hari Krishna Vemuri, Shweta Goyal, Nirendra Awasthi
  • Patent number: 10310923
    Abstract: Systems and methods are disclosed for probabilistic aging command sorting, including adjusting an execution order for a command based on a probability of the command reaching a time out threshold. Various example embodiments are directed to selecting a command for execution from a queue of commands awaiting execution, in which the commands have non-uniform attributes influencing their selection and a time limit within which to execute them. In some embodiments, an apparatus may comprise a circuit configured to calculate a first estimated access time to execute a selected command from a command queue, modify the first estimated access time based on a probability of the selected command reaching a time-out age threshold to determine a time out-adjusted access time, and execute the selected command in an order based on the time out-adjusted access time.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: June 4, 2019
    Assignee: Seagate Technology LLC
    Inventors: Jeffrey Vincent DeRosa, Jon David Trantham, Mark Gaertner
  • Patent number: 10296338
    Abstract: In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space; and a control logic to configure the core based in part on information in the alternate address space configuration register. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Brent R. Boswell, Banu Meenakshi Nagasundaram, Michael D. Abbott, Srikanth Dakshinamoorthy, Jason M. Howard, Joshua B. Fryman
  • Patent number: 10275254
    Abstract: A Spin Loop Delay instruction. The instruction has a field associated therewith that indicates one or more conditions to be checked. Dispatching of the instruction is initially delayed. The instruction is subsequently dispatched based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: April 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fadi Y. Busaba, Christian Jacobi, Anthony Saporito, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 10270442
    Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: April 23, 2019
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 10255213
    Abstract: Provided are methods and adapter devices for buffering write transactions directed to a large space. In various implementations, an adapter device may include a sequential address buffer and a memory. A region of the memory may be configured as a data block, which may be associated with an address range. The address range may correspond to a region of an address space of a target device. The adapter device may be configured to receive a write transaction, the write transaction having an address and data. The adapter device may further write the address to the sequential address buffer. The adapter device may further determine that the address is within the address range, and to write the data to the data block. The adapter device may further, upon the occurrence of an event, write the data from the data block to the region of the address space of the target device.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: April 9, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Adi Habusha, Itai Avron, Yaakov Gendel
  • Patent number: 10254965
    Abstract: The present invention provides a method and apparatus for scheduling block device input/output requests, which relates to the field of computer memories. The method comprises: generating a block device input/output request firstly, wherein the block device input/output request comprises a write operation request; then judging whether the generated block device input/output request can be combined with block device input/output requests in a request queue; and if the generated block device input/output request cannot be combined with block device input/output requests in a request queue, sending the generated block device input/output request to a foremost position of the request queue when a destination device of the generated block device input/output request is a solid state disk or an SD card. By means of the method and apparatus for scheduling the block device input/output requests, the efficiency of write operation is improved.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: April 9, 2019
    Assignee: STREAMAX TECHNOLOGY CO., LTD.
    Inventors: Kaiming Huang, Wentao Liu, Jianzhang Gui
  • Patent number: 10223297
    Abstract: A system can include a plurality of first server modules interconnected to one another via a communication network, each first server module including a first switch, at least one main processor, and at least one computation module coupled to the main processor by a bus, each computation module including a second switch, and a plurality of computation elements; wherein the second switches of the first server modules form a switching plane for the ingress and egress of network packets independent of any main processors of the first server modules.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 5, 2019
    Inventor: Parin Bhadrik Dalal
  • Patent number: 10223019
    Abstract: A computer program product, system, and computer-executable method for managing meta volumes in a data storage system, the computer program product, system, and computer-executable method comprising receiving one or more data storage characteristics, analyzing the one or more data storage characteristics, based on the analyzing, creating a policy responsive to the data storage characteristics, and allocating a meta volume based on the policy.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: March 5, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Evgeny Roytman, Anoop George Ninan
  • Patent number: 10223037
    Abstract: According to an embodiment, a memory device includes a nonvolatile memory and a controller. The controller receives, from a host device, a write request for writing data in the nonvolatile memory, and then performs data writing based on the write request. When a writing order confirmation request, which is issued for confirmation of fact that data writing is performed based on one or more of the write requests that are already sent, is received from the host device, the controller performs data writing based on the write requests received before receiving the writing order confirmation request and then sends to the host device a response with respect to the writing order confirmation request.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: March 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsunori Kanai, Tetsuro Kimura, Masaya Tarui, Yusuke Shirota, Shiyo Yoshimura
  • Patent number: 10219651
    Abstract: A cooking management system is described that identifies a customer and orders a product for the customer based at least on current temporal data. The cooking management system identifies customers associated with previous product requests that occurred during a predetermined range of time based at least on a comparison of current temporal data with temporal data associated with the previous product requests. The cooking management system causes presentation of identifiers of the identified customers on a display. Responsive to determining that the identifier for a particular customer has been selected, the cooking management system automatically causes a cooking device to prepare a product for the particular customer based at least on customer data associated with the particular customer.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: March 5, 2019
    Assignee: Starbucks Corporation
    Inventors: Randy Hulett, Izaak Koller, Brian Shay
  • Patent number: 10199084
    Abstract: Examples may include techniques to use chip select signals for a dual in-line memory module (DIMM). In some examples, the chip select signals are used with either a first encoding scheme for clock enable (CKE) functionality or a second encoding scheme for on-die termination (ODT) functionality to enable memory devices on the DIMM to be accessed or controlled according to commands received with the chip select signals.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventor: Bill Nale
  • Patent number: 10191865
    Abstract: A network device stores information associated with a packet in a queue. The network device sends an interrupt to a host to notify the host of completion of processing the packet. A Memory-Mapped Input/Output (MMIO) write transaction is received that includes a pointer update associated with the queue and an interrupt unmasking value. The pointer is updated and the interrupt is unmasked based on receiving the single MMIO write transaction.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: January 29, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Georgy Machulsky, Netanel Israel Belgazal, Said Bshara, Nafea Bshara, Adi Habusha
  • Patent number: 10180485
    Abstract: Described herein are systems and methods for improving performance of single-frequency (single-point, single-bin) discrete Fourier transform (DFT) detectors by elimination of systematic errors from the detector output. Calibration procedures known in the art for practical implementations of such detectors do not provide adequate reduction of these systematic errors thus reducing utilization of these detectors in useful applications and products. The described methods, systems and devices allow such detectors to measure both DC and AC signals and, in latter case, considerably expand the operation frequency range without any additional hardware. These methods enable wide practical applications of DFT detectors across diverse variety of fields: from monitoring health of mechanical structures and fluid properties to impedimetric measurements in electrochemistry, monitoring of corrosion and bioimpedance.
    Type: Grant
    Filed: September 5, 2015
    Date of Patent: January 15, 2019
    Inventor: Leonid Matsiev
  • Patent number: 10176135
    Abstract: A system includes an input/output adapter operable to receive a plurality of packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet at a data link layer and determine a state of a first output indicator to maintain packet ordering. Based on determining that a first receiver formatting interface is selected by the first output indicator, the controller performs an alignment adjustment and output of the first packet by the first receiver formatting interface. Based on determining that a second receiver formatting interface is selected by the first output indicator, the controller performs the alignment adjustment and output of the first packet by the second receiver formatting interface.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey C. Hanscom, Eric N. Lais, John M. Pritz
  • Patent number: 10162534
    Abstract: Systems and methods for utilization of notification or ordering commands are disclosed that can enable more efficient processing of flush requests from software programs and increase data consistency in storage devices. A data storage device or system may include a non-volatile memory, a memory comprising a data cache and a controller. The controller may be configured to receive an ordering command requesting commitment to the non-volatile memory of cached data items associated with a first identifier prior to commitment of cached data items associated with a second identifier, and to delay commitment of the second data item to the non-volatile memory until commitment of the first data item to the non-volatile memory, based at least in part on the ordering command. The controller may be further configured to select data items from the data cache for commitment to the non-volatile memory in accordance with native command queuing (NCQ).
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: December 25, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventor: Nathan Obr
  • Patent number: 10146207
    Abstract: A numerical control apparatus includes an API interface section that accepts invocation of an API function, an API control section that executes the process of the API function based on the invocation of the API function, and processing period estimation means for estimating if the execution of the API function is completed in a predetermined period, and the API control section does not execute but terminates the process of the API function when the processing period estimation means estimates that the execution of the API function will not be completed in the predetermined period.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: December 4, 2018
    Assignee: Fanuc Corporation
    Inventors: Tomokazu Kato, Kazuo Sato, Hideaki Maeda
  • Patent number: 10140313
    Abstract: Parallel processing files on a distributed file system, responds to a request to process the file, by partitioning the file into a set of predetermined sized blocks by a single coordinator and assigns blocks to a reader in a set of readers. Block assignments are recorded to a control table accessible to all readers. The set of readers search the control table for a row assigned to a respective reader. Responsive to locating the row, the respective reader changes a state of the row to in progress updating an associated timestamp. The respective reader scans the control table for an available set of the blocks, when all blocks currently assigned are exhausted and dynamically re-assigns an available block from another owning reader to itself and changes ownership to itself. When no rows are available, the respective reader completes processing and returns an end of file indication to the single coordinator.
    Type: Grant
    Filed: September 27, 2015
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexander Abrashkevich, Toni Kunic, Steven Raspudic
  • Patent number: 10095613
    Abstract: A data storage device which exchanges multi-stream data with a host includes a nonvolatile memory device; a buffer memory configured to temporarily store data to be stored in the nonvolatile memory device or data read from the nonvolatile memory device; and a storage controller configured to receive from the host an access command for accessing segments of the multi-stream data, the accessing including reading the segments of the multi-stream data from or writing the segments of the multi-stream data to the nonvolatile memory device, wherein the storage controller is configured to store the access-requested segments in the buffer memory, the access-requested segments being the segments of data for which access is requested in the access command, the multi-stream data including a plurality of data streams that correspond respectively to a plurality of multi-stream indexes, the first multi-stream index being one of a plurality of multi-stream indexes.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung-hyun Jo, Seongnam Kwon
  • Patent number: 10068306
    Abstract: A mechanism is described for facilitating dynamic pipelining of workload executions at graphics processing units on computing devices. A method of embodiments, as described herein, includes generating a command buffer having a plurality of kernels relating to a plurality of workloads to be executed at a graphics processing unit (GPU), and pipelining the workloads to be processed at the GPU, where pipelining includes scheduling each kernel to be executed on the GPU based on at least one of availability of resource threads and status of one or more dependency events relating to each kernel in relation to other kernels of the plurality of kernels.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: September 4, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jayanth N. Rao, Pavan K. Lanka
  • Patent number: 10067903
    Abstract: A semiconductor device includes: various types of memories; an interface configured to transmit memory characteristic information of the memories to a host, receive information needed to control operations of the memories from the host, and perform interfacing between the host and the memories; and a controller configured to control operations of the memories in response to information received from the host, and control an operation of the interface.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 4, 2018
    Assignee: SK hynix Inc.
    Inventor: Hyuk Choong Kang
  • Patent number: 10055593
    Abstract: Approaches are described for updating code and/or instructions in one or more computing devices. In particular, various embodiments provide approaches for updating the microcode of one or more processors of a computing device without requiring a restart of the computing device and without disrupting the various components (e.g., applications, virtual machines, etc.) executing on the computing device. The microcode updates can be performed on host computing devices deployed in a resource center of a service provider (e.g., cloud computing service provider), where each host computing device may be executing a hypervisor hosting multiple guest virtual machines (or other guest applications) for the customers of the service provider.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: August 21, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Nachiketh Rao Potlapally, Michael David Marr
  • Patent number: 10055144
    Abstract: A configurable storage drive includes multiple types of storage such as magnetic media and solid state storage and can implement any of multiple valid configuration modes. A user of the configurable storage drive can select the particular configuration mode so desired to achieve, for example, a desired number of input and output transactions per second. In one example, a service provider network includes multiple such configurable storage drives and customers of the service provider can configure their respective storage drives independently and differently from the other service provider customers. The service provider can opt to provide for selection to its customers all or only a subset of the possible valid configuration modes for selection by the customers. For example, storage drive configuration modes that would result in higher power consumption levels by the storage drives might not be offered to the customers.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: August 21, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Rajan Panchapakesan
  • Patent number: 10031677
    Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: July 24, 2018
    Assignee: Rambus Inc.
    Inventors: Aws Shallal, Michael Miller, Stephen Horn
  • Patent number: 10032119
    Abstract: An ordering system receives release requests to release packets, where each packet has an associated sequence number, but the system only releases packets sequentially in accordance with the sequence numbers. The system includes a Ticket Order Release Command Dispatcher And Sequence Number Translator (TORCDSNT) and a plurality of Ticket Order Release Bitmap Blocks (TORBBs). The TORBBs are stored in one or more transactional memories. In response to receiving release requests, the TORCDSNT issues atomic ticket release commands to the transactional memory or memories, and uses the multiple TORBBs in a chained manner to implement a larger overall ticket release bitmap than could otherwise be supported by any one of the TORBBs individually. Special use of one flag bit position in each TORBB facilitates this chaining. In one example, the system is implemented in a network flow processor so that the TORBBs are maintained in transactional memories spread across the chip.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 24, 2018
    Assignee: Netronome Systems, Inc.
    Inventor: Christopher A. Telfer
  • Patent number: 10025922
    Abstract: Techniques are described herein for loading a user-mode component associated with a kernel-mode component based on an asynchronous procedure call (APC) built by the kernel-mode component. The APC is provided to the main thread of a user-mode process while that user-mode process loads, causing the user-mode process to load the user-mode component. The APC also causes allocation of memory at a location adjacent to that of the user-mode process and stores instructions at the allocated memory. The user-mode component then atomically hooks function(s) of the user-mode process, including modifying a single instruction or set of instructions of the function(s) to jump to the allocated memory. When that modified instruction is executed and jumps to the allocated memory, the instructions at the allocated memory request loading of the user-mode component, which receives data from the hooked function. The user-mode component then provides that data to the kernel-mode component.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: July 17, 2018
    Assignee: CrowdStrike, Inc.
    Inventors: Ion-Alexandru Ionescu, Loren C. Robinson
  • Patent number: 10025531
    Abstract: A storage device, such as a NAND flash device, includes a controller that assigns host read commands to a high priority queue and all other I/O commands including host write commands to a low priority queue. The controller executes any commands in the high priority queue before executing commands in the low priority queue. Block write commands are broken into page write commands that are added to the low priority queue, thereby enabling any host read commands to be interleaved with execution of the page write commands, rather than waiting for completion of a block write command. Coherency between overlapping commands is performed by a host device coupled to the controller such that no checking of coherency is performed by the SSD controller.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: July 17, 2018
    Assignee: HONEYCOMBDATA INC.
    Inventors: Jongman Yoon, Sushma Devendrappa, Xiangyong Ouyang
  • Patent number: 10019181
    Abstract: Various example embodiments herein disclose a method of managing input/output (I/O) queues by a Non-Volatile Memory Express (NVMe) controller. The method includes receiving a single command from a host to perform a creation of the I/O queues or deletion of the I/O queues. Further, the method includes processing a queue identifier, a queue size, and combination of the queue identifier and queue size indicated in the single command. Furthermore, the method includes performing the creation of the I/O queues or deletion of the I/O queues, in a host memory.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: July 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Vikram Singh, Suman Prakash Balakrishnan
  • Patent number: 10019161
    Abstract: A system and method that allows out of order fetching of host non-volatile memory commands can improve and maximize the memory device performance. The memory device can examine the non-volatile memory command headers available in the non-volatile memory command queue to select one or more, non-volatile memory commands to be fetched, in an optimum order and executed according to currently available resources in the memory device. The memory device can optimize performance of the non-volatile memory commands by re-ordering the host commands fetched from the host memory.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 10, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Tal Sharifie, Shay Benisty, Amir Turjeman
  • Patent number: 10013280
    Abstract: Many storage devices (or drives) include a mechanism, such as a processor, to execute internal maintenance process(es) that maintain data integrity and long-term drive health. One example of such an internal maintenance process is a background media scan (BMS). However, on busy systems, the BMS may not have an opportunity to execute, which can damage long term drive performance. In one embodiment, a method includes sending a command from a host device to a storage device. The storage device can responsively run an internal maintenance process of the storage device. In one embodiment, the internal maintenance process can be an internal maintenance process such as a background media scan.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: July 3, 2018
    Assignee: Dell Products, LP
    Inventors: Damon Hsu-Hung, Paul David Guttormson, Bernard Abraham Rozmovits
  • Patent number: 10015347
    Abstract: An information processing apparatus includes: a retention unit that retains a list of paper information and detailed information associated with the paper information; a first acquisition unit that acquires a list of paper information from a storage unit of a printer; an update unit that updates the list of the paper information retained in the retention unit by using the acquired list of paper information; a second acquisition unit that acquires, based on a difference between the list, of the paper information retained in the retention unit and the acquired list of paper information, part of detailed information associated with paper information stored in the storage unit, from the storage unit; and a generation unit that generates, based on the detailed information acquired by the second acquisition unit, data to be transmitted to the printer. The update unit updates, based on the acquired detailed information, the retained detailed information.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: July 3, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yasuo Kurata
  • Patent number: 9998350
    Abstract: A testing device of high-frequency memory comprises a transfer interface, a tester and a socket group. The tester is electrically connected to the socket group via the transfer interface. The transfer interface is configured to merge a first testing signal with a second testing signal to generate a double frequency testing signal, wherein the first testing signal and the second testing signal are outputted by the tester, and through the transfer interface, the double frequency testing signal is shared and transmitted to the socket group for testing at least two memory packages disposed on the socket group.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: June 12, 2018
    Assignee: Powertech Technology Inc.
    Inventors: Chih-Hui Yeh, Chih-Wei Lee
  • Patent number: 9990283
    Abstract: A memory system includes: a first memory device including a plurality of first memories and a first memory controller suitable for controlling the plurality of first memories to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: June 5, 2018
    Assignee: SK Hynix Inc.
    Inventors: Do-Yun Lee, Min-Chang Kim, Chang-Hyun Kim, Yong-Woo Lee, Jae-Jin Lee, Hoe-Kwon Jung
  • Patent number: 9923726
    Abstract: Embodiments of the present invention provide methods, systems, and computer program products for transferring data in a MapReduce framework. In one embodiment, MapReduce jobs are performed such that data spills are stored by mapper systems in memory and are transferred to reducer systems via one-sided RDMA transfers, which can reduce CPU overhead of mapper systems and the latency of data transfer to reducer systems.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Muhammad Sohaib Aslam, Tiia J. Salo
  • Patent number: 9898084
    Abstract: A system is provided that generates a dynamic haptic effect that includes one or more key frames, where each key frame includes a first interpolant value and a first haptic effect. The system further receives an interpolant value, where the interpolant value is between at least two interpolant values of at least two key frames. The system further determines the dynamic haptic effect from the interpolant value. The system further distributes the dynamic haptic effect among a plurality of actuators.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: February 20, 2018
    Assignee: IMMERSION CORPORATION
    Inventors: Henry Da Costa, Eric Gervais, Satvir Singh Bhatia
  • Patent number: 9892085
    Abstract: A method for controlling an I2C slave device with the aid of a control device, including: evaluating states on a data line and on a clock line of the I2C bus; and assigning the states on the data line and on the clock line to states in a state diagram, control signals for the I2C slave device being generated with the aid of the control device from the states in the state diagram.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: February 13, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventors: Dorde Cvejanovic, Jan Hayek
  • Patent number: 9889881
    Abstract: An apparatus and a method that includes a program execution monitoring dedicated circuit connected to a CPU of a control apparatus of an on-vehicle electronic equipment that includes an execution time monitoring timer circuit, an execution sequence monitoring comparison circuit, a setting register, and an other attached circuit, perform monitoring of an execution sequence of a task executed by a control program of the on-vehicle electronic equipment and/or an execution time of the task executed by the control program, stop monitoring the execution time of the task when a priority interruption occurs, and enable the control of the on-vehicle electronic equipment such as an electric power steering apparatus to be continued by performing an alternative processing in the case of detecting an abnormality in the execution sequence and/or the execution time.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: February 13, 2018
    Assignee: NSK LTD.
    Inventor: Toshihiko Kobayashi
  • Patent number: 9886367
    Abstract: A method, comprises receiving a test case on a processor, receiving an input from a user to call the test case in a first calling environment, identifying the first calling environment, setting a first indicator in a memory indicating the first calling environment, running a directive in the test case, wherein the directive calls a subroutine associated with the directive, and running the subroutine called by the directive wherein the subroutine includes receiving the first indicator indicating the first calling environment, performing a first task associated with the directive wherein the first task is performed in the first calling environment responsive to receiving the first indicator indicating the first calling environment, and outputting a result of the first task to a user on a display.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: February 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Richard L. Fine
  • Patent number: 9880850
    Abstract: In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A major signal is generated that identifies an oldest ready instruction in the first age array and a subset signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen
  • Patent number: 9870287
    Abstract: A method, computer program product, and computing system for receiving a point-in-time copy command for a virtual volume exposed within a storage virtualization layer of a storage system. The point-in-time copy command is provided to one or more data arrays underlying the storage virtualization layer. The virtual volume is associated with physical storage within the one or more data arrays, thus defining associated physical storage. A level of high-availability is identified for the associated physical storage. A copy of the associated physical storage is generated that has the same level of high-availability, thus defining a high-availability copy.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: January 16, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Sumeet K. Malhotra, Colin D. Durocher
  • Patent number: 9857866
    Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: January 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akihisa Fujimoto
  • Patent number: 9852089
    Abstract: A semiconductor device includes a memory device, a host, and an interface. The memory device includes various types of memory units configured to be mounted to one slot. The host stores memory characteristic information of the various types of memory units contained in the memory device, processes a signal for the memory units on the basis of the memory characteristic information, and transmits and receives the processed signal to and from the memory units. The interface allows the host to interface with the various types of memory units contained in the memory device.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: December 26, 2017
    Assignee: SK hynix Inc.
    Inventor: Hyuk Choong Kang