Input/output Command Process Patents (Class 710/5)
  • Patent number: 10848972
    Abstract: Wireless restricted peripheral sessions are described herein. In a wireless restricted peripheral session, a mobile device has wireless access to peripheral devices and associated resources of a computing device but is restricted from accessing other resources of the computing device (such as files or applications unrelated to the peripheral devices). The mobile device can then receive input provided through a keyboard or mouse associated with the computing device, for example, and can provide information for display on a monitor associated with the computing device. A wireless restricted peripheral session can be established through a variety of approaches that can include the use of hardware, firmware, software, and/or virtual machine sessions. Wireless restricted peripheral sessions allow a visitor with a mobile device to work using peripheral devices of an organization's computer in a secure manner.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: November 24, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pablo Veramendi, David Michael Callaghan
  • Patent number: 10846254
    Abstract: Various examples described herein provide for a management controller that includes a virtual universal serial bus (USB) host controller that can emulate an actual USB host controller to a central processor. A particular endpoint from a number of endpoints is associated with a virtual USB device that is coupled to the virtual USB host controller. The particular endpoint is to refer to a location in a management memory.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 24, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Theodore F. Emerson, David F. Heinrich, Richard Wei Chieh Yu, Robert L. Noonan, Christopher J. Frantz, Sze Hau Loh
  • Patent number: 10848513
    Abstract: A computer-implemented method, computer program product and computing system for: allowing a third-party to select a training routine for a specific attack of a computing platform, thus defining a selected training routine; analyzing the requirements of the selected training routine to determine a quantity of entities required to effectuate the selected training routine, thus defining one or more required entities; generating one or more virtual machines to emulate the one or more required entities; and generating a simulation of the specific attack by executing the selected training routine.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: November 24, 2020
    Assignee: ReliaQuest Holdings, LLC
    Inventors: Brian P. Murphy, Joe Partlow, Colin O'Connor, Jason Pfeiffer
  • Patent number: 10838662
    Abstract: Provided herein may be a memory system and a method of operating the same. The method of operating a memory system may include receiving a first program command, and performing an operation corresponding to the first program command, receiving a second program command while performing the operation corresponding to the first program command, delaying setting of a queue status register for the second program command by a first wait time, receiving a third read command before the first wait time elapses, and setting the queue status register for the third read command before setting the queue status register for the second program command.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: November 17, 2020
    Assignee: SK hynix Inc.
    Inventor: Kwang Su Kim
  • Patent number: 10817328
    Abstract: Methods and systems for resource usage metric grading are disclosed. In one embodiment, an exemplary method comprises receiving a request to assign a first role to at least one virtual server; configuring the virtual server to associate the first role with a first resource of the virtual server; modifying a database to include an identifier associated with the virtual server and an identifier of the first role assigned to the virtual server; receiving, from the virtual server, indications of resource usage for a plurality of roles; calculating an efficiency metric associated with the first role, the efficiency based on resource usage associated with the first role and resource usage associated with the plurality of roles; modifying a user interface element for presentation on a web page to include the calculated efficiency metric for the first role; receiving a request from a user; and delivering the web page.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: October 27, 2020
    Assignee: Coupang Corp.
    Inventor: Tae Kyung Kim
  • Patent number: 10802990
    Abstract: Hardware mechanisms are provided for performing hardware based access control of instructions to data. These hardware mechanisms associate an instruction access policy label with an instruction to be processed by a processor and associate an operand access policy label with data to be processed by the processor. The instruction access policy label is passed along with the instruction through one or more hardware functional units of the processor. The operand access policy label is passed along with the data through the one or more hardware functional units of the processor. One or more hardware implemented policy engines associated with the one or more hardware functional units of the processor are utilized to control access by the instruction to the data based on the instruction access policy label and the operand access policy label.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventors: William E. Hall, Guerney D. H. Hunt, Paul A. Karger, Mark F. Mergen, David R. Safford, David C. Toll
  • Patent number: 10803206
    Abstract: Systems and methods for wireless enabled security in relation to a storage drive are described. In one embodiment, the systems and methods may include receiving, at a storage drive, a request from a host of the storage drive. In some cases, the request may be received via a wired connection between the storage drive and the host. In some embodiments, the systems and methods may include determining whether the request is flagged by the host as a secure connection request, processing the request upon determining the request is not flagged as a secure connection request, and establishing a wireless connection with the host upon determining the request is flagged by the host as a secure connection request.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: October 13, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventor: Christopher Nicholas Allo
  • Patent number: 10789756
    Abstract: Systems, methods, and computer readable media to encode and execute an indirect command buffer are described. A processor creates an indirect command buffer that is configured to be encoded into by a graphics processor at a later point in time. The processor encodes, within a command buffer, a produce command that references the indirect command buffer, where the produce command triggers execution on the graphics processor of a first operation that encodes a set of commands within the data structure. The processor also encodes, within the command buffer, a consume command that triggers execution on the graphics processor of a second operation that executes the set of commands encoded within the data structure. After encoding the command buffer, a processor commits the command buffer for execution on the graphics processor.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 29, 2020
    Assignee: Apple Inc.
    Inventors: Michael Imbrogno, Michal Valient
  • Patent number: 10768816
    Abstract: A method is disclosed for changing data within a solid state drive without using a host interface, comprising issuing a write buffer command with a code to the solid state drive, receiving the code at the solid state drive, storing the code at the solid state drive, transmitting a command to run the code at the solid state drive, running the code with a processor in a virtual machine arranged within the solid state drive, wherein the running of the code alters data within the solid state drive and altering at least one memory arrangement in the solid state drive such that the memory arrangement records the altered data.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 8, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Mackenzie Roeser, Robert Hill
  • Patent number: 10770123
    Abstract: A storage device including a nonvolatile memory device including memory blocks and a controller connected with the nonvolatile memory device through data input and output lines and a data strobe line may be provided. The nonvolatile memory device and the controller may be configured to perform training on the data input and output lines by adjusting a delay of a data strobe signal sent through the data strobe line and adjust delays of the data input and output lines based on the training result.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: September 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soong-Man Shin, Hyungjin Kim, YoungWook Kim
  • Patent number: 10733093
    Abstract: A memory system may include: a memory device including a plurality of memory dies suitable for storing data; and a controller operatively coupled to the memory dies of the memory device via a plurality of channels, the controller may be suitable for checking the plurality of the channels, selecting independently best transmission channels and best reception channels among the plurality of the channels according to states of the channels, requesting performing of command operations corresponding to the commands through the best transmission channels to the memory dies, and receiving performance results of the command operations through the best reception channels from the memory dies.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Ik-Sung Oh, Jin-Woong Kim
  • Patent number: 10719464
    Abstract: An example hardware accelerator in a computing system includes a bus interface coupled to a peripheral bus of the computing system; a lock circuit coupled to the bus interface; and a plurality of kernel circuits coupled to the lock circuit and the bus interface; wherein the plurality of kernel circuits provide lock requests to the lock circuit, the lock requests for data stored in system memory of the computing system; wherein the lock circuit is configured to process the lock requests from the plurality of kernel circuits and to issue atomic transactions over the peripheral bus through the bus interface based on the lock requests.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: July 21, 2020
    Assignee: XILINX, INC.
    Inventors: Sunita Jain, Sweatha Rao
  • Patent number: 10713188
    Abstract: An inter-process signaling system and method support implementation of semaphores or messaging signals between masters in a multi-master system, or between tasks in a single master system. A semaphore flag register contains one or more bits indicating whether resources are free or busy. The register is aliased to allow atomic read-and-clear of individual bits in the register. Masters poll the status of a resource until the resource reads as free. Alternatively, interrupts or events per master can be implemented to indicate availability of a resource.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: July 14, 2020
    Assignee: Atmel Corporation
    Inventor: Frode Milch Pedersen
  • Patent number: 10709289
    Abstract: A cooking management system is described that identifies a customer and orders a product for the customer based at least on current temporal data. The cooking management system identifies customers associated with previous product requests that occurred during a predetermined range of time based at least on a comparison of current temporal data with temporal data associated with the previous product requests. The cooking management system causes presentation of identifiers of the identified customers on a display. Responsive to determining that the identifier for a particular customer has been selected, the cooking management system automatically causes a cooking device to prepare a product for the particular customer based at least on customer data associated with the particular customer.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: July 14, 2020
    Assignee: Starbucks Corporation
    Inventors: Randy Hulett, Izaak Koller, Brian Shay
  • Patent number: 10705893
    Abstract: Examples described herein relate to a system consistent with the disclosure. For instance, the system may comprise a memory resource, a processing resource, and a database to collect command code information for a command line interface of a client device included in a plurality of client devices, analyze the command code information, modify a command code based on the command code information, and send the modified command code to of the plurality of client devices to cause a modified output responsive to execution of the command code on the plurality of client device.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: July 7, 2020
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventor: Seth Pickett
  • Patent number: 10684794
    Abstract: In a memory system having a storage controller and a plurality of distinct sets of non-volatile memory devices, each respective channel controller of a plurality of channel controllers, each channel controller corresponding to a distinct set of the plurality of distinct sets of non-volatile memory devices, determines a backlog of the respective channel controller in accordance with pending commands in one or more command queues, receives power credits allocated by the storage controller, based at least in part on the backlog of the respective channel controller, and while executing commands in the one or more command queues, limits execution of said commands in accordance with the received power credits. For example, limiting execution includes deferring execution of a respective command in accordance with a determination that executing the respective command would require power credits in excess of power credits available in the respective channel controller.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: June 16, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Reed P. Tidwell, Steven T. Sprouse, Satish B. Vasudeva, James M. Higgins, Jonathan Q. Tu
  • Patent number: 10681021
    Abstract: A system and method provide for the selective authorization and admission of a client into a data sharing session with a host. A host may select one or more clients into the sharing session based on the proximity of the clients. When a client is selected, an identifier is provided from the client device to the host device, for example, utilizing an optical identifier such as a bar code or an audible identifier such as an encoded sound. The identifier is then utilized to establish a link between the client and the host. In this fashion any number of client devices may be selectively admitted into the sharing session in a quick and easy process enabling security for the host and anonymity for the client.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: June 9, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Martin H. Renschler, Frederick D. Kim, Patrik Lundqvist
  • Patent number: 10679722
    Abstract: A storage system with several integrated components and method for use therewith are provided. In one embodiment, a storage system comprising: a plurality of non-volatile memory devices; a controller in communication with the plurality of non-volatile memory devices; a plurality of data buffers in communication with the controller and configured to store data sent between the controller and an input/output bus; and a command and address buffer configured to store commands and addresses sent from a host, wherein the command and address buffer is further configured to synchronize data flow into and out of the plurality of data buffer; wherein at least three of the above components are integrated with each other.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: June 9, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel L. Helmick, Martin V. Lueker-Boden
  • Patent number: 10656834
    Abstract: An interface superpipe is implemented in a filesystem. A filesystem in a kernel, receives a command to open a file, the command issued in the execution of a process in an application. The file is determined to be on an interface disk. It is determined that a context does not exist for the process and, in response, an adapter queue is allocated for the process in a kernel memory and mapped into a process address space associated with the process. The context information of the process is saved in the kernel memory. The filesystem may be part of a system further comprising a processor, a storage, an interface adapter in communication with the storage and sharing a memory space with the processor, and an application in communication with the filesystem.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Vinod K. Boddukuri, Phani Kumar V. U. Ayyagari, Venkata N. S. Anumula, Sudhir Maddali, Sanket Rathi, Bruce G. Mealey
  • Patent number: 10656950
    Abstract: A Spin Loop Delay instruction. The instruction has a field associated therewith that indicates one or more conditions to be checked. Dispatching of the instruction is initially delayed. The instruction is subsequently dispatched based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fadi Y. Busaba, Christian Jacobi, Anthony Saporito, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 10651849
    Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: May 12, 2020
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ian P. Shaeffer
  • Patent number: 10628172
    Abstract: Systems and methods for using distributed Universal Serial Bus (USB) host drivers are disclosed. In one aspect, USB packet processing that was historically done on an application processor is moved to a distributed USB driver running in parallel on a low-power processor such as a digital signal processor (DSP). While a DSP is particularly contemplated, other processors may also be used. Further, a communication path is provided from the low-power processor to USB hardware that bypasses the application processor. Bypassing the application processor in this fashion allows the application processor to remain in a sleep mode for longer periods of time instead of processing digital data received from the low-power processor or the USB hardware. Further, by bypassing the application processor, latency is reduced, which improves the listener experience.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: April 21, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Ameya Kulkarni, Andrew Cheung, Jay Yu Jae Choi, Daniel Hyongkyu Kim, Hemant Kumar, Vamsi Krishna Samavedam
  • Patent number: 10621114
    Abstract: An Input/Output (I/O) adapter device is provided. The I/O adapter device comprises: a device interface configured to communicate with a first device and a second device communicatively coupled to the I/O adapter device; a host interface configured to support communication with a frontend driver of a host device via a software interface of the host device; a first emulated backend driver configured to communicate with the frontend driver through the host interface using the software interface and to communicate with the first device to provide the frontend driver with access to the first device; and a second emulated backend driver configured to communicate with the frontend driver through the host interface using the software interface and to communicate with the second device to provide the frontend driver with access to the second device.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 14, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Nafea Bshara, Georgy Machulsky, Anthony Nicholas Liguori
  • Patent number: 10592274
    Abstract: This computer system includes: at least one computer having a memory and a plurality of CPU cores; and a storage sub device having a plurality of logical storage units configured using storage devices. In the computer, a plurality of queues are configured in the memory, and at least one of the plurality of CPU cores is assigned to each of the plurality of queues. The queue is enqueued with an I/O command dispatched from a CPU core, to which the queue is assigned, to a logical storage unit. The computer system has access control information including information concerning whether to accept or refuse access from each queue to each logical storage unit.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: March 17, 2020
    Assignee: HITACHI, LTD.
    Inventors: Katsuto Sato, Tetsuro Honmura
  • Patent number: 10581683
    Abstract: Methods, techniques, computer program products, apparatus, devices, etc., used in connection with DSL Management Interfaces, significantly improve the management capabilities of a DSL network and/or improve testing relating to DSL equipment and services by permitting better control and operation of a DSL system, including implementation of timestamping for more accurate measurement, monitoring and control of a system. Timestamping further allows customized data collection techniques, where a DSL line can be measured or monitored at intervals whose frequency depends on the line's stability. Moreover, data parameter read and control parameter write operations are presented in conjunction with the use of timestamping. Also, control and operation of a DSL system is enhanced by implementing bit-loading that minimizes, eliminates or otherwise mitigates the amount by which the SNR margin per tone exceeds a maximum SNR margin quantity, where such bit-loading can be selected through an appropriate interface.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: March 3, 2020
    Assignee: ASSIA SPE, LLC
    Inventors: John Cioffi, Wonjong Rhee, Sumanth Jagannathan, Peter Joshua Silverman, Mehdi Mohseni, Georgios Ginis
  • Patent number: 10574773
    Abstract: A method of processing a network request and response includes: merging a plurality of requests to obtain a merged request; transmitting the merged request to a server side; detecting a current status identification of the merged request; when the status indicated by the current status identification shows that data is transferring, receiving resource data corresponding to each request in the merged request and returned by the server side, and detecting the received resource data and obtaining a boundary identification contained in the received resource data; extracting and processing the resource data corresponding to each request in the merged request one by one according to the obtained boundary identification; and when the status indicated by the current status identification shows that the data transferring is completed, stopping receiving the resource data.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: February 25, 2020
    Assignee: PING AN TECHNOLOGY (SHENZHEN) CO., LTD.
    Inventor: Yangjun Xiang
  • Patent number: 10565148
    Abstract: A system and method for configuring a filter object for a controller area network is disclosed. The method includes determining, by a processor, a plurality of message identifiers of messages that are to be captured by a filter object. The method also includes performing factorization of a function that represents the plurality of message identifiers to generate a simplified function. The method also includes configuring at least one filter object based on the generated simplified function.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: February 18, 2020
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Paolo Giusto, Grant A. Soremekun, Michael A. Turley, Ramesh S
  • Patent number: 10558392
    Abstract: Systems and methods presented herein provide a controller that is operable to monitor a plurality of background commands to a storage device over a pre-determined period of time and to determine how often each of the background commands is issued during the pre-determined period of time. The controller is further operable to establish a time interval for each of the background commands, and to issue each of the background commands at their respective time intervals.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 11, 2020
    Assignee: Seagate Technology LLC
    Inventors: David Scott Ebsen, Dana Simonson
  • Patent number: 10552158
    Abstract: Various embodiments of a microprocessor include a scoreboard implementation that directs the microprocessor to the location of data values. For example, the scoreboard may include individual bits that instruct the microprocessor to retrieve the data from a re-order buffer, retire queue, result bus, or register file. As a first step, the microprocessor receives an instruction indicating a process that requires data from one or more source registers. Instead of automatically retrieving the data from the register file, which is a costly process, the microprocessor may read the scoreboard to determine whether the needed data can be more cost-effectively retrieved from the re-order buffer, retire queue, or result busses. Therefore, the microprocessor can avoid costly data retrieval procedures. Additionally, the scoreboard implementation enables the microprocessor to handle limited out-of-order instructions, which improves overall performance of the microprocessor.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: February 4, 2020
    Assignee: Synopsys, Inc.
    Inventor: Thang Tran
  • Patent number: 10540195
    Abstract: The disclosed embodiments provide a system that operates a computer system. During operation, the system detects a first change in a setting associated with a first computing environment executing on the computer system, wherein the first change is associated with at least one of an input/output (I/O) device setting, a regional setting, a network setting, a power setting, and a display setting. Next, the system propagates the first change to one or more other computing environments executing on the computer system.
    Type: Grant
    Filed: October 15, 2017
    Date of Patent: January 21, 2020
    Assignee: OPEN INVENTION NETWORK LLC
    Inventors: John Whaley, Thomas Joseph Purtell, II, Geoffrey G. Thomas
  • Patent number: 10534721
    Abstract: A cache controller determines replacement priority for cache lines at a cache based on data stored at non-cache buffers. In response to determining that a cache line at the cache is to be replaced, the cache controller identifies a set of candidate cache lines for replacement. The cache controller probes the non-cache buffers to identify any entries that are assigned to the same memory address as a candidate cache line and adjusts the replacement priorities for the candidate cache lines based on the probe responses. The cache controller deprioritizes for replacement cache lines associated with entries of the non-cache buffers.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: January 14, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Paul Moyer
  • Patent number: 10514922
    Abstract: A microcontroller includes a program memory, data memory, central processing unit, at least one register module, a memory management unit, and a transport network. Instructions are executed in one clock cycle via an instruction word. The instruction word indicates the source module from which data is to be retrieved and the destination module to which data is to be stored. The address/data capability of an instruction word may be extended via a prefix module. If an operation is performed on the data, the source module or the destination module may perform the operation during the same clock cycle in which the data is transferred.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: December 24, 2019
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Jeffrey D. Owens, Edward Tangkwai Ma, Donald W. Loomis, Thomas Augustus Chenot
  • Patent number: 10503668
    Abstract: A device includes multiple communication interfaces configured to send and receive data over multiple communication paths. The device also includes multiple input/output (I/O) channels configured to communicate with multiple field devices. The device further includes at least one processing device configured to process at least some of the data and control at least one of the field devices based on the processed data. The device may also include an intrinsic safety barrier electrically separating the communication interfaces and the I/O channels. The communication interfaces may include at least one first interface configured to communicate over one or more first communication paths with at least one component of an industrial control system and at least one second interface configured to communicate over one or more second communication paths with at least one other device that is configured to communicate with additional field devices.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: December 10, 2019
    Assignee: Honeywell International Inc.
    Inventors: Dinesh Kumar KN, Paul F. McLaughlin, Paul Gerhart, Jethro Francis Steinman, Sai Krishnan Jagannathan, Amol Kinage
  • Patent number: 10489072
    Abstract: A controller of a storage device analyzes data comprising a plurality of previous host idle durations to identify a trend in the previous host idle duration. The controller projects a next host idle duration based on the trend. The controller determines a transition from a storage device active state to a next storage device sleep state or a transition from a storage device sleep state to a next storage device active state based on the projected host idle duration.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: November 26, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Eran Erez, Shay Benisty
  • Patent number: 10489163
    Abstract: An apparatus, method, and program product are disclosed for loading a program during boot of a device. A monitor module collects usage data for each of one or more programs executing on a device. The usage data for each program comprising an amount of time that the program was used and a schedule of when the program was used. A priority module assigns a boot priority to each of the one or more programs based on the amount of time that each program was used. A boot module selects one or more programs to load during a boot period for the device based on each program's usage schedule. The one or more selected programs are loaded according to each selected program's boot priority.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: November 26, 2019
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
    Inventors: Jeffrey S. Holland, Shareef F. Alshinnawi, Gary D. Cudak
  • Patent number: 10484461
    Abstract: Systems are provided for logging transactions in heterogeneous networks that include a combination of one or more instrumented components and one or more non-instrumented components. The instrumented components are configured to generate impersonated log records for the non-instrumented components involved in the transaction processing hand-offs with the instrumented components. The impersonated log records are persisted with other log records that are generated by the instrumented components in a transaction log that is maintained by a central logging system to reflect a complete flow of the transaction processing performed on the object, including the flow through the non-instrumented component(s).
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: November 19, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: David Christopher Wright, Arijit Chatterjee, Qingqing Yuan, Praveen Kumar Barli, Basaveshwar S. Hiremath, Nosheen M. Syed
  • Patent number: 10481593
    Abstract: A system and method for capturing automation data from an automated system uses a multi-array populated by an automation controller with automation data including timing data defined by a controller clock. The multi-array includes at least one member corresponding to a sensor sensing a state of the member and a plurality of member-defined data elements, which may correspond to a start time and end time of the member state. Automation data is captured from the controller multi-array by a computing device in communication with the controller including a first data table corresponding with the controller multi-array for efficient collection of the automation data from the controller memory, and a second data table for associating each data element with its defining member and storing the associated data in a historical database which may be used for analysis of cycle time data of a member, device or operation of the automated system.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: November 19, 2019
    Assignee: BEET, LLC
    Inventors: Ivan Richard Nausley, Jeremy Philip Epple, Kusmady Susanto, David Jingqiu Wang
  • Patent number: 10474394
    Abstract: Example methods are provided to perform persistent reservation emulation in a shared virtual storage environment that includes a first host supporting a first node and a second host supporting a second node. One example method may comprise detecting a command issued by a first node to command issued by a first node to update information relating to a reservation or registration associated with a virtual disk, and updating persistent reservation information associated with the virtual disk to indicate that the command has been issued by the first node. The method may also comprise determining that the second node either has acknowledged the updated persistent reservation information, or has not acknowledged the updated persistent reservation information within a time interval. The method may further comprise updating the persistent reservation information based on the command.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: November 12, 2019
    Assignee: VMWARE, INC.
    Inventors: Rahul Dev, Gautham Swamy, Prasanna Aithal
  • Patent number: 10452279
    Abstract: A storage server comprises a plurality of solid state drives (SSDs), a plurality of input/output (I/O) controllers, a switch, and a management controller. A first SSD of the plurality of SSDs comprises a plurality of queue pairs. The management controller is to allocate a first subset of the plurality of queue pairs in the first SSD to a first I/O controller, wherein the first I/O controller is to use the first subset of the plurality of queue pairs to read from and write to the first SSD. The management controller is further to allocate a second subset of the plurality of queue pairs in the first SSD to a second I/O controller, wherein the second I/O controller is to use the second subset of the plurality of queue pairs to read from and write to the first SSD.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: October 22, 2019
    Assignee: Pavilion Data Systems, Inc.
    Inventors: Kiron Balkrishna Malwankar, Karagada Ramarao Kishore
  • Patent number: 10403332
    Abstract: Provided are a memory device and a memory system including the same. The memory device may include a first memory rank including at least one first memory chip, a memory controller configured to provide a command to the first memory rank, at least one data buffer configured to buffer data input to the at least one first memory chip or being output from the at least one first memory chip, and a second memory rank connected to the first memory rank and comprising at least one second memory chip. The first memory rank may provide training data and a data strobe signal to the second memory rank based on a data training command from the memory controller without the training data and the data strobe signal passing through the data buffer. The second memory rank may determine a delay of the data strobe signal based on the training data being detected by the second memory rank.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Geun Lee, Young Jin Cho, Hee Hyun Nam, Hyo Deok Shin, Young Kwang Yoo
  • Patent number: 10402288
    Abstract: A universal serial bus (USB) testing method includes selecting a selected test mode from test modes, creating a USB communication link between a USB device and a testing fixture board, generating, by the testing fixture board, a test-triggering instruction corresponding to the selected test mode according to the selected test mode, sending the test-triggering instruction to the USB device with the USB communication link, generating, by the USB device, a testing packet corresponding to the selected test mode according to the test-triggering instruction, and outputting the testing packet repeatedly from at least one external port of the USB device.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: September 3, 2019
    Assignee: GETAC TECHNOLOGY CORPORATION
    Inventors: Huang-Wen Su, Shi-Tsan Lin
  • Patent number: 10385796
    Abstract: A downlink communication data DND from a main control circuit section to a combination control circuit section is divided into first and second downlink data, high-speed communication using a downlink clock signal and a transmission start instruction signal is performed, a high-speed load which has been directly driven from the main control circuit section is indirectly driven at high speed from the combination control circuit section by the first downlink data, a low-speed analog input signal ANL which has been indirectly inputted to the combination control circuit section is inputted to a specific input channel of a multi-channel converter through an indirect multiplexer, and channel selection is made by the downlink communication data.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: August 20, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuki Iwagami, Junji Tada, Tomoki Yamamoto
  • Patent number: 10381087
    Abstract: Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yafeng Zhang, Liang Qiao, Chunyuan Hou, Jun Xu
  • Patent number: 10365929
    Abstract: A Spin Loop Delay instruction. The instruction has a field associated therewith that indicates one or more conditions to be checked. Dispatching of the instruction is initially delayed. The instruction is subsequently dispatched based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fadi Y. Busaba, Christian Jacobi, Anthony Saporito, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 10365826
    Abstract: A command from a host is received via a port of a storage system. The port is assigned a current port revision identifier. The current port revision identifier of the port is associated with the command. Responsive to a status change associated with the port, an updated port revision identifier is assigned to the port to replace the current port revision identifier of the port and execution of the command is aborted responsive to determining that the current port revision identifier associated with the command is different than the updated port revision identifier of the port.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Duncan, Terry M. Cronin
  • Patent number: 10353613
    Abstract: When mounting hardware which is coupled to another portion by a plurality of paths with different applications, despite the hardware being a single device, and a failure occurs in any of the paths, there is a risk that the failure may propagate to other components unless the other paths are also blocked. In order to solve the problem described above, in a storage apparatus to which a device coupled by a plurality of coupling paths with different applications can be mounted, the present invention determines a block range at the time of an occurrence of a failure to be a device and a plurality of coupling paths coupled to the device, manages the block range, and upon an occurrence of a failure, executes failure handling which involves blocking an appropriate block range determined in advance by referring to the information.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: July 16, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Akihiko Araki, Yusuke Nonaka, Masanori Takada, Naoya Okada
  • Patent number: 10346362
    Abstract: Techniques herein are for accessing non-materialized blocks of a sparse file. A method involves a storage system receiving a storage command to access a sparse file. A combined content of a set of materialized blocks and a header that identifies one or more non-materialized blocks is assembled. The combined content does not comprise a content of the one or more non-materialized blocks. Responsive to the assembling, the combined content is transferred between the storage system and a computer system.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: July 9, 2019
    Assignee: Oracle International Corporation
    Inventors: Zuoyo Tao, Nilesh Choudhury, Scott Martin, Mingmin Chen, Jia Shi, Alexander Tsukerman, Kothanda Umamageswaran
  • Patent number: 10338950
    Abstract: Quality of service is provided to prioritized VMs and applications, based on the varied quality of different shared computing resources. Each VM or application has an associated priority. A quality rating is dynamically assigned to each shared computing resource. Requests for shared computing resources made by specific VMs or applications are received. For each specific received request, the current priority of the requesting VM or application is identified. In response to each received request, a specific shared computing resource is assigned to the specific requesting VM or application. This assignment is made based on the current priority of the requesting VM or application and the current quality rating of the shared computing resource, thereby providing quality of service to the requesting VM or application corresponding to its current priority.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 2, 2019
    Assignee: Veritas Technologies LLC
    Inventors: Hari Krishna Vemuri, Shweta Goyal, Nirendra Awasthi
  • Patent number: 10310923
    Abstract: Systems and methods are disclosed for probabilistic aging command sorting, including adjusting an execution order for a command based on a probability of the command reaching a time out threshold. Various example embodiments are directed to selecting a command for execution from a queue of commands awaiting execution, in which the commands have non-uniform attributes influencing their selection and a time limit within which to execute them. In some embodiments, an apparatus may comprise a circuit configured to calculate a first estimated access time to execute a selected command from a command queue, modify the first estimated access time based on a probability of the selected command reaching a time-out age threshold to determine a time out-adjusted access time, and execute the selected command in an order based on the time out-adjusted access time.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: June 4, 2019
    Assignee: Seagate Technology LLC
    Inventors: Jeffrey Vincent DeRosa, Jon David Trantham, Mark Gaertner
  • Patent number: 10296338
    Abstract: In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space; and a control logic to configure the core based in part on information in the alternate address space configuration register. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Brent R. Boswell, Banu Meenakshi Nagasundaram, Michael D. Abbott, Srikanth Dakshinamoorthy, Jason M. Howard, Joshua B. Fryman