Input/output Command Process Patents (Class 710/5)
  • Patent number: 10095613
    Abstract: A data storage device which exchanges multi-stream data with a host includes a nonvolatile memory device; a buffer memory configured to temporarily store data to be stored in the nonvolatile memory device or data read from the nonvolatile memory device; and a storage controller configured to receive from the host an access command for accessing segments of the multi-stream data, the accessing including reading the segments of the multi-stream data from or writing the segments of the multi-stream data to the nonvolatile memory device, wherein the storage controller is configured to store the access-requested segments in the buffer memory, the access-requested segments being the segments of data for which access is requested in the access command, the multi-stream data including a plurality of data streams that correspond respectively to a plurality of multi-stream indexes, the first multi-stream index being one of a plurality of multi-stream indexes.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung-hyun Jo, Seongnam Kwon
  • Patent number: 10068306
    Abstract: A mechanism is described for facilitating dynamic pipelining of workload executions at graphics processing units on computing devices. A method of embodiments, as described herein, includes generating a command buffer having a plurality of kernels relating to a plurality of workloads to be executed at a graphics processing unit (GPU), and pipelining the workloads to be processed at the GPU, where pipelining includes scheduling each kernel to be executed on the GPU based on at least one of availability of resource threads and status of one or more dependency events relating to each kernel in relation to other kernels of the plurality of kernels.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: September 4, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jayanth N. Rao, Pavan K. Lanka
  • Patent number: 10067903
    Abstract: A semiconductor device includes: various types of memories; an interface configured to transmit memory characteristic information of the memories to a host, receive information needed to control operations of the memories from the host, and perform interfacing between the host and the memories; and a controller configured to control operations of the memories in response to information received from the host, and control an operation of the interface.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 4, 2018
    Assignee: SK hynix Inc.
    Inventor: Hyuk Choong Kang
  • Patent number: 10055144
    Abstract: A configurable storage drive includes multiple types of storage such as magnetic media and solid state storage and can implement any of multiple valid configuration modes. A user of the configurable storage drive can select the particular configuration mode so desired to achieve, for example, a desired number of input and output transactions per second. In one example, a service provider network includes multiple such configurable storage drives and customers of the service provider can configure their respective storage drives independently and differently from the other service provider customers. The service provider can opt to provide for selection to its customers all or only a subset of the possible valid configuration modes for selection by the customers. For example, storage drive configuration modes that would result in higher power consumption levels by the storage drives might not be offered to the customers.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: August 21, 2018
    Assignee: Amazon Technologies, Inc.
    Inventor: Rajan Panchapakesan
  • Patent number: 10055593
    Abstract: Approaches are described for updating code and/or instructions in one or more computing devices. In particular, various embodiments provide approaches for updating the microcode of one or more processors of a computing device without requiring a restart of the computing device and without disrupting the various components (e.g., applications, virtual machines, etc.) executing on the computing device. The microcode updates can be performed on host computing devices deployed in a resource center of a service provider (e.g., cloud computing service provider), where each host computing device may be executing a hypervisor hosting multiple guest virtual machines (or other guest applications) for the customers of the service provider.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: August 21, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Nachiketh Rao Potlapally, Michael David Marr
  • Patent number: 10031677
    Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: July 24, 2018
    Assignee: Rambus Inc.
    Inventors: Aws Shallal, Michael Miller, Stephen Horn
  • Patent number: 10032119
    Abstract: An ordering system receives release requests to release packets, where each packet has an associated sequence number, but the system only releases packets sequentially in accordance with the sequence numbers. The system includes a Ticket Order Release Command Dispatcher And Sequence Number Translator (TORCDSNT) and a plurality of Ticket Order Release Bitmap Blocks (TORBBs). The TORBBs are stored in one or more transactional memories. In response to receiving release requests, the TORCDSNT issues atomic ticket release commands to the transactional memory or memories, and uses the multiple TORBBs in a chained manner to implement a larger overall ticket release bitmap than could otherwise be supported by any one of the TORBBs individually. Special use of one flag bit position in each TORBB facilitates this chaining. In one example, the system is implemented in a network flow processor so that the TORBBs are maintained in transactional memories spread across the chip.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 24, 2018
    Assignee: Netronome Systems, Inc.
    Inventor: Christopher A. Telfer
  • Patent number: 10025531
    Abstract: A storage device, such as a NAND flash device, includes a controller that assigns host read commands to a high priority queue and all other I/O commands including host write commands to a low priority queue. The controller executes any commands in the high priority queue before executing commands in the low priority queue. Block write commands are broken into page write commands that are added to the low priority queue, thereby enabling any host read commands to be interleaved with execution of the page write commands, rather than waiting for completion of a block write command. Coherency between overlapping commands is performed by a host device coupled to the controller such that no checking of coherency is performed by the SSD controller.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: July 17, 2018
    Assignee: HONEYCOMBDATA INC.
    Inventors: Jongman Yoon, Sushma Devendrappa, Xiangyong Ouyang
  • Patent number: 10025922
    Abstract: Techniques are described herein for loading a user-mode component associated with a kernel-mode component based on an asynchronous procedure call (APC) built by the kernel-mode component. The APC is provided to the main thread of a user-mode process while that user-mode process loads, causing the user-mode process to load the user-mode component. The APC also causes allocation of memory at a location adjacent to that of the user-mode process and stores instructions at the allocated memory. The user-mode component then atomically hooks function(s) of the user-mode process, including modifying a single instruction or set of instructions of the function(s) to jump to the allocated memory. When that modified instruction is executed and jumps to the allocated memory, the instructions at the allocated memory request loading of the user-mode component, which receives data from the hooked function. The user-mode component then provides that data to the kernel-mode component.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: July 17, 2018
    Assignee: CrowdStrike, Inc.
    Inventors: Ion-Alexandru Ionescu, Loren C. Robinson
  • Patent number: 10019181
    Abstract: Various example embodiments herein disclose a method of managing input/output (I/O) queues by a Non-Volatile Memory Express (NVMe) controller. The method includes receiving a single command from a host to perform a creation of the I/O queues or deletion of the I/O queues. Further, the method includes processing a queue identifier, a queue size, and combination of the queue identifier and queue size indicated in the single command. Furthermore, the method includes performing the creation of the I/O queues or deletion of the I/O queues, in a host memory.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: July 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Vikram Singh, Suman Prakash Balakrishnan
  • Patent number: 10019161
    Abstract: A system and method that allows out of order fetching of host non-volatile memory commands can improve and maximize the memory device performance. The memory device can examine the non-volatile memory command headers available in the non-volatile memory command queue to select one or more, non-volatile memory commands to be fetched, in an optimum order and executed according to currently available resources in the memory device. The memory device can optimize performance of the non-volatile memory commands by re-ordering the host commands fetched from the host memory.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 10, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Tal Sharifie, Shay Benisty, Amir Turjeman
  • Patent number: 10013280
    Abstract: Many storage devices (or drives) include a mechanism, such as a processor, to execute internal maintenance process(es) that maintain data integrity and long-term drive health. One example of such an internal maintenance process is a background media scan (BMS). However, on busy systems, the BMS may not have an opportunity to execute, which can damage long term drive performance. In one embodiment, a method includes sending a command from a host device to a storage device. The storage device can responsively run an internal maintenance process of the storage device. In one embodiment, the internal maintenance process can be an internal maintenance process such as a background media scan.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: July 3, 2018
    Assignee: Dell Products, LP
    Inventors: Damon Hsu-Hung, Paul David Guttormson, Bernard Abraham Rozmovits
  • Patent number: 10015347
    Abstract: An information processing apparatus includes: a retention unit that retains a list of paper information and detailed information associated with the paper information; a first acquisition unit that acquires a list of paper information from a storage unit of a printer; an update unit that updates the list of the paper information retained in the retention unit by using the acquired list of paper information; a second acquisition unit that acquires, based on a difference between the list, of the paper information retained in the retention unit and the acquired list of paper information, part of detailed information associated with paper information stored in the storage unit, from the storage unit; and a generation unit that generates, based on the detailed information acquired by the second acquisition unit, data to be transmitted to the printer. The update unit updates, based on the acquired detailed information, the retained detailed information.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: July 3, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yasuo Kurata
  • Patent number: 9998350
    Abstract: A testing device of high-frequency memory comprises a transfer interface, a tester and a socket group. The tester is electrically connected to the socket group via the transfer interface. The transfer interface is configured to merge a first testing signal with a second testing signal to generate a double frequency testing signal, wherein the first testing signal and the second testing signal are outputted by the tester, and through the transfer interface, the double frequency testing signal is shared and transmitted to the socket group for testing at least two memory packages disposed on the socket group.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: June 12, 2018
    Assignee: Powertech Technology Inc.
    Inventors: Chih-Hui Yeh, Chih-Wei Lee
  • Patent number: 9990283
    Abstract: A memory system includes: a first memory device including a plurality of first memories and a first memory controller suitable for controlling the plurality of first memories to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: June 5, 2018
    Assignee: SK Hynix Inc.
    Inventors: Do-Yun Lee, Min-Chang Kim, Chang-Hyun Kim, Yong-Woo Lee, Jae-Jin Lee, Hoe-Kwon Jung
  • Patent number: 9923726
    Abstract: Embodiments of the present invention provide methods, systems, and computer program products for transferring data in a MapReduce framework. In one embodiment, MapReduce jobs are performed such that data spills are stored by mapper systems in memory and are transferred to reducer systems via one-sided RDMA transfers, which can reduce CPU overhead of mapper systems and the latency of data transfer to reducer systems.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Muhammad Sohaib Aslam, Tiia J. Salo
  • Patent number: 9898084
    Abstract: A system is provided that generates a dynamic haptic effect that includes one or more key frames, where each key frame includes a first interpolant value and a first haptic effect. The system further receives an interpolant value, where the interpolant value is between at least two interpolant values of at least two key frames. The system further determines the dynamic haptic effect from the interpolant value. The system further distributes the dynamic haptic effect among a plurality of actuators.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: February 20, 2018
    Assignee: IMMERSION CORPORATION
    Inventors: Henry Da Costa, Eric Gervais, Satvir Singh Bhatia
  • Patent number: 9889881
    Abstract: An apparatus and a method that includes a program execution monitoring dedicated circuit connected to a CPU of a control apparatus of an on-vehicle electronic equipment that includes an execution time monitoring timer circuit, an execution sequence monitoring comparison circuit, a setting register, and an other attached circuit, perform monitoring of an execution sequence of a task executed by a control program of the on-vehicle electronic equipment and/or an execution time of the task executed by the control program, stop monitoring the execution time of the task when a priority interruption occurs, and enable the control of the on-vehicle electronic equipment such as an electric power steering apparatus to be continued by performing an alternative processing in the case of detecting an abnormality in the execution sequence and/or the execution time.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: February 13, 2018
    Assignee: NSK LTD.
    Inventor: Toshihiko Kobayashi
  • Patent number: 9892085
    Abstract: A method for controlling an I2C slave device with the aid of a control device, including: evaluating states on a data line and on a clock line of the I2C bus; and assigning the states on the data line and on the clock line to states in a state diagram, control signals for the I2C slave device being generated with the aid of the control device from the states in the state diagram.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: February 13, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventors: Dorde Cvejanovic, Jan Hayek
  • Patent number: 9886367
    Abstract: A method, comprises receiving a test case on a processor, receiving an input from a user to call the test case in a first calling environment, identifying the first calling environment, setting a first indicator in a memory indicating the first calling environment, running a directive in the test case, wherein the directive calls a subroutine associated with the directive, and running the subroutine called by the directive wherein the subroutine includes receiving the first indicator indicating the first calling environment, performing a first task associated with the directive wherein the first task is performed in the first calling environment responsive to receiving the first indicator indicating the first calling environment, and outputting a result of the first task to a user on a display.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: February 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Richard L. Fine
  • Patent number: 9880850
    Abstract: In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A major signal is generated that identifies an oldest ready instruction in the first age array and a subset signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen
  • Patent number: 9870287
    Abstract: A method, computer program product, and computing system for receiving a point-in-time copy command for a virtual volume exposed within a storage virtualization layer of a storage system. The point-in-time copy command is provided to one or more data arrays underlying the storage virtualization layer. The virtual volume is associated with physical storage within the one or more data arrays, thus defining associated physical storage. A level of high-availability is identified for the associated physical storage. A copy of the associated physical storage is generated that has the same level of high-availability, thus defining a high-availability copy.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: January 16, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Sumeet K. Malhotra, Colin D. Durocher
  • Patent number: 9857866
    Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: January 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akihisa Fujimoto
  • Patent number: 9852315
    Abstract: Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: December 26, 2017
    Assignee: Altera Corporation
    Inventor: Bruce B. Pedersen
  • Patent number: 9852089
    Abstract: A semiconductor device includes a memory device, a host, and an interface. The memory device includes various types of memory units configured to be mounted to one slot. The host stores memory characteristic information of the various types of memory units contained in the memory device, processes a signal for the memory units on the basis of the memory characteristic information, and transmits and receives the processed signal to and from the memory units. The interface allows the host to interface with the various types of memory units contained in the memory device.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: December 26, 2017
    Assignee: SK hynix Inc.
    Inventor: Hyuk Choong Kang
  • Patent number: 9842074
    Abstract: Embodiments herein provide for tag allocation in a PCIe application layer. In one embodiment, an apparatus operable to interface with a plurality of virtual functions and a plurality of physical functions to process data via the PCIe protocol. The apparatus includes a packet builder communicatively coupled to each of the virtual functions and the physical functions and operable to build packets for non-posted commands from the virtual and physical functions. The apparatus also includes a tag allocator operable to allocate tags from a first set of tags to the packets of non-posted commands from any of the virtual and physical functions employing extended tags when the tags of the first set are available, and to reserve a second different set of tags for remaining virtual and physical functions not employing extended tags until the first set of tags are all allocated.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: December 12, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventor: Ramprasad Raghavan
  • Patent number: 9824054
    Abstract: A firmware updating method in just a bunch of disks includes the following blocks. A motherboard is coupled to a first primary storage extension chip or to a second primary storage extension chip. The first primary storage extension chip and the second primary storage extension chip are coupled to each other. At least one secondary storage extension chip is coupled to the first primary storage extension chip. At least one secondary storage extension chip is coupled to the second primary storage extension chip. A signal sent to the first primary storage extension chip or to the second primary storage extension chip by the motherboard causes firmware of each storage extension chip to be updated.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: November 21, 2017
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jiing-Shyang Jang, Yang Gao, Meng-Liang Yang
  • Patent number: 9824006
    Abstract: An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary configurations include a call interface, a physical layer interface, an object-based storage solid-state device (OSD-SSD), and are further characterized by the presence of a storage processor capable of processing object-based storage device algorithms interleaved with processing of physical storage device management. Embodiments include a storage controller capable of executing recognition, classification and tagging of application files, especially including image, music, and other media. Also disclosed are methods for initializing and configuring an OSD-SSD device.
    Type: Grant
    Filed: March 2, 2013
    Date of Patent: November 21, 2017
    Assignee: Digital Kiva, Inc.
    Inventor: Paul A. Duran
  • Patent number: 9817777
    Abstract: Methods and SATA devices having more than one operating state suitable for providing efficient command and data transfers over a SATA bus. A SATA device is provided for communicating with a host. The host sends commands to the SATA device and the SATA device sends data to the host in response to the commands being received by the SATA device. The SATA device has a queue of commands received from the host. The SATA device is configured to operate in a first operating state wherein the commands are received by the SATA device and the data are not sent to the host, and a second operating state wherein the commands are received by the SATA device and the data are sent to the host wherein data being sent to the host has priority over receiving commands by the SATA device.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: November 14, 2017
    Assignee: Toshiba Memory Corporation
    Inventor: Philip David Rose
  • Patent number: 9819732
    Abstract: A method, non-transitory computer readable medium, and device that manages API requests includes receiving an API request to obtain a list of storage volumes from one or more storage devices, wherein the received API request is non-compatible with the API server computing device or the one or more storage devices. The received API request is scanned to identify a service type associated with the received request. Next, one or more service instances associated with the identified service type are identified. The list of storage volumes from the one or more storage devices using information from at least one service instance of the identified one or more service instances without converting the received API request is provided.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: November 14, 2017
    Assignee: NETAPP, INC.
    Inventors: Ameet Deulgaonkar, Swaminathan Ramany, Subhabrata Sen
  • Patent number: 9796415
    Abstract: An apparatus and a method that includes a program execution monitoring dedicated circuit connected to a CPU of a control apparatus of an on-vehicle electronic equipment that includes an execution time monitoring timer circuit (111), an execution sequence monitoring comparison circuit (113), a setting register (115), an attached circuit (117), perform monitoring of an execution sequence of a task executed by a control program of the on-vehicle electronic equipment and/or an execution time of the task executed by the control program, and enabled to continue the control of the on-vehicle electronic equipment such as an electric power steering apparatus by performing an alternative processing in the case of detecting an abnormality in the execution sequence and/or the execution time.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: October 24, 2017
    Assignee: NSK LTD.
    Inventor: Toshihiko Kobayashi
  • Patent number: 9785591
    Abstract: The present invention relates to an apparatus and a method for transferring a data signal between a smartcard interface and an interface of a processor within an embedded system. According to an exemplary embodiment of the present invention, an interface conversion device communicating between a processor and a smartcard IC chip includes: an input/output signal conversion logic configured to transfer a signal between a first interface of the processor and a second interface of the smartcard IC chip; a clock generator configured to generate a clock signal driving the smartcard IC chip depending on a first control signal received from the processor and provide the generated clock signal to the smartcard IC chip; and a reset controller configured to generate a reset signal depending on a second control signal received from the processor and provide the generated reset signal to the smartcard IC chip.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: October 10, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong-Sung Jeon, Young-Sae Kim, Jeong-Nyeo Kim, Seung-Yong Yoon, Hong-Il Ju, Hyun-Sook Cho
  • Patent number: 9779018
    Abstract: A technique quantifies logical storage space trapped in an extent store due to overlapping write requests associated with volume metadata managed by the volume layer. The volume metadata is illustratively organized as a multi-level dense tree metadata structure, wherein each level of the dense tree metadata structure (dense tree) includes volume metadata entries for storing the volume metadata. When a level of the dense tree is full, the volume metadata entries of the level are merged with a next lower level of the dense tree in accordance with a merge operation. Illustratively, the technique may be invoked during the merge operation to examine the volume metadata entries at each level of the dense tree involved in the merge and determine the LBA range overlap of the entries.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: October 3, 2017
    Assignee: NetApp, Inc.
    Inventors: Sriranjani Babu, Janice D'Sa
  • Patent number: 9760512
    Abstract: A method of migrating DMA mappings from a source I/O adapter of a source computing system to a destination I/O adapter of a destination computing system, including: collecting, by a source hypervisor of the source computing system, DMA mapping information, wherein the source hypervisor supports operation of a logical partition executing on the source computing system and the logical partition is configured for DMA operations with the source I/O adapter utilizing the DMA mapping information; configuring, by a destination hypervisor of the destination computing system, the destination I/O adapter with DMA mappings based on the DMA mapping information collected by the source hypervisor; placing, by the destination hypervisor, the destination I/O adapter in an error state; migrating the logical partition from the source computing system to the destination computing system; and restarting the logical partition on the destination computing system, including recovering, by the logical partition, from the error state
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Charles S. Graham, Prathima Kommineni, Timothy J. Schimke
  • Patent number: 9740647
    Abstract: Migrating DMA mappings from a source I/O adapter of a computing system to a destination I/O adapter of the computing system, includes: collecting, by a hypervisor of the computing system, DMA mapping information, where the hypervisor supports operation of a logical partition executing on the computing system and the logical partition is configured for DMA operations with the source I/O adapter utilizing the DMA mapping information; configuring, by the hypervisor, the destination I/O adapter with DMA mappings based on the DMA mapping information collected by the hypervisor; placing, by the hypervisor, the source and destination I/O adapter in an error state; deconfiguring the source I/O adapter from the logical partition; and enabling the logical partition and destination I/O adapter to recover from the error state.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jesse P. Arroyo, Charles S. Graham, Prathima Kommineni, Timothy J. Schimke
  • Patent number: 9734341
    Abstract: A computer-implemented method for protecting computing systems from peripheral devices may include (1) identifying a peripheral device configured to perform a charging function and at least one non-charging function, (2) configuring an endpoint protection application with an endpoint protection rule that allows the charging function of the peripheral device and does not allow the non-charging function of the peripheral device, (3) detecting that the peripheral device is connected to a computing system that is provisioned with the endpoint protection application, and (4) applying the endpoint protection rule on the computing system to allow the charging function of the peripheral device so that the peripheral device is able to charge via the computing system and block the non-charging function of the peripheral device from being performed on the computing system. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: August 15, 2017
    Assignee: Symantec Corporation
    Inventor: Cui Cheng
  • Patent number: 9720598
    Abstract: A storage system comprises a storage array comprising a plurality of solid state storage devices (SSDs), a first processor comprising a first root complex of the storage system, a plurality of controller devices, and a first switch to interconnect the plurality of SSDs, the first processor and the plurality of controller devices. A first controller device of the plurality of controller devices is to connect the storage system to one or more remote servers. The first controller device is further to receive a first request from a first server of the one or more remote servers and determine whether the first request is a data request or a control request. The first controller device is further to send a first message to a first SSD of the plurality of SSDs via the first switch, bypassing the first processor, responsive to a determination that the first request is a data request.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: August 1, 2017
    Assignee: Pavilion Data Systems, Inc.
    Inventor: Kiron Balkrishna Malwankar
  • Patent number: 9721048
    Abstract: In a system and method for emulating a circuit design, an emulation system receives input instructions from a host device executing the emulation. Channels of multiple buffers and associated processors provide implement read and write instructions received at the interface. Multiple access modes are provided to read and write to system memory and to store sequences of commands in the provided buffers and to execute those stored sequences using an associated processor. By writing a sequence of commands and/or data blocks to the channel buffers, the associated processors can execute programs of varying complexity that may have been written or modified in real time or preconfigured.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: August 1, 2017
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Mitchell Grant Poplack, Yuhei Hayashi, Mark Alton Sherred
  • Patent number: 9715352
    Abstract: Aspects include transmitting a synchronous I/O command to a persistent storage control unit (SCU in response to a synchronous I/O request from an operating system (OS). A unit of work in the OS corresponding to the synchronous I/O request remains active at least until the synchronous I/O request is completed. Based on an operation code of the synchronous I/O command specifying a read operation and in response to detecting that the persistent SCU has stored one or more read data records in a memory located on the processor, the firmware indicates to the OS that the synchronous I/O request is completed. Based on the operation code specifying a write operation and in response to detecting an indication from the persistent SCU that write data has been written or indicating that an error has occurred, indicating to the OS that the synchronous I/O request is completed.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Matthew J. Kalos, Peter G. Sutton, Harry M. Yudenfriend
  • Patent number: 9703739
    Abstract: In response to receiving a novel “Return Available PPI Credits” command from a credit-aware device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the credit-aware device, and zeroes out its stored CTBR value. The credit-aware device adds the credits returned to a “Credits Available” value it maintains. The credit-aware device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another novel aspect, the credit-aware device is permitted to issue one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: July 11, 2017
    Assignee: Netronome Systems, Inc.
    Inventors: Salma Mirza, Gavin J. Stark, Steven W. Zagorianakos
  • Patent number: 9696912
    Abstract: Aspects include communicating synchronous input/output (I/O) commands between an operating system and recipient by issuing a first synchronous I/O command with an initiation bit set, identifying that a mailbox command has been initiated to return control to an operating system before waiting for operations of the first synchronous I/O command to complete, and issuing a second synchronous I/O command with a completion bit set in response to the control returning to the operating system.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: July 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Mark S. Farrell, Beth A. Glendening, Dale F. Riedy, Peter G. Sutton, Harry M. Yudenfriend
  • Patent number: 9684589
    Abstract: A computing device includes, a memory component, a memory module including memory resistors, and a virtualization module. The virtualization module intercepts communication between an application and a memory component and directs the communication to the memory module including memory resistors. The virtualization module directs communication from the memory module to the application.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: June 20, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kent E Biggs, Chi W So, Michael A Provencher
  • Patent number: 9684611
    Abstract: Aspects include transmitting a synchronous I/O command to a persistent storage control unit (SCU in response to a synchronous I/O request from an operating system (OS). A unit of work in the OS corresponding to the synchronous I/O request remains active at least until the synchronous I/O request is completed. Based on an operation code of the synchronous I/O command specifying a read operation and in response to detecting that the persistent SCU has stored one or more read data records in a memory located on the processor, the firmware indicates to the OS that the synchronous I/O request is completed. Based on the operation code specifying a write operation and in response to detecting an indication from the persistent SCU that write data has been written or indicating that an error has occurred, indicating to the OS that the synchronous I/O request is completed.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: June 20, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Matthew J. Kalos, Peter G. Sutton, Harry M. Yudenfriend
  • Patent number: 9678699
    Abstract: A communication apparatus performs wireless connection processing for performing wireless communication with another communication apparatus, specifies a service that is to be executed along with the other communication apparatus, in the wireless connection processing, using wireless communication that is based on the wireless connection processing, and performs port control such that a port necessary for execution of the specified service is opened, and a port not necessary for execution of the service is locked.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: June 13, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Kazuo Moritomo
  • Patent number: 9680766
    Abstract: A proactive networking system and method is disclosed. The network anticipates the user demands in advance and utilizes this predictive ability to reduce the peak to average ratio of the wireless traffic and yield significant savings in the required resources to guarantee certain Quality of Service (QoS) metrics. The system and method focuses on the existing cellular architecture and involves the design and analysis of learning algorithms, predictive resource allocation strategies, and incentive techniques to maximize the efficiency of proactive cellular networks. The system and method further involve proactive peer-to-peer (P2P) overlaying, which leverages the spatial and social structure of the network. Machine learning techniques are applied to find the optimal tradeoff between predictions that result in content being retrieved that the user ultimately never requests, and requests that are not anticipated in a timely manner.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: June 13, 2017
    Assignees: OHIO STATE INNOVATION FOUNDATION, UNIVERSITY OF SOUTHERN CALIFRONIA
    Inventors: Hesham El Gamal, Atilla Eryilmaz, Giuseppe Caire, Fei Sha, Margaret McLaughlin
  • Patent number: 9678674
    Abstract: Aspects include communicating synchronous input/output (I/O) commands between an operating system and recipient by issuing a first synchronous I/O command with an initiation bit set, identifying that a mailbox command has been initiated to return control to an operating system before waiting for operations of the first synchronous I/O command to complete, and issuing a second synchronous I/O command with a completion bit set in response to the control returning to the operating system.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: June 13, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Mark S. Farrell, Beth A. Glendening, Dale F. Riedy, Peter G. Sutton, Harry M. Yudenfriend
  • Patent number: 9665920
    Abstract: One embodiment of the present invention sets forth a technique for distributing graphics commands and atomic commands to a color processing unit (CROP) in an efficient manner. The interleaving mechanism determines, at each clock cycle, which graphics command(s) or atomic command(s) is transmitted to the CROP based on different factors. First, the interleaving mechanism ensures that atomic commands or graphics commands associated with a multi-transaction command stream are processed together. Second, the interleaving mechanism selects consecutive graphics commands for transmission to the CROP that optimize the use of different memory caches. Third, the interleaving mechanism prioritizes atomic commands over graphics commands. At each clock cycle, the graphics command(s) or the atomic command(s) selected by the interleaving mechanism are transmitted to the CROP for processing.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: May 30, 2017
    Assignee: NVIDIA Corporation
    Inventors: Chad D. Walker, Rui M. Bastos, Narayan Kulshrestha
  • Patent number: 9665519
    Abstract: In response to receiving a “Return Available PPI Credits” command from a credit-aware (CA) device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the CA device, and zeroes out its stored CTBR value. The CA device adds the credits returned to a “Credits Available” value it maintains. The CA device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another aspect, the CA device issues one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: May 30, 2017
    Assignee: Netronome Systems, Inc.
    Inventors: Salma Mirza, Gavin J. Stark, Steven W. Zagorianakos
  • Patent number: 9654972
    Abstract: Techniques are described for securely provisioning a client device. A client device may output first client information over a secure interface to a trusted device to be transmitted to an authentication server. Second client information related to the first client information may be transmitted to the authentication server. The authentication server may link the second client information and the first client information. The client device may receive an encrypted authentication credential from the authentication server. The authentication credential may be encrypted based at least in part on the first client information or the second client information. The client device may decrypt the encrypted authentication credential using the first client information, the second client information, or a shared secret key.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: May 16, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Olivier Jean Benoit, Peerapol Tinnakornsrisuphap
  • Patent number: 9639409
    Abstract: A device and method for communicating between cores are provided. The device comprises: a postbox component, configured to store a message sent from a message sending core to a message receiving core and notify the message receiving core to read the message; and a bus adapter component, connected between the postbox component and the message receiving core and the message sending core which communicate with each other and configured to provide read/write interfaces of the postbox component and the message receiving core and the message sending core. By means of the disclosure, the problems that the device and method for communicating between cores with high complexity, poor timeliness and poor expandability during multi-core application in the related art are solved, thereby achieving the effects of reducing the communication between cores complexity significantly, reducing communication time delay and having excellent expandability and scalability.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: May 2, 2017
    Assignee: ZTE CORPORATION
    Inventor: Peng Wang