Abstract: A method according to one embodiment includes receiving, at an I/O Handler, an instruction to initiate a backup operation on data associated with an application running on multiple servers; and stretching communication between instances of the application and data storage volumes associated therewith during initiating the backup operation. Additional systems, methods, and computer program products are also disclosed.

Abstract: A data interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. A maximum operating data rate can be negotiated. The interface provides a cost-effective, low power, bi-directional, high speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors with thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless, communication devices.

Abstract: In one embodiment, a main circuit board includes a plurality of expansion slots that are operative to receive a corresponding plurality of expansion cards. The plurality of expansion slots include at least one first expansion slot configured at a first position on the main circuit board, that is operative to connect to at least one corresponding first expansion card. At least one second expansion slot configured at a second position on the main circuit board, and the second expansion slot is operative to connect to at least one corresponding second expansion card. The plurality of expansion cards includes at least one secondary expansion card that is different from the main circuit board and that is configured to be operatively coupled to at least one of the plurality of expansion slots. One or more particular expansion slots are selected for connecting one or more corresponding particular expansion cards, based on the size, dimensions, and/or function of the particular expansion cards to be connected.

Abstract: The present invention is directed to a method which allows for substitution of standard SAS ALIGN primitives with an alternative, more spectrally pure set of SAS ALIGN primitives that allows for enhanced continuous adaptation performance. Two consenting SAS devices which are connected to each other may negotiate for and start communicating using the alternate set of ALIGN primitives, which may allow for improved jitter tolerance and reduced bit error rate.

Abstract: The present invention provides a system and method for controlling data entries in a hierarchical buffer system. The system includes an integrated circuit device comprising: a memory core, a shared data bus, and a plurality of 1st tier buffers that receive data from the memory. The system further includes a 2nd tier transfer buffer that delivers the data onto the shared data bus with pre-determined timing. The present invention can also be viewed as providing methods for controlling moving data entries in a hierarchical buffer system. The method includes managing the buffers to allow data to flow from a plurality of 1st tier buffers through a 2nd tier transfer buffer, and delivering the data onto a shared data bus with pre-determined timing.

Abstract: Disclosed are a method and a computer program storage product for dynamically stabilizing a stream processing system. The method includes receiving at least one computing resource allocation target. A plurality of downstream processing elements and an upstream processing element are associated with at least one input buffer. Each of the downstream processing elements consumes data packets produced by the upstream processing element received on an output stream associated with the upstream processing element. A fastest input rate among each downstream processing element in the plurality of downstream processing elements is identified. An output rate of the upstream processing element is set to the fastest input rate that has been determined for the plurality of downstream processing elements.

Abstract: An interface device for input device includes a motherboard, a connector, a first video graphics array (VGA) interface electronically connected to motherboard, a second VGA interface electronically connected with the first VGA interface and a display. The connector is positioned on the display and electronically connected to the second VGA interface. The motherboard controls the connector via the first VGA interface and the second VGA interface to communicate with an input device mated with the connector.

Abstract: The present invention is directed to a universal serial bus (USB) transaction translator and a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, wherein the counting value of the SOF counter is compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves the predefined value or is greater than the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time.

Abstract: To increase the number of analog inputs at low cost, an analog input system includes: one or more analog slave units each connected to a bus to which a CPU unit is connected, and each including an A/D-conversion device converting an analog value outputted by an external device into a first digital value, a buffer memory buffering a second digital value to be transferred to the CPU unit, and a nonvolatile storage device containing specific information of its own unit; and an analog master unit connected to the bus and including an operation section performing operation processing based on the specific information stored in the storage device with the first digital value being used as an input, to calculate the second digital value, the master unit performing on each of the slave input units the operation processing and processing of transferring the calculated second digital value to the buffer memory.

Abstract: A system includes a hard disk controller configured to, using only a single pin, transfer serial information from the hard disk controller. The serial information includes control data associated with control of both write operations and read operations. The serial information includes a first bit indicating a start of the control data, a predetermined number of bits of the control data following the first bit, and a second bit indicating an end of the predetermined number of bits of the control data. A read/write channel is configured to receive the serial information and perform the write operations and the read operations based on the serial information.

Abstract: A circuit arrangement and method facilitate the direct streaming of data between producer and consumer circuits (12P, 12C) that are otherwise configured to communicate over an address-based network (18). Sync signals (46, 56) are generated for each of producer and consumer circuits (12P, 12C) from the address information encoded into requests that communicate the data streams output by the producer circuit (12P) and expected by the consumer circuit (12C). The sync signals (46, 56) for the producer and consumer circuits (12C) are then used to selectively modify the data stream output by the producer circuit (12P) to a format expected by the consumer circuit (12C). Typically, such modification takes the form of inserting data into the data stream when the consumer circuit (12C) expects more data than output by the producer circuit (12P), and discarding data communicated by the producer circuit (12P) when the consumer expects less data than that output by the producer circuit (12P).

Abstract: A method for trimming a cycle time of an adjustable oscillator to match a Controller Area Network-bus (CAN-bus) operating with a predetermined bit time includes determining a measured number of cycles of an adjustable oscillator between a first signal and a second signal within a CAN frame transmitted on a CAN-bus; determining an information about a present cycle time of the adjustable oscillator using the measured number of cycles and a nominal number of cycles per bit time; and trimming a cycle time of an adjustable oscillator to match the CAN-bus operating with a predetermined bit time based on the determined information.

Abstract: A webcasting system and the audio data regulating methods to be used in the webcasting system are presented. The webcasting system includes a host and an audio playing apparatus. The host, which is loaded with an operating system and drivers, determines the audio data output according to an expected data received by the operating system. The drivers provide the expected data according to the audio data received and transform the audio data for network transmission. The audio playing apparatus receives the network data and processes the network data for audio playing.

Abstract: Techniques for adaptive data transfer are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for adaptive data transfer comprising receiving a write request at an application protocol layer, buffering the write request, transferring to electronic storage a first portion of data of the buffered write request using a first setting value in a range, measuring, a transfer rate of the first portion of transferred data, varying the first setting value by a small amount in a first direction to identify a second setting value, transferring to electronic storage a second portion of data of the buffered write request using the second setting value, measuring a transfer rate of the second portion of transferred data, and replacing the first setting value with the second setting value if the transfer rate of the second portion of transferred data is greater than the first transfer rate.

Abstract: A method for transmitting packets, including forwarding a first set of upstream packets and a first set of local packets by inserting at least one of the first set of local packets between subsets of the first set of upstream packets according to a first insertion rate; calculating a second insertion rate after forwarding a predetermined number of upstream packets generated by a single upstream source, by dividing a cardinality of the first set of upstream packets by a greatest common divisor of the predetermined number and the cardinality of the first set of upstream packets; and forwarding a second set of upstream packets and a second set of local packets from the local switch to the downstream switch by inserting at least one of the second set of local packets between subsets of the second set of upstream packets according to the second insertion rate.

Abstract: Data received over a shared network interface is directly placed by the shared network interface in a designated memory area of a host. In providing this direct memory access, the incoming data packets are split, such that the headers are separated from the data. The headers are placed in a designated area of a memory buffer of the host. Additionally, the data is stored in contiguous locations within the buffer. This receive and store is performed without interruption to the host. Then, at a defined time, the host is interrupted to indicate the receipt and direct storage of the data.

Abstract: A communication speed control application sets the initial communication mode of the USB controller to a full speed mode through a USB driver. If a data transfer start request is received from a USB device using application and if the requested communication speed is a high speed communication mode, the communication speed mode of the USB controller is changed to a high speed mode through the USB driver. The USB application estimates the transfer rate required for the data transfer to be executed and, if the estimated transfer rate is higher than the full speed mode or the transfer rate resulting from subtraction of a predetermined margin from the full speed, the requested communication speed is set to the high speed or is set to full speed otherwise.

Abstract: This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided.

Abstract: A method and computer program product for sending a data request from a host bus adapter logic processor to a hard disk drive, setting a standard time out period for receiving a reply from the hard disk drive, sensing vibration in the hard disk drive, sending a vibration alert signal from the hard disk drive to the host bus adapter logic processor in response to the sensed vibration exceeding a predetermined amount of vibration, and, in response to receiving the vibration alert signal from the hard disk drive, the host bus adapter logic processor establishing an extended time out period for receiving the reply. The rotational vibration sensor used by the hard disk drive for repositioning the read/write head may also be used to sense the vibration and form the basis for the vibration alert signal, such as a vibration error code. By extending the time out period during high vibration events, the hard disk drive can ride out the event without being tagged as having failed.

Abstract: Methods and apparatus for enhancing efficiency (e.g., reducing power consumption and bus activity) in a data bus. In an exemplary embodiment, a client-driven host device state machine switches among various states, each comprising a different polling frequency. A client device on the data bus (e.g., serial bus) checks for non-productive periods of polling activity, and upon discovering such a period, informs the host. The state machine then alters its polling scheme; e.g., switches to a lower state comprising a reduced polling frequency, and polling continues at this reduced frequency. In one variant, the client device continuously monitors itself to determine whether it has any data to transmit to a host device and if so, the host is informed, and the state machine restarts (e.g., to its highest polling state). By eliminating extraneous polling, power consumption and serial bus activity is optimized, potentially on both the host and the client.

Abstract: Devices and methods for generating timing signals at a rate that matches a rate of remotely generated timing signals are provided. In some embodiments, a host generates timing signals in accordance with a USB specification, such as keep-alives, start-of-frame packets, or ITPs. An upstream facing port transmits the timing signals over a network to a downstream facing port. The downstream facing port generates and transmits timing signals to a USB device at a predetermined rate, and alters the predetermined rate based on an analysis of the rate at which timing signals are received from the upstream facing port.

Abstract: An asynchronous upsizing circuit in a data processing system. The asynchronous upsizing circuit includes an asynchronous packer and an asynchronous unpacker. The asynchronous packer includes a write buffer commonly used for an asynchronous bridge and for upsizing and for buffering a write channel data; and first and second asynchronous packing controllers controlling channel compaction according to first and second clocks, respectively, regarding the write channel data inputted/outputted to/from the write buffer during a burst write operation. The asynchronous unpacker includes a read buffer commonly used for an asynchronous bridge and for upsizing and for buffering a read channel data; and first and second asynchronous unpacking controllers controlling channel compaction according to the first and second clocks, respectively, regarding the read channel data inputted/outputted to/from the read buffer during a burst read operation.

Abstract: A process is provided for transferring a first sequence control and/or first data into a first control device and a second sequence control and/or second data into a second control device in a motor vehicle. The transfer is carried out by way of a first data bus while using a first transmission protocol which has a data frame with a predetermined frame format or message format, and the transfer as a whole takes place by the transmission of a plurality of data frames. In a first step, by way of a first data frame, a portion of the first sequence control and/or of the first data is transmitted to the first control device. In a second step, by way of the second data frame, a portion of the second sequence control and/or of the second data is transmitted to the second control device.

Abstract: A data transmission system is provided. The data transmission system includes a source device having a source device controller and a register and a sink device having a sink device controller. The data transmission system also includes a transmission link coupling the source device and the sink device. The transmission link includes a unidirectional main line having a plurality of main link channels, a bidirectional auxiliary line configured to transmit data between the source device and the sink device at a first data rate, and a unidirectional interrupt line. The transmission link is configured to transmit data from the source device to the sink device over one of the main link lines at a second data rate and to transmit data from the sink device to the source device over the auxiliary line at the second data rate. The transmission link may comply with the DisplayPort standard, and the data may be transmitted in accordance with the USB standard.

Abstract: This disk array subsystem includes a data input/output unit for inputting and outputting data in and from the network, a connecting unit for connecting the data input/output unit and a plurality of storage apparatuses, and a control unit for controlling the input and output of data in and from the network. The control unit includes a logical link setting unit for zoning at least one or more physical links among a plurality of physical links for inputting and outputting data between the data input/output unit and the connecting unit, or between the connecting unit and the connecting unit into at least one or more logical links, and setting a plurality of logical links to one physical link; and a link unit for simultaneously multiplexing the data to a plurality of the logical links set with the logical link setting unit, and linking the data to the physical link.

Abstract: A system and method for enabling legacy media access control (MAC) to do energy efficient Ethernet (EEE). A backpressure mechanism is included in an EEE enhanced PHY that is responsive to a detected need to transition between various power modes of the EEE enhanced PHY. Through the backpressure mechanism, the EEE enhanced PHY can indicate to the legacy MAC that transmission of data is to be deferred due to a power savings initiative in the EEE enhanced PHY.

Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit that includes both a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information for an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

Abstract: An interface device for input device includes a motherboard, a connector, a first video graphics array (VGA) interface electronically connected to motherboard, a second VGA interface electronically connected with the first VGA interface and a display. The connector is positioned on the display and electronically connected to the second VGA interface. The motherboard controls the connector via the first VGA interface and the second VGA interface to communicate with an input device mated with the connector.

Abstract: One embodiment of the present invention sets forth a technique for arbitrating requests received by an L1 cache from multiple clients. The L1 cache outputs bubble requests to a first one of the multiple clients that cause the first one of the multiple clients to insert bubbles into the request stream, where a bubble is the absence of a request. The bubbles allow the L1 cache to grant access to another one of the multiple clients without stalling the first one of the multiple clients. The L1 cache services multiple clients with diverse latency and bandwidth requirements and may be reconfigured to provide memory spaces for clients executing multiple parallel threads, where the memory spaces each have a different scope.

Abstract: A controller for a host system includes an interface and a buffer. The interface receives a plurality of data units isochronously received from a connected device, and the buffer stores the data units and then output a data block upon the occurrence of at least one condition. Each data unit stores data of a first size and the data block includes data of a second size greater than the first size. The connected device may be a Universal Serial Bus (USB) device or another type of device.

Abstract: A system selectively drops data from queues. The system includes a drop table that stores drop probabilities. The system selects one of the queues to examine and generates an index into the drop table to identify one of the drop probabilities for the examined queue. The system then determines whether to drop data from the examined queue based on the identified drop probability.

Abstract: A method according to one embodiment includes receiving a request to perform a backup of data associated with an application running on multiple servers; communicating with I/O Handlers on the servers for initiating a coordinated backup operation on the data at about a same start time; and instructing the I/O Handlers to stretch communication between instances of the application and data storage volumes associated therewith during initiating the backup operation. Additional systems, methods, and computer program products are also disclosed.

Abstract: An input port is assigned to a SAS expander device. An output port is assigned to the SAS expander device. The output port and the input port are defined to be paired with each other as a primary subtractive port. Only a SAS initiator address is programmed in the route table of the SAS expander. An OPEN command is sent out the output port upon receiving the OPEN command into the input port if the DEST of the OPEN command is not a direct attached device of the SAS expander device and the DEST is not in the route table of the SAS expander device. An OPEN command is sent out the input port upon receiving the OPEN command into the output port if the DEST of the OPEN command is not a direct attached device of the SAS expander device and the DEST is not in the route table of the SAS expander device.

Abstract: A first network device includes a first port to provide first data traffic to a first storage area network, a second port to provide second data traffic to a local area network, and memory shared between the first port and the second port to temporarily store the first data traffic in N first buffers and the second data traffic in M second buffers. A queue control module allocates a first memory space of the N first buffers to the first port and a second memory space of the M second buffers to the second port. An adjustment module adjusts a first amount of the first memory space and a second amount of the second memory space in response to a congestion event is caused by a first data traffic. Up to all of the first memory space and the second memory space is allocated to the N first buffers.

Abstract: Methods and apparatus related to techniques for translating requests between a full speed bus and a slower speed device are described. In one embodiment, a translation logic translates requests between a full speed bus (such as a front side bus, e.g., running relatively higher frequencies, for example at MHz levels) and a much slower speed device (such as a System On Chip (SOC) device (or SOC Device Under Test (DUT)), e.g., logic provided through emulation, which may be running at much lower frequency, for example kHz levels). Other embodiments are also disclosed.

Abstract: The use of asymmetric signalling over channels is disclosed. Pursuant to one or more embodiments of the invention, the channels in the parallel bus operate as standard non-differential interconnects for data travelling in one direction through the bus, and operate as differential interconnects for data travelling in the other direction through the bus. So that data capacity of the bus remains the same in both directions, the data rate during differential transmission can be twice that of the data rate during standard transmissions. Asymmetric signalling can also occur over two unidirectional busses of channels to the same effect.

Abstract: A DMA transfer control device comprises: a DMA arbiter that performs DMA transfer for each DMA channel formed by a combination of a memory and a plurality of input/output devices and DMA controller circuits that control the DMA arbiter; a judgment unit and a transfer time calculation unit that calculates a next DMA transfer scheduled time based on the DMA transfer size for a DMA transfer request and a judgment time. A timer counter that times the judgment time at a unit time interval, and a comparator that compares the judgment time at which a DMA transfer request arrives with the DMA transfer scheduled time are also provided, and the judgment unit sends the DMA transfer permission to the DMA arbiter when an output of the comparator indicates that the judgment time is not earlier than the DMA transfer scheduled time. The efficiency of data transfer by dynamically controlling DMA transfer is performed.

Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit that includes both a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information for an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

Abstract: The present invention discloses a method for processing data of a flash memory by differentiating levels, which includes steps of separating the communication between a host and a flash memory by a high-level translation layer (HTL) and a low-level abstraction layer (LAL). The HTL receives commands and logical addresses from the host and translates the received logical addresses to the physical addresses of the flash memory. The LAL executes data processing to the corresponding memory cells according to the commands and the physical addresses from the HTL. Since the LAL is disposed between the HTL and the flash memory, the HTL is irrelevant to the structure of the flash memory, and does not have to re-designed with the flash memory which is replaced with another new flash memory.

Abstract: One embodiment of the present invention sets forth a technique for arbitrating requests received from one of the multiple clients of an L1 cache and for providing hints to the client to assist in arbitration. The L1 cache services multiple clients with diverse latency and bandwidth requirements and may be reconfigured to provide memory spaces for clients executing multiple parallel threads, where the memory spaces each have a different scope.

Abstract: Implementations of the present invention relate in part to optimizations to peer-to-peer communication systems. For example, one implementation relates to use of a smart transceiver that creates, caches, and manages communication channels dynamically between peers. Another implementation relates to use of a central tracking object that can be used to efficiently register and distribute peer messages among the various peers. In one implementation, the central tracking object is shared amongst peers in the group. Still another implementation relates to associating peer groups with namespaces, and for including peer groups of one namespace within still other peer groups of different namespaces. These and other aspects of the invention can also be used to ensure delivery intent of a given peer message is preserved, and to ensure that optimal numbers of messages are communicated to any given peer at any given time.

Abstract: The present invention relates to a device, system and method for controlling a data acquisition device and inserting the acquired data into the memory of an electronic device with minimal buffering of the data. An interface device, separate from the electronic device and capable of highly accurate timing, controls a data acquisition device. This interface device provides an interface between real time data and non real time operating system running on the electronic device. By sending data to a non-real time system in a near real-time manner, the non-real time system can continue the processing of the data either in near real time, or it can store the data for later processing.

Abstract: A method that includes, by one or more computer systems, determining a data retrieval rate policy based on at least one data retrieval rate parameter. The method also includes determining at least one storage subsystem performance parameter. The method further includes determining a fragmentation value based on the data retrieval rate policy and the at least one storage subsystem performance parameter. The method additionally includes determining a storage subsystem fragmentation of a first data object. The storage subsystem fragmentation includes fragmenting the first data object into a plurality of first data object fragments. The method also includes deduplicating the first data object based on the fragmentation value and the storage subsystem fragmentation.

Abstract: Disclosed are a method, upstream processing node, and computer readable medium for dynamically stabilizing a stream processing system. The method includes receiving at least one computing resource allocation target. The method further includes determining that an input data flow rate of at least one upstream processing element varies. The computing resource is dynamically allocated to the upstream processing element in response to the input rate of the upstream processing element varying. Data flow is dynamically controlled between the upstream processing element and at least one downstream processing element.

Abstract: A computerized system and method for processing network content associated with multiple virtual domains. The processing may include anti-malware scanning and/or content filtering. The content associated with multiple domains may be processed in the same daemon process. In response to connection requests from virtual domains, the service process creates separate sockets to communicate with each virtual domain. A global configuration management module is used to provide configuration parameters for each session to the service process. A logging manager processes both the global logs and the logs from each virtual domain. Alternatively, the service process may initiate other service processes to handle incoming connections from one or more virtual domains, in order to better utilize resources in a multiple-CPU environment.

Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit includes a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock, and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information concerning an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

Abstract: A method for generating a device description for a measuring apparatus in a target field bus protocol is described. The method comprises the reception of a first device description of the apparatus. The first device description of the apparatus comprises at least one variable. The at least one variable is related to a storage cell of the apparatus. The target field bus protocol is selected from a plurality of field bus protocols, and at least one block is formed from the at least one variable. The at least one block has a maximum block size that corresponds to the smallest maximum block size of at least two field bus protocols of the plurality of field bus protocols. The maximum block size can be transmitted via a field bus with a single request when the respective field bus protocol is used. Subsequently, the at least one block is provided as device description for the apparatus in the target field bus protocol.

Abstract: Various embodiments are described for data communication between a host device and a mobile communication device having two processors. In a first mode of operation, data communication occurs between the host device and a main processor of the mobile device. In a second mode of operation, data communication occurs between the host device and a communications processor of the mobile device. Some of the embodiments also implement power transfer from the host device to the mobile device.

Abstract: An interface configured to support a signaling protocol between a first hardware component and a second hardware component. The interface comprises a first pin, a second pin, and a third pin. The first pin is configured to provide a write clock signal sourced from the first hardware component to the second hardware component during a write operation. The second pin is configured to receive a read clock signal sourced from the second hardware component during a read operation. The third pin is configured to transfer serial control information from the first hardware component to the second hardware component during both the read operation and the write operation. Only the third pin is used to transfer the serial control information. The serial control information includes control information for both the read operation and the write operation.

Abstract: In a method of adjusting transfer speed after initialization of a SATA interface, a SATA link device transmits a first predetermined primitive to a SATA link partner for requesting to change a first transfer speed of the SATA link device from a first speed to a second speed, the SATA link partner replies to the SATA link device with a second predetermined primitive according to the first predetermined primitive, and the SATA link device and the SATA link partner respectively adjust the first transfer speed of the SATA link device and a second transfer speed of the SATA link partner according to the second predetermined primitive.