Abstract: Systems, methods, and media for managing the print speed of a variable speed printer are disclosed. Embodiments include a print controller system having a raster image processor for rasterizing a print job to create a plurality of rasterized pages and a printer controller buffer for storing one or more of the rasterized pages. The printer controller buffer may also transmit at a print engine feed rate the one or more rasterized pages to a print engine. Embodiments may also include a speed control module in communication with the printer controller buffer for determining the print engine feed rate. Further embodiments may include the speed control module determining the print engine feed rate based on one or more of page processing times, page arrival rates, estimated print completion rates, and the number of pages in a print engine buffer.

Abstract: A controller assembly is adapted for regulating at least one valve having a valve positioner. The controller assembly comprises a digital controller having a plurality of data inputs and data outputs and includes at least one proportional-integral-derivative (PID) controller operative to modulate the valve positioner in response to data received at the data inputs. The digital controller is configured to perform the following functions within a total time period of no greater than 10 ms: acquisition of data at the data inputs, processing of the data, and transmission of data from the data output in order to regulate the valve(s). The digital controller may include a quantity of at least sixteen digital inputs, at least sixteen digital outputs, at least eight analog inputs and at least eight analog outputs.

Abstract: A method to set a communication speed in a Serial-Attached Small Computer System Interface (“SAS”)/Serial-ATA (“SATA”) distance extender apparatus comprising a plurality of supported communication speeds and a local communication speed, a fibre channel interface, a memory, a processor, and a communication bus interconnecting the SAS/SATA Interface, the Fibre Channel interface, the memory, and the processor. The method detects traffic received by the Fibre Channel interface, and determines if the traffic comprises a SAS/SATA Open Address frame. If the traffic comprises a SAS/SATA Open Address frame, the method then determines if the local communication speed matches a communication speed utilized by an interconnected remote SAS/SATA Interface. If the local communication speed matches a communication speed utilized by an interconnected remote SAS/SATA Interface, the method transmits the traffic using the local SAS/SATA Interface.

Abstract: In certain, currently available data-storage systems, incoming commands from remote host computers are subject to several levels of command-queue-depth-fairness-related throttles to ensure that all host computers accessing the data-storage systems receive a reasonable fraction of data-storage-system command-processing bandwidth to avoid starvation of one or more host computers. Recently, certain host-computer-to-data-storage-system communication protocols have been enhanced to provide for association of priorities with commands. However, these new command-associated priorities may lead to starvation of priority levels and to a risk of deadlock due to priority-level starvation and priority inversion. In various embodiments of the present invention, at least one additional level of command-queue-depth-fairness-related throttling is introduced in order to avoid starvation of one or more priority levels, thereby eliminating or minimizing the risk of priority-level starvation and priority-related deadlock.

Abstract: Methods and apparatus for rate control are provided. An isochronous circuit controls data transmission between a first device and a second device. The first device outputs a set of data packets to the isochronous circuit at a first data rate, and the second device pulls the set of data packets from the isochronous circuit at a second data rate. The isochronous circuit comprises a buffer, a rate calculator and a register. The buffer buffers the set of data packets bound to the second device through a USB. The rate calculator monitors occupation of the buffer to estimate the second data rate. The register is coupled to the rate calculator for storage of the second data rate. The first device may access the estimate of the second data rate from the register to update the first data rate.

Abstract: An interface supports a signaling protocol between a first hardware component and a second hardware component. The interface includes a first pin to provide a first clock signal sourced from the first hardware component to the second hardware component during a first operation, the first operation being an operation in which data is being transferred from the first hardware component to the second hardware component. A second pin to receive a second clock signal sourced from the second hardware component during a second operation, the second operation being an operation in which data is being transferred from the second hardware component to the first hardware component. A third pin to provide a first gate control signal sourced from the first hardware component to the second hardware component, the first gate control signal to synchronize data transfer between the first hardware component and the second hardware component during both the first operation and the second operation.

Abstract: This invention is a system and method for managing the use of available bandwidth for a link used for movement of data being copied in a data storage environment.

Abstract: A hard disk controller comprises a first circuit that transmits a first signal to control data transfer between the hard disk controller and a read/write channel. A second circuit transmits or receives data under control of the first signal. A third circuit transmits a second signal to control data transfer between a storage media and the read/write channel. A mode circuit transmits mode data under control of the second signal. A read channel circuit comprises a data circuit and a first circuit that receives a first signal that controls the transfer of data to and from the data circuit. A second circuit transmits or receives data under control of the first signal. A mode circuit receives mode data under control of a second signal. Data is transferred to and from the input/output circuit in accordance with the second signal.

Abstract: A method for handling input/output (I/O) commands in a storage system includes establishing first and second counters for counting unfinished I/O commands, and establishing a reference which is initially set to the first counter. The reference is periodically switched between the first counter and the second counter, and the switching interval is less than the I/O timeout value. Upon placing an I/O command into an I/O command queue, a copy of the current reference is made into an I/O specific control block and the current referenced counter is incremented. Upon finishing of an I/O command, the counter referenced by the I/O specific control block is decremented and the I/O command is removed from the I/O command queue. When switching the reference, a problem is detected in the event that the counter being switched to is above a predetermined threshold. Upon detection of a problem, a more explicit I/O check is conducted.

Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a master in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from the master to the shift registers for serialization, where the mechanism provides deserialized information received from the shift registers to the master, and where the mechanism inserts one or more wait cycles in communication with the master during the serialization and deserialization.

Abstract: Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a slave in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from a bus matrix to the shift registers for serialization and communication to the slave, where the mechanism provides deserialized information received from the shift registers to a bus matrix. The mechanism inserts one or more wait cycles in communication with the matrix during the serialization and deserialization.

Abstract: The invention relates to a slave bus subscriber for a serial data bus with a master bus subscriber, wherein the slave subscriber recognizes the bit rate of a data packet received over the data bus, whose header has a sync break field, a sync field and an ID field, with the help of the header of the data packet in such a manner that the periods between falling edges of bits having known bit intervals at least of the sync field and of the sync break field are evaluated and the bit rate is determined from the evaluated periods.

Abstract: Point-to-point links between devices are brought up at a slowest available speed, and a faster link speed is negotiated after reaching an operational state.

Abstract: A distributed buffering system includes at least one input buffer, at least one serializing module, a at least one deserializing module, at least one output buffer, and a programmable logic device. The input buffer is operably coupled to store at least one data block of incoming data. The serializing module serializes the data block as it is retrieved from the input buffer to produce a serial stream of data. The programmable logic device receives the serial stream of data and distributes it to one or more of the at least one deserializing modules. The at least one deserializing module converts the serial stream back into the data block. The recaptured data block is then provided to the corresponding output buffer, which stores the recaptured data.

Abstract: A media access controller to adapt a rate of an output signal to a rate of an output medium is provided. The media access controller includes a register configured to output data to an external device, said register comprising a first input configured to control an output of the register and a second input configured to control an input to said register. The media access controller also includes a receiver configured to accept a signal from an external clock over the output medium and to provide said external clock signal to said first input of said register. An internal clock in the media access controller is configured to provide an internal clock signal from said internal clock to said second input of said register.

Abstract: Systems and methods for performing data transfer rate throttling o improve the effective data transfer rate for SATA storage devices. The data transfer rate is diluted by inserting ALIGN primitives when data is sent. The receiving device simply discards the ALIGN primitives. Therefore, the receive data FIFO does not fill as quickly and fewer flow control sequences are needed for flow control to prevent the receive data FIFO from overflowing. An advantage of using the ALIGN primitives instead of conventional flow control is that the round-trip handshake latency is not incurred to disable and later enable data transfers.

Abstract: Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit.

Abstract: A client device receives streaming content from a host device. The streaming content is placed in one or more buffers prior to processing. Monitoring as to the capacity and fullness of the buffers is performed at the client device and information is sent to the host device. The host device adjusts the rate or flow of the streaming content based on the information provided by the client device.

Abstract: A disk array apparatus using an SAS can transfer data without lowering a transfer efficiency of data even if rates of a plurality of physical links connected to a controller and storage device are different. A plurality of HDDs are connected to a controller through an expander. Data are transferred from the controller to the expander and then to HDD. In this connection, the controller and the expander transfers a set of transfer data in a plurality of the HDD-side physical links. The controller-side physical link integrates the transfer data, and multiplexes them to transfer. A plurality of HDDs-side physical links separates the transfer data to transfer in parallel.

Abstract: Described is a system and method for frequency offset testing. The system comprises an electronic device, a first testing device providing a reference clock signal at a first frequency to the electronic device, and a second testing device receiving data from the electronic device at the first frequency and transmitting data to the electronic device at a second frequency. The second frequency is equal to a product of the first frequency and a frequency offset value.

Abstract: A method for defining a cycle time for a transmission cycle on a system bus of a monitoring and/or control system having at least one communication module and at least one input/output module, which is connected to the communication module via the system bus for transmitting measurement and/or control signals and is intended to input and/or output measurement and/or control signals to field applications, the at least one communication module having a time control unit for controlling a transmission cycle which is constantly repeatedly carried out and has defined communication times for the communication and input/output modules which are connected to the system bus, comprises measuring the signal propagation times on the system bus and defining the cycle time for a transmission cycle on the system bus on the basis of the longest signal propagation time measured.

Abstract: Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.

Abstract: A first processor that executes at least one application or process includes a first interface module that interfaces the first processor to a second processor and that includes N interfaces. N is an integer greater than 1. The first processor also includes a first communication control module (CCM) that selects M of the N interfaces based on bandwidth requested by the at least one application to transmit data generated by the at least one application to the second processor.

Abstract: An audio input/output control apparatus, in which the speed difference between writing speed in writing audio data to a ring buffer and reading speed in reading out the audio data under a constant speed is calculated. When a read-address is forcibly changed according to the speed difference, between the signal level of the audio data corresponding to a read-address before the change and the signal level of the audio data corresponding to a read-address after the change, an address position at which the signal level change is less than a predetermined value is determined as a read-address after the change. So, the amount of signal processing can be significantly reduced, and the quality of audio data can be maintained.

Abstract: A universal serial bus (USB) with single port and a host controller thereof are provided. The USB comprises a USB port, a speed detection circuitry, a start of frame (SOF) generator, and a host controller. The USB port is electrically coupled to an external circuitry. The speed detection circuitry is electrically coupled to the USB port for detecting a transmission speed between the USB and the external circuitry via the USB port to provide a detecting result. The SOF generator is electrically coupled to the speed detection circuitry for receiving the detecting result and outputting a SOF signal, to determine a cycle of the SOF signal based on the detecting result. The host controller is electrically coupled to the SOF generator and the speed detection circuitry for adjusting the host controller based on SOF signal cycle to comply with the USB 2.0, USB 1.1 and USB 1.0 transmission standards.

Abstract: A data backup system comprises a USB flash drive that includes an emulation component and a flash memory. The emulation component is configured to represent the flash memory as if it were an auto-launch device. Accordingly, a data source, such as a personal computer, will interact with the flash memory as if it were the auto-launch device. As some operating systems are configured to recognize auto-launch devices upon connection and automatically execute applications stored thereon, merely connecting the USB flash drive to a data source running such an operating system will cause a backup application stored by the flash memory to automatically execute on the data source. Here, the backup application is configured to selectively back up data files from the data source to a networked storage such as a server of a commercial service provider.

Abstract: A method for initializing a fiber channel link upon a failure of a standard speed negotiation algorithm is provided. The standard speed negotiation algorithm is disabled. A link speed is set to a highest possible link speed not yet attempted outside the standard speed negotiation algorithm, initializing the fiber channel link if the link speed is negotiated at a maximum link speed. If the link speed is negotiated at a speed less than the maximum link speed, the standard speed negotiation algorithm is reattempted, initializing the fiber channel link according to the standard speed negotiation algorithm if the reattempt is successful.

Abstract: A tape drive, tape drive recording system, and method are provided for improving tape speed selection during data transfer. The tape drive comprises a buffer, a tape for recording the data to be temporarily stored in the buffer, and a read head. The tape drive further comprises a reading controller that initially sets a tape speed such that a drive transfer rate matches a host transfer rate as closely as possible and that drives the tape at the tape speed. To address backhitching caused by one or more host transfer halts, the reading controller subsequently adjusts the tape speed such that the drive transfer rate is lower than the host transfer rate by recalculating the host transfer rate in consideration of the host transfer and the host transfer halt and setting the tape speed such that the drive transfer rate matches the recalculated host transfer rate as closely as possible.

Abstract: A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably lower than the second range of data rates and preferably the first number of channels is higher than the second number of channels which preferably is 1. For backward compatibility with existing devices, the first number of channels in each interface preferably is four. Each channel preferably includes a physical medium attachment module and a physical coding sublayer module. Each of the higher-speed channels in the second number of channels preferably also includes a clock management unit, while the lower-speed channels in the first number of channels preferably share one or more clock management units.

Abstract: Circuits, methods, and apparatus that allow a DisplayPort compatible host device to control data transactions over an I2C bus when communicating with a legacy monitor. One example includes an adapter having a compatibility register that may have a number of locations, where at least some of the locations correspond to I2C bus speeds. Values stored at these locations can indicate whether the adapter is compatible or incompatible with the corresponding I2C bus speed. Another example includes an adapter having a speed register that may have a number of locations, where at least some of the locations correspond to I2C bus speeds. A defined value written to one of these locations dictates the corresponding I2C bus speed.

Abstract: A method for connecting a universal serial bus (USB) device to a USB host is disclosed. The method for connecting the USB device to a USB host includes detecting a connection to the USB host; controlling the USB host not to recognize the connection of the USB device; selecting one of USB modes provided by the USB device; and controlling the connection so as to allow the USB host to recognize the selected USB mode.

Abstract: A system for data processing comprises a host circuit (104) and an integrated circuit (102), the host circuit (104) being external to the integrated circuit (102). The integrated circuit (102) includes a plurality of programming elements (300), each element (300) including a host interface (606) for receiving data and a first control signal from the host circuit (104), a control interface (604) for receiving a second control signal. Each element (300) includes a crosspoint switch (318), and a register array (628) for receiving and storing data from the crosspoint switch (318) according to the first and second control signals, for receiving and storing data from the host interface (606) according to the first and second control signals, and for communicating stored data to the crosspoint switch (318) according to the first and second control signals.

Abstract: Based on user identification data transmitted together with a compressed data from a portable reproducing apparatus, if an apparatus recognizes that a user who purchased and downloaded the compressed data is the same as a user who owns the apparatus, the audio apparatus stores and holds the compressed data after reproducing the signal from the compressed data by the decoder unit and the data processing unit. Alternatively, if it recognizes that the user who purchased and downloaded the compressed data is not the same as the user who owns the apparatus, it removes the compressed data after reproducing the signal from the compressed data by the decoder unit and the data processing unit.

Abstract: Embodiments of the present invention provide a media drive that is intended for reduction in power consumption required for serial communications to/from a host, and a power saving method thereof. In one embodiment, a HDD includes: a cache; a host interface for transferring, to a host, transfer data read out from the cache; a host interface manager that controls the execution of commands so as to generate a transfer unnecessary period during which a command and transfer data need not be exchanged with the host; and a MPU that brings a serial communication part of the host interface into a power save mode during the transfer unnecessary period. The host interface manager determines the optimum data transfer timing of transferring data from the cache to the host on the basis of a transfer rate at which data is transferred to the host, and a read rate at which data is read out from a disk into the cache.

Abstract: An industrial controller may communicate with a number of input/output (I/O) modules using an optimized connection packet assembled by a scanner communicating directly with the I/O modules and forwarding the optimized connection packet to the industrial processor. The optimized connection packet is communicated over a connection as part of a connected messaging system used to ensure highly reliable network communication. The need for higher data rates for some I/O modules as part of the optimized connection packet may be accommodated through the opening of a second redundant connection that provides the high-data-rate data in an interleaving fashion with the optimized connection packet, without upsetting the optimized connection packet or changing the use of the data by the industrial control program.

Abstract: A method, system, and computer-usable medium for coupling a collection of devices to a bridge, wherein the collection of devices includes high-performance devices and low-performance devices, coupling a data bus to the bridge, utilizing a collection of transfer credits to allow transfer of commands to the collection of devices, transferring commands to the collection of devices only when at least one transfer credit is available, and in response to determining a number of transfer credits falls below a predetermined threshold, utilizing a command arbitration scheme that gives priority to commands to the high-performance devices among the collection of devices.

Abstract: A method, apparatus and program storage device for managing dataflow through a processing system is disclosed. A buffer monitor maintains and monitors a buffer full threshold to control the write throughput to a data bus.

Abstract: A method of dynamically allocating the amount of input/output (I/O) rate capacity to partitions in a computer system includes determining a total amount of I/O rate capacity and an economic value of each partition within the partitioned computer system. The economic value is defined as a performance-valued product established for each partition wherein the sum of all performance-value products for each partition defines a total economic value for the computer. The I/O rate to be allocated to each partition is calculated to be a portion of the total amount of I/O rate capacity where the portion allocated to each partition is proportional to the economic value of that respective partition. The calculated rate allocations are recorded in memory which is accessible to each partition. After recording, each partition regulates its I/O usage according to the recorded allocation.

Abstract: An isolated data acquisition device including a plurality of data acquisition channels, an isolated system management unit coupled to the data acquisition channels, a host system management unit, a serial bus coupled to the host system management unit and the isolated system management unit, and isolation circuitry coupled to the serial bus. The isolation circuitry electrically isolates the host system management unit from the isolated system management unit and the data acquisition channels. During operation, the isolated system management unit and the host system management unit may each store data associated with one or more pending bus transactions. Each of the system management units may select at least one of the pending bus transactions according to a predetermined priority scheme, encode and serialize the data associated with the selected bus transaction, and transmit the serialized data across the isolation circuitry to the other system management unit via the serial bus.

Abstract: A read process in a memory device is optimized. Sub-pages of a page of data are read from storage elements by an internal controller of the memory device at a read speed of the internal controller. At a specific time, the controller sets a READY signal to inform an external host to start reading out data from the buffer in a continuous burst, at the associated read speed of the host, which can differ from the controller's read speed, and asynchronous to the internal controller. The READY signal is set so that the host can complete its burst before the buffer runs out of data, while overall read time is minimized. The controller can also be configured for use with hosts having different read speeds. A host may communicate an identifier to the controller for use in determining an optimum time to set the READY signal.

Abstract: Timing of a write and read strobes for a memory having a double data rate (DDR) interface are automatically adjusted using write-read operations. A first and a second value of the write and read strobes are determined for a first write-read operation having the read data match the write data. A second write-read operation is performed for each of a plurality of third values for the write strobe at the second value for the read strobe set. A center of the third values having the read data match the write data is determined. A third write-read operation is performed for each of a plurality of fifth values for the read strobe at the fourth value of the write strobe. A center of the fifth values having the read data match the write data is determined. The timing of the write and read strobes are set to the centers.

Abstract: The invention relates to a system and method for controlling interfacing parameters for a device when connected to a host is provided. The method comprises: monitoring for an initial connection by the device to the host; then, while the device is establishing the connection with the host, utilizing a communication bus controller contained in a microprocessor in the device to process communications with the host at a first data transmission rate; and after a predetermined condition, re-establishing the connection with the host using a second bus controller in the device that processes the communications at a second transmission rate that is higher the first data transmission rate.

Abstract: The serial communication device capable of reducing the load on the CPU is provided for a system using the serial communications such as the car navigation system. The attention is focused on the control method of the serial communication, in which a DMA controller is used for the data reception in the serial communication, and a number larger than the number of data received at a time is set in advance as the number of transfers of the receive DMA controller, and further, the function to generate the timeout interrupt when data is not received for a certain period is added to the serial interface, so that the serial communication can be controlled and performed without applying the load on the CPU.

Abstract: A memory device includes a high speed port, a low speed port, at least a first memory bank, a first register, and a multiplexer. The at least first memory bank is shared by the high speed port and the low speed port. The first register store information that indicates which one of the ports has permission to access the first memory bank. The multiplexer connects one of the high speed port or the low speed port to the first memory bank, in response to the information stored in the first register.

Abstract: A memory system for providing a slow command decode over an untrained high-speed interface. The memory system includes a memory system having a memory interface device, an untrained high-speed interface, and a memory controller. The untrained high-speed interface is in communication with the memory interface device. The memory controller generates slow commands and transmits the slow commands to the memory interface device via the untrained high-speed interface. The slow commands operate at a first data rate that is slower than a second data rate utilized by the high-speed interface after it has been trained. The memory interface device receives the slow commands via the untrained high-speed interface, decodes the slow commands, and executes the slow commands.

Abstract: Between data accesses to a storage medium, requested by an initiator, a logical unit may need to perform autonomous operations. The logical unit receives information from the initiator to allow the logical unit to estimate whether the stream buffer of the initiator is reaching a critical level. Based on this estimate, the logical unit can determine whether to perform or continue autonomous operations such as error recovery; physical maintenance of a drive mechanism or storage medium; or relative positioning between the drive mechanism and storage medium. The estimate also allows a flexible, rather than a fixed, time-out.

Abstract: Disclosed are a method, upstream processing node, and computer readable medium for dynamically stabilizing a stream processing system. The method includes receiving at least one computing resource allocation target. The method further includes determining that an input data flow rate of at least one upstream processing element varies. The computing resource is dynamically allocated to the upstream processing element in response to the input rate of the upstream processing element varying. Data flow is dynamically controlled between the upstream processing element and at least one downstream processing element.

Abstract: A method to set a communication speed in a Serial-Attached Small Computer System Interface (“SAS”)/Serial-ATA (“SATA”) distance extender apparatus comprising a plurality of supported communication speeds and a local communication speed, a fibre channel interface, a memory, a processor, and a communication bus interconnecting the SAS/SATA Interface, the Fibre Channel interface, the memory, and the processor. The method detects traffic received by the Fibre Channel interface, and determines if the traffic comprises a SAS/SATA Open Address frame If the traffic comprises a SAS/SATA Open Address frame, the method then determines if the local communication speed matches a communication speed utilized by an interconnected remote SAS/SATA Interface. If the local communication speed matches a communication speed utilized by an interconnected remote SAS/SATA Interface, the method transmits the traffic using the local SAS/SATA Interface.

Abstract: A system manages access to a cost-constrained resource. The system includes two or more resource consumers that may request access to the cost-constrained resource. Each of the resource consumers may calculate a respective need value corresponding to an amount of data stored in a buffer of the resource consumer relative to a total amount of data that may be stored in the buffer. A concurrency arbitrator may grant access to the cost-constrained resource to a given resource consumer of the plurality of resource consumers based on need values received by the concurrency arbitrator from the plurality of resource consumers. Additionally, or in the alternative, the concurrency arbitrator may grant access to the cost-constrained resource to a given resource consumer based on an amount of data stored in a buffer of the cost-constrained resource that is to be transferred to the given resource consumer.

Abstract: A transmission method for a serial periphery interface (SPI) serial flash includes the steps of providing a first system clock signal and transmitting a plurality of data strings with each two bits of the data strings transmitted in a period of the first system clock signal. A second system clock signal is generated by the first system clock signal to provide a double frequency to enhance the transmission rate of all the data inputted into or outputted from the SPI serial flash.