Operation Scheduling Patents (Class 710/6)
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Patent number: 8135871Abstract: A computer system includes an information processing apparatus configured to incorporate a SCSI (Small Computer System Interface) command into a CBW (Command Block Wrapper), and transmits the CBW based on USB (Universal Serial Bus) protocol; and a peripheral apparatus configured to receive the CBW transmitted from the information processing apparatus, and transmit a value of a predetermined register indicating a state of a GPIO (general purpose input/output) interface to the information processing apparatus, when the SCSI command is a predetermined SCSI command. The information processing apparatus may issue the SCSI command based on an application program. The peripheral apparatus carries out a process corresponding to the SCSI command when the SCSI command is not the predetermined SCSI command.Type: GrantFiled: February 23, 2006Date of Patent: March 13, 2012Assignee: Renesas Electronics CorporationInventors: Shinya Saitou, Masashi Tominaga, Tomohiko Ohtsu
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Patent number: 8135924Abstract: A method, system, and computer usable program product for an improved data storage device driver are provided in the illustrative embodiments. For managing an elevator queue, several requests are stored in the elevator queue. A determination is made whether the elevator queue is sorted. A number of requests in the elevator queue is determined if the elevator queue is unsorted. The unsorted elevator queue is monitored. Reaching a threshold condition in the unsorted elevator queue is detected. Sorting of the unsorted elevator queue is initiated. The requests may be I/O requests for a data storage device. The elevator queue may be sorted according to an ascending or descending order of data block addresses in the requests. The monitoring may monitor a remaining number of unsorted requests in the elevator queue as requests are removed from the elevator queue. The threshold condition may be associated with a threshold value.Type: GrantFiled: January 14, 2009Date of Patent: March 13, 2012Assignee: International Business Machines CorporationInventors: James P Allen, Gary Steven Domrow, John Leslie Neemidge, Stephen M Tee
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Patent number: 8135896Abstract: A serial peripheral interface of an integrated circuit including multiple pins and a clock pin is provided. The pins are coupled to the integrated circuit for transmitting an instruction, an address or a read out data. The clock pin is coupled to the integrated circuit for inputting multiple timing pulses. The plurality of pins transmit the instruction, the address or the read out data at rising edges, falling edges or both edges of the timing pulses.Type: GrantFiled: August 5, 2010Date of Patent: March 13, 2012Assignee: Macronix International Co., Ltd.Inventors: Yu-Lan Kuo, Chun-Hsiung Hung
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Patent number: 8134791Abstract: A method of identifying a string or chain of efficient or “good enough” disc operations for processing (a pseudo optimal chain) is provided. A “pseudo optimal chain” comprises a string or chain of operations that, while not necessarily the optimal string or chain, provides an efficient sequence of operations that can be determined by comparing individual operations to predetermined selection criteria. In contrast to a true optimization technique that can require computing up to N! combinations for N operations, the string or chain of efficient or “good enough” disc operations allows for relatively simpler computations.Type: GrantFiled: February 4, 2010Date of Patent: March 13, 2012Assignee: Seagate Technology LLCInventors: Jonathan W. Haines, Timothy R. Feldman
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Patent number: 8131923Abstract: An I/O Optimizer receives an I/O request specifying a plurality of disk blocks of the disk drive for access. A plurality of I/O sub-requests is determined from the I/O request, each I/O sub-request specifying a set of one or more adjacent disk blocks of the plurality of disk blocks along the same cylinder. A plurality of execution sequences for performing the plurality of I/O sub-requests is determined. For each of the plurality of execution sequences, a total estimated execution time for performing the I/O sub-requests according to the execution sequence is calculated. One of the plurality of execution sequences for performing the I/O sub-requests is selected based, at least in part, on the total estimated execution times for the plurality of execution sequences. A disk drive controller is instructed to perform the I/O sub-requests according to the selected execution sequence.Type: GrantFiled: May 19, 2011Date of Patent: March 6, 2012Assignee: Innternational Business Machines CorporationInventor: Frank E. Levine
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Patent number: 8127047Abstract: Proposed is technology for shortening the time required for analyzing and processing commands issued from multiple hosts and speeding up the processing. When a controller receives a command including random IO processing and the reception of commands is complete, it determines whether the valid extents prescribed in seek parameters attached to an LOC command overlap, and executes extent exclusive wait processing which causes access to the logical volume to enter a wait state or access processing to the logical volume based on the determination result. If the reception of commands is incomplete, the controller determines whether the access ranges (extents) designated in a DX command overlap, and executes extent exclusive wait processing or access processing to the logical volume based on the determination result.Type: GrantFiled: March 6, 2009Date of Patent: February 28, 2012Assignee: Hitachi, Ltd.Inventors: Ran Ogata, Akihiro Mori, Junichi Muto, Kazue Jindo
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Patent number: 8122157Abstract: Techniques are described herein for expanding the range of data targeted in I/O requests made by clients, so that the expanded range results in aligned I/O operations within the file system. Data that is included in the expanded range, but was not actually requested by the client, is trimmed off the data chunk returned by the file system, so that the client receives only the data required by the client. The blocks that contain the partially-read data are cached, so that they can be provided to the clients in response to subsequent I/O requests, without having to retrieve the blocks again from the file system. The I/O requests of multiple clients are handled by a read scheduler that uses a single global queue for all such requests. When appropriate, the read scheduler creates companionship relationships between the requests, and services the “companion” requests based on the data returned for the requests with which the companion requests are associated.Type: GrantFiled: August 7, 2009Date of Patent: February 21, 2012Assignee: Apple Inc.Inventor: Alexander B. Beaman
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Patent number: 8112554Abstract: A method of transmitting data on a data line between a central control device and a decentralized data processing device. During a normal operation of the system, the central control device periodically sends synchronization pulses to the at least one data processing device via the data line in order to request data packets, and the decentralized data processing device sends the data thereof to be transmitted, as data packets, to the central control device, following the synchronization pulse. The data line is embodied as a data bus. Each of the decentralized data processing devices is configured by the central control device before the first transmission of data packets to the central control device. In order to configure the system, a bi-directional communication is carried out between the central control device and the at least one decentralized data processing device.Type: GrantFiled: March 28, 2006Date of Patent: February 7, 2012Assignee: Continental Automotive GmbHInventor: Wolfgang Gottswinter
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Patent number: 8099523Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: GrantFiled: March 28, 2011Date of Patent: January 17, 2012Assignee: Intel CorporationInventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Patent number: 8099522Abstract: A method for controlling input and output of a virtualized computing platform is disclosed. The method can include creating a device interface definition, assigning an identifier to a paging device and configuring commands useable by a virtual input output server. The commands can be sent to the input output server and can be converted by the input output server into paging device commands. A hypervisor can assist in facilitating the communication configuration. Other embodiments are also disclosed.Type: GrantFiled: June 9, 2008Date of Patent: January 17, 2012Assignee: International Business Machines CorporationInventors: Gary D. Anderson, Carol B. Hernandez, Naresh Nayar, James A. Pafumi, Veena Patwari, Morgan J. Rosas
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Patent number: 8086765Abstract: Illustrated is a system and method for identifying a memory page that is accessible via a common physical address, the common physical address simultaneously accessed by a hypervisor remapping the physical address to a machine address, and the physical address used as part of a DMA operation generated by an I/O device that is programmed by a VM. It also includes transmitting data associated with the memory page as part of a memory disaggregation regime, the memory disaggregation regime to include an allocation of an additional memory page, on a remote memory device, to which the data will be written. It further includes updating a P2M translation table associated with the hypervisor, and an IOMMU translation table associated with the I/O device, to reflect a mapping from the physical address to a machine address associated with the remote memory device and used to identify the additional memory page.Type: GrantFiled: April 29, 2010Date of Patent: December 27, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Yoshio Turner, Jose Renato Santos, Jichuan Chang
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Patent number: 8082373Abstract: A universal serial bus controller pre-generates and stores a subset of USB commands in a memory, the pre-generated commands available for transmission to at least one USB peripheral device over universal serial bus, and transfers at least one command from the subset of pre-generated commands stored in the memory to the USB peripheral device over the universal serial bus. The universal serial bus controller may receive a response to the transferred command from the USB peripheral device over the universal serial bus, and send an acknowledgment packet to the USB peripheral device over the universal serial bus responsive to receiving the response from the USB peripheral device.Type: GrantFiled: September 19, 2007Date of Patent: December 20, 2011Assignee: Cypress Semiconductor CorporationInventors: David Wright, Steve Kolokowsky
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Patent number: 8074005Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.Type: GrantFiled: September 21, 2010Date of Patent: December 6, 2011Assignee: Renesas Electronics CorporationInventors: Hidemi Oyama, Masanobu Kawamura, Takuya Ikeguchi, Masanori Matsumoto, Hiroyuki Kawajiri
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Publication number: 20110296056Abstract: A plurality of devices are operated by storing at a device a first ID number received at a first port of the device and a second ID number received at a second port of the device. The device receives a data command through at least one of the first and second ports. The data command has a command ID number. The device executes the data command when at least one of the command ID number is equal to the first ID number when the data command is received at the first port and the command ID number is equal to the second ID number when the data command is received at the second port.Type: ApplicationFiled: January 24, 2011Publication date: December 1, 2011Applicant: MOSAID TECHNOLOGIES INCORPORATEDInventor: Byoung Jin Choi
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Patent number: 8069292Abstract: The present invention provides a method and apparatus for data processing and virtualization. The method and apparatus are configured to receive communications, separate a command communication from a data communication, parallel process the command communication and the data communication, generate at least one virtual command based on the command communication, and generate virtual data according to the at least one virtual command. The apparatus can comprise a parallel virtualization subsystem configured to separate data communications from command communications and to parallel process the command communications and the data communications, to generate virtual commands and to generate virtual data according to a virtual command, and a physical volume driver coupled with the parallel virtualization subsystem, wherein the physical volume driver receives the virtual data and configures the virtual data.Type: GrantFiled: October 3, 2007Date of Patent: November 29, 2011Assignee: Dynamic Network Factory, Inc.Inventors: Joseph S. Powell, Randall Brown, Stephen G. Finch
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Patent number: 8065445Abstract: A method of accessing a peripheral device can include determining whether the peripheral device is busy. The method can include selectively providing to a processor, according to whether the peripheral device is busy, either a driver or a program. The driver, when executed by the processor, causes the processor to offload the operation to the peripheral device. The program, when executed by the processor, causes the processor to perform the operation in lieu of the peripheral device performing the operation.Type: GrantFiled: March 18, 2010Date of Patent: November 22, 2011Assignee: Xilinx, Inc.Inventors: Jingzhao Ou, Chi Bun Chan
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Patent number: 8055807Abstract: A method, apparatus, and computer program product for processing a chain linked transport control channel program in an I/O processing system is provided. The method includes receiving a first command message at a control unit specifying a first predetermined sequence number for performing a first set of one or more commands as part of an I/O operation. The method further includes receiving a second command message specifying a second predetermined sequence number for performing a second set of one or more commands as part of the I/O operation. The method also includes comparing the sequence numbers to a next expected predetermined sequence number to determine an order of performing the commands. The method additionally includes executing the commands in the determined order to perform the I/O operation.Type: GrantFiled: July 31, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Daniel F. Casper, John R. Flanagan
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Patent number: 8055806Abstract: Embodiments of the present invention address deficiencies of the art in respect to threading model switching between asynchronous I/O and synchronous I/O models and provide a novel and non-obvious method, system and computer program product for autonomic threading model switching based upon I/O request types. In one embodiment, a method for autonomic threading model switching based upon I/O request types can be provided. The method can include selectably activating and de-activating a blocking I/O threading model according to a volume of received and completed blocking I/O requests.Type: GrantFiled: August 21, 2006Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: David B. Gilgen, William D. Wigger
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Patent number: 8055816Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.Type: GrantFiled: April 9, 2009Date of Patent: November 8, 2011Assignee: Micron Technology, Inc.Inventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao (Ray) Yang, Siamack Nemazie
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Publication number: 20110258347Abstract: A system, method and computer program product are provided for supporting Transactional Memory communications. In one embodiment, the system comprises a transactional memory host with a host transactional memory buffer, an endpoint device, a transactional memory buffer associated with the endpoint device, and a communication path connecting the endpoint device and host. Input/Output transactions associated with the endpoint device executed in transactional memory on the host are stored in both the host transactional memory buffer and the transactional memory buffer associated with the endpoint device. In an embodiment, the Transactional Memory system further comprises an intermediate device located on the communication path between the host and the endpoint device, and an intermediate transactional memory buffer associated with said intermediate devices.Type: ApplicationFiled: April 20, 2010Publication date: October 20, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jose E. Moreira, Patricia M. Sagmeister
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Patent number: 8024498Abstract: Disclosed is a computer implemented method and apparatus for queuing I/O requests to a pending queue. The I/O device driver sets a maximum ordered queue length for an I/O device driver coupled to a storage device then receives an I/O request from an application. The I/O device driver determines whether the pending queue is sorted and responds to a determination that the pending queue is sorted, determining if queued I/O requests exceed the maximum ordered queue length. Responding to a determination that the pending queue exceeds the maximum ordered queue length, the I/O device driver adds the I/O request based on a high pointer, and points the high pointer to the I/O request.Type: GrantFiled: December 15, 2008Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: James P. Allen, Nicholas S. Ham, John L. Neemidge, Stephen M. Tee
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Patent number: 8010661Abstract: In a system of networked devices such as printers managed by a computer connected to them by a network, a method is described for executing device discovery and device status update at independent time intervals using a SNMP broadcast method while eliminating thread safety risk. Device discovery and status update are executed as subroutines within a main routine and each subroutine has its own decrement counter. The entire routine is repeated one cycle every time unit. In each cycle, the decrement counters are evaluated. If a counter is a positive value, the corresponding subroutine is skipped and the counter is decremented by one. If a counter is zero, the corresponding subroutine is executed and its counter is reset to the user-specified time interval afterwards.Type: GrantFiled: December 18, 2008Date of Patent: August 30, 2011Assignee: Konica Minolta Laboratory U.S.A., Inc.Inventor: Naoki Komine
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Patent number: 8009310Abstract: A print control program for controlling execution of a print job, the print job being shared among a main printing apparatus and one or more sub-printing apparatus(es), the print control program allowing a computer to function as: a print requesting section for requesting the main printing apparatus and the sub-printing apparatus(es) to execute the print job in a cooperative manner; an apparatus information acquiring section for acquiring information relating to printing capabilities of the respective printing apparatuses as apparatus information, the apparatus information being stored in the main printing apparatus in advance; an instruction determining section for determining shares of the print job assigned to the respective apparatuses based upon the acquired apparatus information; and a controlling section for generating control instructions to be transmitted to the respective apparatuses.Type: GrantFiled: May 22, 2006Date of Patent: August 30, 2011Assignee: Sharp Kabushiki KaishaInventors: Yoshiaki Tanaka, Ryoji Murata
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Patent number: 8005998Abstract: A method for controlling power consumption of a Universal Serial Bus (USB) Mass Storage is provided. The USB Mass Storage is electrically connected to a USB port. The method includes: monitoring at least one Test Unit Ready (TUR) command from an operating system (OS) to the USB Mass Storage; and when it is detected that there is no other command from the OS to the USB Mass Storage for a predetermined time period, controlling the USB port to enter a suspend mode in order to save power supplied to the USB Mass Storage. An associated personal computer and a storage medium storing an associated USB Mass Storage driver for controlling power consumption of the USB Mass Storage are further provided, where the personal computer includes the storage medium. In particular, when the USB Mass Storage driver is executed by the personal computer, the personal computer operates according to the method.Type: GrantFiled: March 22, 2009Date of Patent: August 23, 2011Assignee: Silicon Motion Inc.Inventors: Jen-Hung Liao, Chang-Hao Chiang
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Patent number: 8001283Abstract: A system, apparatus and method for managing input/output requests in a multi-processor system is disclosed. An IO coherence unit includes an IO request handler, a variable size transaction table, and an IO response handler. The size of the transaction table varies according to the number of pending IO requests. The IO request handler stores information about pending IO requests in the transaction table to establish an order among related requests and to permit out-of-order handling of unrelated requests. The IO response handler tracks responses to the IO requests and updates the information in the transaction table. The IO coherence unit returns responses to requesting devices in compliance with device ordering requirements.Type: GrantFiled: March 12, 2008Date of Patent: August 16, 2011Assignee: MIPS Technologies, Inc.Inventors: William Lee, Thomas Benjamin Berg
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Patent number: 7996623Abstract: Method and apparatus for managing the storage of data in a cache memory by placing pending read requests for sequential data in a dedicated read ahead stream control (RASC) data structure, and further configured for dynamically switching both ways, in response to data stored in the RASC, between speculative non-requested read ahead data streaming to read behind stream locking on the read requests in the RASC.Type: GrantFiled: June 30, 2006Date of Patent: August 9, 2011Assignee: Seagate Technology LLCInventor: Michael D. Walker
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Patent number: 7991948Abstract: Methods, apparatus, and products are disclosed for optimizing execution of Input/Output (‘I/O’) requests for a disk drive in a computing system that include: receiving I/O requests specifying disk blocks of the disk drive for access, each disk block specified by a disk drive head, a cylinder, and a sector of the disk drive; determining I/O sub-requests from the I/O requests, each I/O sub-request specifying a set of adjacent disk blocks along the same cylinder; determining execution sequences for performing the I/O sub-requests; calculating, for each execution sequence, a total estimated execution time for performing the I/O sub-requests according to that execution sequence; selecting one of the execution sequences for performing the I/O sub-requests in dependence upon the total estimated execution times for the execution sequences; and instructing a disk drive controller to perform the I/O requests by performing the I/O sub-requests according to the selected execution sequence.Type: GrantFiled: January 30, 2008Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventor: Frank E. Levine
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Publication number: 20110179193Abstract: A peripheral interface for use with a control computer and a peripheral device. The peripheral interface has a controller receiving an input data stream from the control computer and delivering an output data stream to the peripheral device, the controller obtaining an instruction from the input data stream for a modification of the output data stream. Prior art devices transfer data streams for peripheral devices blockwise by means of DMA using peripheral interfaces. In conventional peripheral interfaces, a burdensome real-time operating system must be used on the control computer in order have a sufficiently short reaction time to bring about a continuous, uninterrupted data stream. The invention achieves the object using a non-real-time operating system.Type: ApplicationFiled: March 29, 2011Publication date: July 21, 2011Inventors: Andreas KUEHM, Nico Presser, Joerg Engel
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Patent number: 7984198Abstract: Input/output processing is facilitated by readily enabling access to information associated with input/output processing. This information includes status information and measurement data provided by a control unit executing input/output commands. The status and measurement data are provided in a status control block identified in a transport control word, which is further used to specify a location in memory that includes the input/output commands to be executed.Type: GrantFiled: February 3, 2009Date of Patent: July 19, 2011Assignee: International Business Machines CorporationInventors: Daniel F. Casper, John R. Flanagan
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Patent number: 7984252Abstract: A controller including an interface module and an index module. The interface module is configured to connect devices. The index module is configured to include, in a table stored in memory, an entry for each of the devices. Each entry includes an address field. The index module is configured to: receive a frame of data including an address of one of the devices; compare the address to the address fields associated with the entries in the table; in response to the address matching one of the address fields, access an index value identifying an entry of the table when the address matches one of the address fields; and in response to the address not matching one of the address fields, generate the index value. The index value is used to connect the device associated with the matching one of the address fields with the one of the devices.Type: GrantFiled: July 9, 2010Date of Patent: July 19, 2011Assignee: Marvell International Ltd.Inventors: Leon A. Krantz, Kha Nguyen, Michael J. North
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Publication number: 20110167176Abstract: A portable computing device (PCD) can be connected to multiple accessories concurrently in a daisy chain topology. with the PCD at a “front” end of the chain. At least one intermediary accessory (or relay) provides one port for connection to the PCD and another port for connection to another accessory, which can also be a relay. Each connected accessory can interact with the PCD to invoke functionality, receive or deliver content, etc. Concurrently, each relay accessory can also act as a relay for other accessories in the chain, directing signals from a downstream accessory toward the PCD and directing signals received from upstream toward a downstream accessory, thereby allowing downstream accessories to interact with the PCD. The presence of upstream intermediaries can be transparent to a downstream accessory.Type: ApplicationFiled: April 7, 2010Publication date: July 7, 2011Applicant: Apple Inc.Inventors: Jason J. Yew, Shailesh Rathi, Scott Krueger, Lawrence G. Bolton, John M. Ananny
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Patent number: 7966439Abstract: A system controller includes a memory controller and a host interface residing in different clock domains. There is a time delay between the time when the memory controller issues a read command to a memory and the data becoming present and available at the host interface. The memory controller generates an alarm message at or near the time that it issues the read command. The alarm message indicates to the host interface the time that the data is available for transfer to a host.Type: GrantFiled: November 24, 2004Date of Patent: June 21, 2011Assignee: Nvidia CorporationInventors: Sean J. Treichler, Brad W. Simeral, Roman Surgutchick, Anand Srinivasan, Dmitry Vyshetsky
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Patent number: 7962666Abstract: A transfer apparatus includes a connection status detection block, a storage status detection block, a no-operation status detection block, and a transfer block. The transfer block can automatically transfer candidate data to a memory device when a connected status is detected by the connection status block, the transfer candidate stored status is detected by the storage status detection block, and a no-operation status is detected by the no-operation status detection block.Type: GrantFiled: September 27, 2007Date of Patent: June 14, 2011Assignee: Sony CorporationInventors: Takayuki Kori, Yasuharu Seki, Rui Yamada, Tatsuya Konno
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Patent number: 7949806Abstract: A method to provide an operation to an information storage device is disclosed. The method supplies an information storage device and a protocol conversion device capable of receiving an operation in a first communication protocol comprising a variable attribute, and providing that operation to the information storage device in a second communication protocol, where that second communication protocol does not support the variable attribute. The method provides an operation to the protocol conversion device using said first communication protocol, and determines if the variable attribute is configured in that operation. If the method determines that the variable attribute is not configured in the operation, then the method provides the operation to the information storage device using the second communication protocol.Type: GrantFiled: November 18, 2004Date of Patent: May 24, 2011Assignee: International Business Machines CorporationInventors: Carl E. Jones, Robert A. Kubo, Gregg S. Lucas
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Patent number: 7949817Abstract: An adaptive bus profiler is described. In embodiment(s), data traffic that is communicated on an adaptive bus can be monitored, and projected data traffic that is scheduled for communication via the adaptive bus can be determined. An adaptive bus profile can be determined based on the data traffic and the projected data traffic. The data traffic that is communicated on the adaptive bus can be suspended to reconfigure a bus width of the adaptive bus based on the adaptive bus profile.Type: GrantFiled: July 29, 2008Date of Patent: May 24, 2011Assignee: Marvell International Ltd.Inventor: Premanand Sakarda
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Patent number: 7949794Abstract: A method and apparatus for enhancing /extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: GrantFiled: November 2, 2006Date of Patent: May 24, 2011Assignee: Intel CorporationInventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Fallk, Avi (Abraham) Mendelson, Ilan Pardo, Eran Tamari, Ellezer Weissmann, Doron Shamia
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Publication number: 20110119407Abstract: Disclosed is an improved approach for managing access to resources by workloads in a computing system. A much more accurate and useful technique is provided for determining disk utilization, and for using the calculated disk utilization to enforce workload constraints and limits. The technique may be used by any application that is attempting to share storage between multiple workloads can use the present solution, as well as any operating system and workload manager that need to manage workloads and resources.Type: ApplicationFiled: January 21, 2011Publication date: May 19, 2011Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Akshay D. SHAH, Sue K. LEE
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Publication number: 20110119406Abstract: A content providing method is provided involving an electronic apparatus and an external apparatus communicably connected with each other. A play command of the external apparatus for a particular content is received. at the electronic apparatus When the particular content is set to a content transferable to the external apparatus, the electronic apparatus sends the particular content to the external apparatus in response to the play command. Thus, a user can check only specified photos in the external apparatus.Type: ApplicationFiled: November 10, 2010Publication date: May 19, 2011Applicant: Samsung Electronics Co., Ltd.Inventors: Woo-Yong CHANG, Seung-dong Yu, Se-jun Park, Min-jeong Moon
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Patent number: 7945715Abstract: The system according to the present invention for data transfer between microcomputer devices contains a standard protocol controller, a generally known ethernet controller, for example, as a coupling device instead of the known multipart RAM. Instead of a parallel data connection, the microcomputer devices are coupled to one another via a standardized, serial data connection, for example, ethernet. Using functions of ethernet switches already known, a number of microcomputer devices in the system may be increased.Type: GrantFiled: April 9, 2003Date of Patent: May 17, 2011Assignee: Phoenix Contact GmbH & Co., KGInventors: Andreas Engel, Rainer Esch
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Apparatus and method to preserve one or more logical communication paths in a data processing system
Patent number: 7934026Abstract: A method to preserve a logical communication path in a data processing system, that includes a host computer, a storage controller that comprises a first logical control unit (“LCU”), and a logical communication path that is in communication with the host computer and the first LCU, comprising deleting the first LCU and setting a first status for same. The method then configures a second LCU, and establishes a second status for same, wherein the second LCU includes all or a portion of the first LCU, but is not the same as the first LCU. The deleting, setting, configuring, and establishing are performed while maintaining the logical communication path, which is in communication with the second LCU.Type: GrantFiled: September 17, 2008Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Juan Alonso Coronado, Roger Gregory Hathorn, Dinh Hai Le, Daniel Perkin, Aaron Eugene Taylor -
Patent number: 7930439Abstract: In a command output control apparatus, one of first and second storage areas that corresponds to the smaller number of subcommands is selected as a storage area subjected to division, according to a comparison result by a subcommand number comparison unit. From partial storage areas constituting the storage area subjected to the division, a partial storage area no smaller than a predetermined size is selected as a partial storage area subjected to the division, according to a comparison result by a size comparison unit. Subcommands for accessing partial storage areas obtained by dividing the partial storage area subjected to the division are generated by an access area division unit. A subcommand for accessing the partial storage area subjected to the division is replaced with the generated subcommands. Subcommands are alternately selected from first and second subcommand groups after the replacement and outputted to a memory.Type: GrantFiled: February 20, 2007Date of Patent: April 19, 2011Assignee: Panasonic CorporationInventors: Kazuya Furukawa, Masayuki Masumoto
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Patent number: 7924845Abstract: Message send and receive blocks are provided to emulation ICs and reconfigurable interconnect ICs of an emulation system to reduce the multiplexed transfer latency of critical emulation signals. Each of a corresponding pair of a message send block and a message receive block is provided with a signal state value inclusion schedule to control operation of the message send and receive blocks. The signal state inclusion schedule calls for some signals within a message to be sent more often than other signals within the message. In some embodiments a parity value is implemented as part the message and included in the signal state inclusion schedule.Type: GrantFiled: September 30, 2003Date of Patent: April 12, 2011Assignee: Mentor Graphics CorporationInventors: Philippe Diehl, Marc Vieillot, Cyril Quennesson, Gilles Laurent, Frederic Reblewski
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Patent number: 7925800Abstract: The present invention discloses a method of editing a multi-media playing schedule for a digital photo frame, a system and a computer readable storage medium thereof, which are characterized in that users can edit a multi-media playing schedule on the data processing apparatus when the digital photo frame is electrically connected to the data processing apparatus, and after editing of the multi-media playing schedule is finished, the multi-media playing schedule is transmitted to the digital photo frame and stored in the digital photo frame. Therefore, the problem of being unable to edit complicated multi-media playing schedules due to simple operation interface of digital photo frames can be solved.Type: GrantFiled: April 22, 2009Date of Patent: April 12, 2011Assignee: Elitegroup Computer Systems Co., Ltd.Inventor: Yao-Sen Cheng
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Publication number: 20110072164Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: ApplicationFiled: September 16, 2010Publication date: March 24, 2011Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi (Abraham) Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Patent number: 7908434Abstract: A cache managing unit creates a list of elements corresponding to each data block arranged based on a priority of writing data blocks to a magnetic disk apparatus, and when a group of elements corresponding to data blocks to be written to the same magnetic disk apparatus exists, provides a link connecting elements at both ends of the group. A write control unit searches, upon selecting a data block for writing, elements belonging to the list in descending order of priority, and if a link is set at an element corresponding to a data block to be written to a magnetic disk that cannot perform a writing, follows the link to search a subsequent element.Type: GrantFiled: October 31, 2006Date of Patent: March 15, 2011Assignee: Fujitsu LimitedInventors: Akihito Kobayashi, Katsuhiko Nagashima, Hidenori Yamada
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Patent number: 7908403Abstract: A computer program product, an apparatus, and a method for reducing reserved device access contention at a control unit in communication with a plurality of operating systems via one or more channels are provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method that includes receiving a command message at the control unit from a first operating system, including an I/O operation command for a device. A device busy indicator is received, indicating that a second operating system has reserved the device. The command message is queued on a device busy queue in response to the device busy indicator. The control unit monitors for a device end indicator. The device busy queue is serviced to perform the I/O operation command in response to the device end indicator.Type: GrantFiled: February 14, 2008Date of Patent: March 15, 2011Assignee: International Business Machines CorporationInventors: Mark P Bendyk, Daniel F Casper, John R. Flanagan, Clint A. Hardy, Roger G. Hathorn, Catherine C. Huang, Matthew L. Kalos, Louis W. Ricci, Gustav E. Sittmann, Harry M. Yudenfriend
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Patent number: 7904612Abstract: Improved administering of shared resources in a computer system. In a preferred embodiment, transaction throughput is improved and potential starvation eliminated by a ticket mechanism. The ticket mechanism provides a wait counter and a service counter. When a requested transaction fails, a wait counter is incremented and a wait value is sent to the requesting transaction source. As transactions are completed at the resource, the service counter is incremented and its value broadcast to transaction sources sharing that resource. When a source holds a wait count value that equals the service count value, the source can retry the transaction successfully.Type: GrantFiled: July 8, 2004Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventor: Peter Steven Lenk
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Publication number: 20110055431Abstract: The present disclosure relates to performing maintenance operations in a data system using configurable parameters. In one embodiment, a method in a data system is provided. The method includes receiving an indication of a data latency threshold and performing at least one maintenance operation in the data system based on the data latency threshold.Type: ApplicationFiled: August 26, 2009Publication date: March 3, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Christopher Ryan Fulkerson, Paul Francis Kusbel
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Patent number: 7899943Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: GrantFiled: October 31, 2007Date of Patent: March 1, 2011Assignee: Intel CorporationInventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi (Arraham) Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Patent number: 7895375Abstract: A Direct Memory Access (DMA) controller issues a read request to read data stored in a cache memory and sends a cache controller the read request via a bridge chip. When a response time monitored by a response time monitor exceeds a predetermined time, a status information notification unit obtains a measured value of a throughput from a throughput measuring unit and sends the cache controller a notification of both delay in the response time and the status information of a bus. A suppression instruction counting unit counts the number of suppression instructions, issued from the cache controller, to suppress a read request and sends a suppression control unit a notification of the number of suppression instructions. Then, the suppression control unit indicates a waiting time corresponding to the number of suppression instructions to the DMA controller to perform control to suppress issuance of a read request.Type: GrantFiled: November 13, 2007Date of Patent: February 22, 2011Assignee: Fujitsu LimitedInventors: Nina Tsukamoto, Sadayuki Ohyama