Abstract: An audio and video transmission system includes a multimedia device. The multimedia device includes a high-definition multimedia interface (HDMI) receiver, a first transfer circuit, and a first universal serial bus type C (USB-C) interface. The first transfer circuit is configured to transfer a first audio signal output by an audio channel pin of the HDMI receiver into a second audio signal in a universal serial bus (USB) interface format. The first USB-C interface is configured to transmit the second audio signal. The HDMI audio channel pin is an audio return channel (ARC) pin or an enhanced ARC pin.

Abstract: A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

Abstract: A microscope system having a plurality of microscope modules connected to one another for data transfer purposes. The microscope system includes a central clock generator, the clock signal of which is provided to all microscope modules. The microscope modules are configured to use the clock signal or a clock derived therefrom as an internal clock. Moreover, a corresponding method for operating such a microscope system is described.

Abstract: A cross-clock-domain processing circuit configured to implement data processing between asynchronous clock domains with a relatively low latency. The cross-clock-domain processing circuit includes a jitter filtering circuit and a synchronization circuit. The jitter filtering circuit is configured to: perform jitter filtering on a clock recovered from input data; adjust a jitter-filtered clock phase; and output a processed input data clock as an output data clock to the synchronization circuit. The synchronization circuit is configured to perform cross-clock-domain synchronization on the input data based on the input data clock and the output data clock.

Abstract: Apparatuses and methods for configuration and operation of data communication connectors supporting connectivity to various physical interfaces are provided.

Abstract: A data transmission system includes a host, a universal serial bus (USB) interface adaptor, a first-in first-out (FIFO) interface adaptor, a plurality of functional circuits, and a bus bridge circuit. The host accesses data according to the communications protocols of USB. The USB interface adaptor accesses data through a first port according to the communications protocols of USB, and accesses data through a second port according to the communications protocols of FIFO. The FIFO interface adaptor accesses data through a third port coupled to the second port according to the communications protocols of FIFO, and accesses data through a fourth port according to the communications protocols of a specific type of bus. The bus bridge circuit transmits the data received from the fourth port to a functional circuit according to the communications protocols of the specific type of bus.

Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.

Abstract: A serial general purpose input/output system includes a transmitter, a cable, a receiver and a verification unit. The transmitter includes an encoder to perform cyclic redundancy check coding on a data to generate a cyclic redundancy check code for verifying the accuracy of the data, and a first serial general purpose input/output connector coupled to the encoder to transmit the data and the cyclic redundancy check code. The receiver includes a second serial general purpose input/output connector coupled to the first serial general purpose input/output connector by the serial general purpose input/output cable to receive the data and the cyclic redundancy check code from the first serial general purpose input/output connector.

Abstract: Disclosed herein is circuitry that extends the charge-steering (CS) logic library with a 2:1 CS-multiplexor (MUX) cell that can be used in a tree fashion to compose a 2N:1 CS-MUX. Also presented is the integration of 2N:1 CS-MUX with conventional CMOS signals at a parallel input, and a current-mode driver at the serialized output. Also presented are a non-return-to-zero (NRZ) to RZ serializing transmitter, a charge-steering multiplexor (CSM) pre-driver, and a CSM transmitter.

Abstract: System and method for convergence analysis. One or more state variables of a first program may be determined based on dependencies of variables in a first program. A second program corresponding to the first program is created based on the state variables and their dependencies, and executed multiple times. Each execution may include recording values of the state variables, determining an execution count, comparing the values to corresponding values from previous executions of the second program, and terminating the executing in response to the values matching corresponding values from at least one previous execution of the second program. A convergence property for the first program is determined based on the execution count, and indicating a number of executions of the first program required to generate all possible values of the one or more variables. The convergence property is stored, and may be useable to optimize the first program.

Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.

Abstract: The present invention is applicable to a semiconductor device having a plurality of chips being stacked with a TSV structure in which adjacent ones of the chips are connected to each other via a plurality of through electrodes. Each of the chips includes a plurality of TSV array portions provided so as to correspond to a plurality of channels. The TSV array portions include a TSV array portion that contributes to an input and an output depending upon the number of the chips being stacked, and a pass-through TSV array portion that is not connected to an input/output circuit.

Abstract: A control method comprising: a first step of detecting, by the server module, a failure in the first interface; a second step of executing, by the server module, given recovery processing when a failure is detected in the first interface; a third step of using, by the coupling module, the first end point to detect a failure in the first interface and output a failure notification; a fourth step of converting, by the coupling module, the failure notification into a notification of disconnection of the first interface, and transmitting the disconnection notification generated by the conversion to the storage module from the second end point; and a fifth step of disengaging, by the storage module, coupling to the server module when the disconnection notification is received from the coupling module.

Abstract: On the basis of single-ended signals based on logic levels, and of differential, in particular common-mode-based, signals, a circuit arrangement and a corresponding method are proposed, in which it is possible to further reduce the size of tools, which are associated with said type of circuit arrangement and said type of method.

Abstract: On the basis of single-ended signals based on logic levels, and of differential, in particular common-mode-based, signals, a circuit arrangement and a corresponding method are proposed, in which a serialized signal transmission is always performed in an error-free and stable manner.

Abstract: A clock control circuit for a parallel in, serial out (PISO) shift register helps save power. The clock control circuit selectively clocks the shift register as it converts a parallel input to a serial output. For example, the clock control circuit may provide clock signals to the flip flops (or other buffers) in the shift register that will receive data elements provided with the parallel input. However, the clock control circuit withholds clock signals from flip flops that will not receive data elements provided with the parallel input, or that have already been received by a particular flip flop. As the parallel loaded input elements propagate serially through the shift register, on each clock cycle an additional memory no longer needs to be clocked. The memory no longer needs to be clocked because that memory has already propagated its loaded input element to the following memory, and no further element provided in the N element parallel loaded data is incoming.

Abstract: On the basis of single-ended signals based on logic levels, and of differential, in particular common-mode-based, signals, a transmission arrangement and a corresponding method are proposed, in which a serialized signal transmission is always performed in an error-free and stable manner.

Abstract: According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.

Abstract: The present invention is applicable to a semiconductor device having a plurality of chips being stacked with a TSV structure in which adjacent ones of the chips are connected to each other via a plurality of through electrodes. Each of the chips includes a plurality of TSV array portions provided so as to correspond to a plurality of channels. The TSV array portions include a TSV array portion that contributes to an input and an output depending upon the number of the chips being stacked, and a pass-through TSV array portion that is not connected to an input/output circuit.

Abstract: A shift register structure is presented that can be used in variable rate parallel to serial data conversions. In an N to 1 conversion, data is received from an (N×m)-wide parallel data bus in an N by m wide latch. This data can include m-bit wide units of data are to be ignore and the parallel bus clock will be of variable rate due to this data to be skipped, which is not to be put out on to the serial bus. The data is transferred from the latch to an N unit shift register, each unit holding m-bits. Multiplexing circuitry is included so that at least on unit of the shift can receive data from more than one latch location, thereby reducing the number of units in the shift register that may need to be skipped when the data is transferred out on to an m-bit wide serial bus with the bits to be ignored absent.

Abstract: A serial transmission device includes a transmitting unit that transmits data, a receiving unit that receives the data, and a plurality of serial transmission paths that connect the transmitting unit with the receiving unit and are used to transmit data. The receiving unit includes an inter-lane skew information generation unit that generates inter-lane skew information about skew of each of the serial transmission paths and transmits the generated inter-lane skew information to the transmitting unit. The transmitting unit includes a data conversion rule generation unit that generates a conversion rule used to determine distribution of the data to each of the serial transmission paths based on the inter-lane skew information.

Abstract: The present disclosure provides a CPU interconnect device, the CPU interconnect device connects with a first CPU, which includes a quick path interconnect QPI interface and a serial deserial SerDes interface, the quick path interconnect QPI interface receives serial QPI data sent from a CPU, converts the received serial QPI data into a parallel QPI data, and outputs the parallel QPI data to the serial deserial SerDes interface; the serial deserial SerDes interface converts the parallel QPI data output by the QPI interface into a high-speed serial SerDes data and then send the high-speed serial SerDes data to another CPU interconnect device connected with another CPU. The defects of poor scalability, long data transmission delay, and a high cost of an existing interconnect system among CPUs can be solved.

Abstract: A plug connector with external contacts is provided. The connector has one pair of contacts for transmitting data and one pair of contacts for receiving data. All data transmitted and received using the plug connector is serialized/de-serialized to enable data transmission at a very high rate. A corresponding receptacle connector has configurable contacts that are configured based on the orientation of the plug connector with respect to the receptacle connector. The receptacle connector may be included in a host device and has associated circuitry to detect orientation of the plug connector and to configure the contacts of the receptacle connector.

Abstract: A data processing unit includes a main controller configured to receive data requirement information from a host and to generate processing information based on the data requirement information; a pre-processing unit configured to pre-process n types of data output from the main controller according to the processing information and to generate n types of pre-processed data where n is an integer equal to or greater than 2; and a pre-processed data storing unit configured to store the n types of pre-processed data and to output the n types of pre-processed data in an output order determined based on the processing information, wherein the processing information includes information about at least one of type, format, order, size and transmission mode of the n types of pre-processed data.

Abstract: An information memory system in which data received is divided into pieces of data, which are stored in memories in parallel, includes controller configured to storing a number of the divided pieces of data and monitoring a read request and a buffer full notice, in a case where the number of read requests does not reach the number of valid memory units and the buffer full notice continues in all buffers except for one buffer which does not output the read request, performing a read control corresponding to the buffers which output the buffer full notice, and performing control of the integration of a piece of data reconstructed, after being read from the memory unit corresponding to the buffer which does not output the read request and the pieces of data read from the memory units corresponding to the buffers which output the buffer full notice.

Abstract: An input device with parallel multi-tasking capabilities is disclosed. The input device comprises a controller, a data assigning unit and a plurality of first communication end-points. The input device declares the plurality of first communication end-points as virtual peripheral devices with equivalent performance. When the input device is electrically connected to a host for data communication, the virtual peripheral devices with equivalent performance and a plurality of second communication end-points are respectively establish communication link of point-to-point correspondingly, so that the plurality of second communication end-points receive a plurality of operation slave data for reducing data communication time.

Abstract: A logic device for communicating with a memory package with a first protocol, communicating with a memory controller with a second protocol, and for performing a protocol conversion between the first and the second protocol.

Abstract: The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side.

Abstract: An integrated circuit (IC) that enables a fast parallel-to-serial memory data transfer is described. The IC includes a first input output (IO) interface operable to receive a plurality of data in parallel from a memory device, wherein the plurality of data is a binary sequence. The IC also includes a controller receiving the plurality of data from the first IO interface, wherein the controller is operable to generate a compressed data by compressing the plurality of data, wherein a portion of the compressed data provides information on a significant portion of the plurality of data. And the IC also includes a second IO interface receives the compressed data from the controller and serially shifts the compressed data out of the IC.

Abstract: A semiconductor memory apparatus includes a synchronized signal generation circuit, a serial-to-parallel data conversion unit and a data storage region. The synchronized signal generation unit outputs one of a data input/output strobe signal and a delay locked clock signal as synchronized signals in response to a control signal in a write operation. The serial-to-parallel data conversion unit converts serial data into parallel data in response to the synchronized signals. The parallel data is stored in the data storage region.

Abstract: Various techniques are provided to support efficient data transfers over serial data streams. In one example, a serial device may be used to efficiently transfer data between a host device and the serial device over a data stream of a serial interface. A data stream value identifying the data stream may be stored in a register indexed by a tag associated with a command received from the host device. The command may be passed to a storage media device, wherein the passing is controlled by a processor of the serial device. The tag may be extracted from an address value received from the storage media device in response to execution of the command by the storage media device. The data stream value may be retrieved from the register using the extracted tag as an index without requiring an interrupt to the processor to determine the data stream value.

Abstract: A brake control device, wherein control is executed that keeps braking force generated to wheels of a vehicle to a predetermined value or more when detected operating pressure has reached a control determination value, the detected operating pressure being operating pressure input to a brake operating member in a state that the vehicle stops and applied to a working fluid in response to operation force increased using negative pressure generated in an internal combustion engine of the vehicle and being the operating pressure detected by an operating pressure detecting unit, and when the detected operating pressure has exceeded dead point operating pressure which is the operating pressure at a negative pressure dead point at which an effect of increase of the operation force using the negative pressure disappears, at least any one of the detected operating pressure and the control determination value is corrected and the control is executed based on the corrected value.

Abstract: A method for converting serial data having a certain word size to parallel data, comprises the steps of: generating segments from the serial data using one or more serially-connected first stages, wherein the segments have a predetermined bit size; storing each of the segments into a selectively turned-on flip-flop of a final stage, wherein the final stage is serially connected to the first stages, wherein the final stage has a plurality of flip-flops and each of the flip-flops has a bit size equaling to the bit size of the segments; and outputting the stored segments in parallel from the final stage.

Abstract: In one embodiment, a monolithic integrated circuit includes a first UART, a second UART, and a multiplexer. The first UART has a parallel IO interface to couple to a host system to transceive parallel data and a serial IO interface. The second UART has a parallel IO interface and a serial IO interface coupled to the serial IO interface of the first UART. The first and second UARTs convert parallel data into serial data and serial data into parallel data. The multiplexer has an output coupled to the serial input of the first UART, a first input coupled to the serial output of the second UART, a second input coupled to a serial input of a serial communication port, and a select input coupled to a control signal selectively coupling serial interfaces of first and second UARTs together for remote terminal services at a remote computer system over a network.

Abstract: This document discusses, among other things, a system and method for serializing a video signal and providing non-packet-based serialized video information to a physical Universal Serial Bus (USB) interface and, in certain examples, receiving the non-packet-based serialized video information from the physical USB interface, deserializing the received non-packet-based serialized video information, and providing a high definition output signal to a video port (e.g., an HD video port, such as HDMI, DisplayPort, etc.) using the deserialized video information.

Abstract: To address the need for efficient and reliable testing of integrated devices, system on chips, and computers, deterministic behavior for an interface is accomplished by fixing variation in latency associated with receiver and transmitter data stream. The interface may be a serial interface that is PCIe compliant and corrects latency variations in the receiver that consequently results in deterministic transmit data. Consequently, the data received and/or transmitted is predictable with respect to time and facilitates testing and validation of the devices and logic associated with the interface.

Abstract: A connector assembly includes a first connector, a second connector, a first controller, an inter-integrated circuit (I2C), and a second controller. The first connector is electrically connected between a first element and the first controller. The second connector is electrically connected between a second element and the second controller. The I2C is electrically connected between the first controller and the second controller. The first connector receives and outputs a number of parallel signals from the first element. The first controller converts the parallel signals into two serial signals. The I2C transmits the two serial signals to the second controller. The second controller converts the two serial signals into a number of parallel signals.

Abstract: An electronic measuring device includes a detection channel module, a sampling module, a control unit, a data path selector and a memory device. A user will be able to selectively enable the desired detection channels and store only data collected from enabled channels. The data collected from the detection channels are in serial data form. The device utilizes a serial-parallel shifter in its sampling module to convert the serial data to parallel data bytes. Two indicators in the storage unit of the memory device allow users to effectively store the parallel data bytes in designated locations. The innovative data conversion and storage methods of this invention will significantly conserve memory space that otherwise will be occupied by data from the disabled channels and allow accurate and efficient reading of the stored data.

Abstract: Embodiments of the invention describe an apparatus, system and method for executing self-correction logic for serial-to-parallel data converters. Embodiments of the invention receive one of a plurality of serial data streams from a peripheral device, each of the serial data streams having one or more bits. In response to detecting that a shift register chain includes a register select value, embodiments of the invention may store the received serial data stream in one of a plurality of data registers, wherein the one data register is selected based, at least in part, on a position of the register select value in the shift register chain. In response to detecting the shift register chain does contain the register select value, embodiments of the invention may insert the register select value at a register of the shift register chain.

Abstract: An SVID data test system is applied on a test device and a display device, and the test device is electrically connected to a tested device via an SVID interface, and the display device via a serial interface. The system receives SVID signals, analyzes the SVID signals to obtain nine bit real signals, and performs parallel encoding on the nine bit real signals to obtain nine bit parallel signals. The system further converts the nine bit parallel signals to nine bit serial signals, transmits the serial signals in sequence to the display device, and parses the nine bit serial signals to obtain a packet in hexadecimal and controls the display device to display the packet in response to the display command.

Abstract: A system, apparatus, and method for testing blocks of a system on a chip (SOC) are described herein. An SOC, in accordance with various embodiments, may include a serial communication interface configured to multiplex, serialize, and/or parallelize signals streams from selected blocks of the SOC to an off-chip test unit through an off-chip serial communication interface. Other embodiments may be described and claimed.

Abstract: An apparatus consisting of a digital communication channel comprised of a multiplicity of lanes where data is striped across the lanes in a predefined sequence. Each lane has the ability to be powered down or powered up in response to the amount of data being held in a transmit buffer at one end of the communication channel. The method consists of monitoring the amount of data being held in the transmit buffer; making the decision of how many lanes are required based on the amount of data; sending signals to cause the required number of lanes to be powered down or powered up; and performing the required power down or power up action at the particular transmitter and receiver.

Abstract: Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins.

Abstract: A data transfer circuit includes a serial-to-parallel converter configured to convert multi-bit data inputted in series into parallel data by controlling the number of bits of the parallel data and a conversion timing based on an operation mode, and a data transmission unit configured to transfer the parallel data to a first data path or a second data path based on the operation mode.

Abstract: Embodiments of the present invention provide an approach for dynamic random access memory (DRAM)/SSD-based memory to improve memory usage. Specifically, embodiments of the present invention provide a field programmable gate array (FPGA) (SSD controller) that comprises a PCI-express interface for receiving and converting serial data to 64 bit data; a data/bit converter coupled to the interface for converting the 64 bit data to 128 bit data; and a memory controller coupled to the data converter for receiving and storing the 128 bit data in a set of DRAM units coupled to the memory controller.

Abstract: Apparatus and methods are provided for alleviating processing requirements of a central computer in a vessel. Each apparatus is placed in close proximity to one or more pieces of electronic equipment implementing a legacy interface. The apparatus processes data to and from the electronic equipment, including converting data to formats consistent with the formats used by the intended recipient.

Abstract: The invention concerns a device for transmitting data between a serial data bus and working modules, wherein the data bus is connected to a bus node in a bus module having at least two serial communication ports which are connected to ports of a hub connected to or integrated with the bus node, wherein the communication ports are designed for the connection and for the power supply of the working modules and wherein at least one of the working modules is designed as an actuator and/or I/O module comprising a serial-to-parallel converter for the parallel connection of actuators and/or I/O interfaces provided on or connected to the respective working module.

Abstract: A control unit includes at least one computing device and at least one separate peripheral module which is connected to the computing device via a serial multiwire bus, the peripheral module including at least one output stage for transferring serial data to means outside of the control unit. In order to keep the number of pins required on a peripheral module to a minimum, thereby reducing costs for the entire control unit, the peripheral module has an asynchronous single-wire interface between one interface for the serial multiwire bus and the output stage. The asynchronous single-wire interface is preferably a UART (universal asynchronous receiver/transmitter) interface. The serial multiwire bus is preferably a microsecond bus.

Abstract: A KVM switch includes: a first input portion and a second input portion that inputs a plurality of video signals from the first and the second information processing apparatus, respectively; a converting portion that converts the video signals input from the first or second input portion into a plurality of pieces of image data which are capable of being displayed on a remote terminal; a transmitting and receiving portion that transmits the pieces of converted image data to the remote terminal, and receives various requests from the remote terminal; and a switching portion that switches the video signals input from the first input portion to the video signals input from the second input portion when the transmitting and receiving portion receives a switching request for switching from a first information processing apparatus to a second information processing apparatus from the remote terminal.

Abstract: The present disclosure describes techniques and apparatuses for multiport memory architecture. In some aspects serial data is received from a data port and converted to n-bit-wide words of data. The n-bit-wide words of data are then buffered as a k-word-long block of parallel data into a line of a multiline buffer as a block of k*n bits of data. The block of k*n bits of data is then transmitted to a multiport memory via a write bus effective to write the block of k*n bits of data to the multiport memory.