Programmable Read Only Memory (prom, Eeprom, Etc.) Patents (Class 711/103)
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Patent number: 12366996Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.Type: GrantFiled: April 8, 2024Date of Patent: July 22, 2025Inventors: Victor Y. Tsai, Danilo Caraccio, Daniele Balluchi, Neal A. Galbo, Robert Warren
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Patent number: 12366962Abstract: Mechanisms for improving read command processing times in a solid-state drive (SSD) are provided, the mechanisms comprising: determining a workload type of an SSD; in response to determining that the workload type is a pure read workload type: determining at least one command size into which an original background write is to be split-up using at least one hardware processor; and splitting-up the background write into a plurality of split background writes, each having one of the determined at least one command size. In some embodiments, the at least one command size accounts for a page of the physical medium of the SSD. In some embodiments, the at least one command size includes at least two different sizes. In some embodiments, the mechanisms further comprise combining two or more split background writes. In some embodiments, the original background write is split-up before being placed in a channel queue.Type: GrantFiled: December 28, 2022Date of Patent: July 22, 2025Assignee: SK hynix NAND Product Solutions CorporationInventors: Mark Anthony Sumabat Golez, Henry Chu, Darshan Mallapur Vishwanath, Sarvesh Varakabe Gangadhar, David J. Pelster
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Patent number: 12366987Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a data merge operation; selecting a plurality of first-type physical units and a second-type physical unit from a rewritable non-volatile memory module to execute the data merge operation, wherein a data capacity of each first-type physical unit is less than a data capacity of each second-type physical unit; during a first execution period of the data merge operation, copying first data from a first physical unit in a stable state among the first-type physical units to the second-type physical unit; and during the first execution period, storing second data from a host system to a second physical unit not in the stable state among the first-type physical units.Type: GrantFiled: June 12, 2023Date of Patent: July 22, 2025Assignee: PHISON ELECTRONICS CORP.Inventor: Yen Chen Yeh
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Patent number: 12360673Abstract: A multi-tier memory comprises a block of memory with a plurality of sub-blocks (e.g., three sub-blocks). A garbage collection operation that chooses a source block based on a valid fragment count may not be suitable in multi-tier memories where sub-blocks have a dependency on one another (e.g., for an erase or program operation). The embodiments presented herein provide various garbage collection techniques that can be used in this situation. The techniques described herein can take in to account the valid fragment count of various sub-block groupings when deciding where to perform a garbage collection operation.Type: GrantFiled: May 29, 2024Date of Patent: July 15, 2025Assignee: Sandisk Technologies, Inc.Inventors: Manoj M. Shenoy, Ramanathan Muthiah
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Patent number: 12360669Abstract: The size of page map memory in a NAND flash device used to store page related information is decreased by embedding page type in a row address. The row address is received by the NAND flash device from the host on the data bus in a six-cycle sequence. The received row address is used to decode a physical page address received during the row address cycle to obtain a word line and a block segment number for a block segment in the word line in the NAND flash array. A same block segment number is used for each page type in the block segment.Type: GrantFiled: February 9, 2023Date of Patent: July 15, 2025Assignee: Intel NDTM US LLCInventors: Aliasgar S. Madraswala, Shanmathi Mookiah, Pratyush Chandrapati, Naveen Prabhu Vittal Prabhu
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Patent number: 12360705Abstract: Disclosed is a storage device, which includes a nonvolatile memory device, and a controller that controls the nonvolatile memory device. In response to a first command, a barrier command, and a second command being received from an external host device, the controller supports an order guarantee between the first command and the second command. Each of the first command and the second command is selected from two or more different commands. In response to a request from the external host device, the controller circuitry is configured to provide the external host device with a device descriptor associated with the ordering.Type: GrantFiled: February 26, 2024Date of Patent: July 15, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Jimin Ryu, Jongju Kim, Jeong-Woo Park, Byung-Ki Lee
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Patent number: 12360889Abstract: A method and controller for operating a memory system in communication with a host. The method and controller logically arrange a sequence of reclaim sub-groups within a memory device. The method and controller process the reclaim sub-groups according to the sequence to control the memory device to perform garbage collection on the reclaim sub-groups in the memory device. In the sequence, the reclaim sub-groups are processed during the garbage collection such that at least one re-ordered data sequence in the sequence of the reclaim sub-groups being processed has re-ordered valid data that is not clumped.Type: GrantFiled: March 2, 2023Date of Patent: July 15, 2025Assignee: SK hynix NAND Product Solutions Corp.Inventors: David J. Pelster, Mark Golez, Daniel R. McLeran, Nathan Koch, Paul Ruby
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Patent number: 12353961Abstract: A method includes acquiring statistic data of a storage load, inputting the statistic data, and determining read/write request tracking data of the storage load. The acquired statistic data of a storage load may be generated by an application in a predetermined time period. The determined read/write request tracking data of the storage load may be during the predetermined time period through the pre-trained machine learning model. The statistic data may include global statistic information corresponding to read/write requests generated by the application in a predetermined time period. The read/write request tracking data may be information of each read/write request generated by the application in a predetermined time period.Type: GrantFiled: December 1, 2020Date of Patent: July 8, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Wei Xia
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Patent number: 12346301Abstract: A computer-implemented method for performing a database query within a database, that contains logical data records which are physically stored in the form of field-specific data value lists, includes receiving instructions to change data values; storing the instructions in an append-only data structure without making the changes to the field-specific data value lists, wherein each entry in the append-only data structure-referred to here as an AOD entry-contains at least those of the field identifier-data value pairs of one of the data records that are to be changed according to one of the change instructions; for each of the data records for which the database receives instructions, storing the address of the most recent of the stored AOD entries specifying a change to that data record, linked to the data record ID of that data record, in an address allocation table; and performing a database query.Type: GrantFiled: April 22, 2022Date of Patent: July 1, 2025Assignee: Cortex Innovations GmbhInventor: Peter Palm
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Patent number: 12333177Abstract: Devices and techniques are disclosed wherein a data storage device (DSD) generates ranking information corresponding to user data stored at a non-volatile memory of the DSD. The ranking information can be used by the DSD to form a frequently used files list, which can be read by a host system upon initialization with the host system and displayed to a user at the host system.Type: GrantFiled: July 28, 2023Date of Patent: June 17, 2025Assignee: Sandisk Technologies, Inc.Inventors: Rohith Radhakrishnan, Alvin Gomez
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Patent number: 12333154Abstract: A processing device in a memory sub-system performs a first media scan operation with respect to a plurality of memory pages addressable by the ordinary wordline, wherein each page of the plurality of memory pages is contained by a respective management unit, and responsive to determining that a value of a data state metric of a memory page of the plurality of memory page addressable by the ordinary wordline satisfies a specified condition, performs a first media management operation with respect to a management unit containing the memory page.Type: GrantFiled: July 6, 2023Date of Patent: June 17, 2025Assignee: Micron Technology, Inc.Inventors: Tingjun Xie, Yang Liu, Jiangli Zhu, Juane Li, Aaron Lee
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Patent number: 12333168Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: in a first operation mode, setting a physical management unit to cross N physical regions in a rewritable non-volatile memory module; in a second operation mode, setting the physical management unit to cross M physical regions in the rewritable non-volatile memory module, wherein N is greater than M; and accessing the rewritable non-volatile memory module based on the physical management unit.Type: GrantFiled: February 1, 2023Date of Patent: June 17, 2025Assignee: PHISON ELECTRONICS CORP.Inventor: Chih-Kang Yeh
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Patent number: 12333179Abstract: A system includes a first compute express link (CXL) storage device, a second CXL storage device, a first CXL memory device, and a CXL switch connected to the first CXL storage device, the second CXL storage device and the first CXL memory device through a CXL interface, the CXL switch configured to arbitrate communications between the first CXL storage device and the second CXL storage device, and the first CXL memory device. The first CXL memory device is configured to store first map data of the first CXL storage device and second map data of the second CXL storage device, the first CXL storage device is configured to exchange at least a portion of the first map data with the first CXL memory device through the CXL switch, and the second CXL storage device is configured to exchange at least a portion of the second map data with the first CXL memory device through the CXL switch.Type: GrantFiled: April 4, 2023Date of Patent: June 17, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyunghan Lee, Jae-Gon Lee, Chon Yong Lee
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Patent number: 12327185Abstract: An operation method of an artificial neural network is provided. The operation method includes: dividing input information into a plurality of sub-input information, and expanding kernel information to generate expanded kernel information; performing a Fast Fourier Transform (FFT) on the sub-input information and the expanded kernel information to respectively generate a plurality of frequency domain sub-input information and frequency domain expanded kernel information; respectively performing a multiplying operation on the frequency domain expanded kernel information and the frequency domain sub-input information to respectively generate a plurality of sub-feature maps; and performing an inverse FFT on the sub-feature maps to provide a plurality of converted sub-feature maps for executing a feature extraction operation of the artificial neural network.Type: GrantFiled: November 12, 2020Date of Patent: June 10, 2025Assignee: MACRONIX International Co., Ltd.Inventors: Wei-Chen Wang, Shu-Yin Ho, Chien-Chung Ho, Yuan-Hao Chang
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Patent number: 12315582Abstract: A memory device configured to select a page having a probability that uncorrectable error correction codes (UECC) will occur by comparing a reference current with a sensing current, and configured to perform a read reclaim operation or an additional pulse applying operation on the corresponding page according to the comparison.Type: GrantFiled: October 21, 2021Date of Patent: May 27, 2025Assignee: SK hynix Inc.Inventors: Min Ho Her, Seung Il Kim, Jae Min Lee, Myoung Kyun Kim, Won Gyu Park
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Patent number: 12314172Abstract: A memory controller includes a block ratio calculator configured to calculate a ratio of free blocks among memory blocks for storing data; a policy selector configured to select, based on the calculated ratio of free blocks, any one garbage collection policy of a first garbage collection policy of specifying priorities to be used to select a victim block depending on attributes of the data, and a second garbage collection policy of specifying the priorities to be used to select the victim block regardless of the attributes of the data; and a garbage collection performing component configured to perform a garbage collection operation on at least one memory block of the memory blocks according to the garbage collection policy selected by the policy selector.Type: GrantFiled: September 18, 2023Date of Patent: May 27, 2025Assignee: SK hynix Inc.Inventor: Hung Yung Cho
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Patent number: 12314565Abstract: In an embodiment of the disclosed technology, a host device may control an operation of writing data to a plurality of types of memory cells included in a memory, through booster logic units respectively corresponding to the plurality of types of memory cells, and a timing thereof. It is possible to prevent performance of a device from degrading due to differences in characteristics of operations in which data are written to the plurality of types of memory cells, and improve performance and efficiency of an operation of writing data to a plurality of memory cells.Type: GrantFiled: October 24, 2023Date of Patent: May 27, 2025Assignee: SK hynix Inc.Inventor: Hyeong Ju Na
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Patent number: 12314171Abstract: A computer-implemented method, according to one approach, includes: monitoring performance in NVRAM having a plurality of memory blocks. Moreover, a change in the flow rate of I/O requests received at the NVRAM is identified as a result of the monitoring. In response to identifying the change is an increase in the flow rate of received I/O requests, the percentage of invalid pages in a given block of NVRAM that triggers garbage collection to be performed on the given block is increased. However, in response to identifying the change is a decrease in the flow rate of received I/O requests, the percentage of invalid pages in a given block that triggers garbage collection to be performed on the given block is decreased.Type: GrantFiled: October 31, 2023Date of Patent: May 27, 2025Assignee: International Business Machines CorporationInventors: Micah Robison, Matthew G. Borlick, Beth Ann Peterson, Lokesh Mohan Gupta
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Patent number: 12292827Abstract: A storage device, including a nonvolatile memory device comprising a plurality of memory cells; and a controller configured to: allocate a plurality of zones to a storage space of the nonvolatile memory device based on a request received from an external host device, fixedly and sequentially manage logical addresses of data written in the plurality of zones, generate a first page map table corresponding to a first zone based on performing the write operation on the first zone, the first page map table comprising a logical address and a physical address of the first zone, based on the first zone being full, activate a read service, which is based on the zone map table, and based on the read service being activated, process read requests for the first zone from the external host device using the zone map table.Type: GrantFiled: August 25, 2023Date of Patent: May 6, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seunghyun Choi, Keunsan Park, Heetak Shin, Junyeong Han, Gyeongmin Kim, Joon-Whan Bae, Jooyoung Hwang
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Patent number: 12293101Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.Type: GrantFiled: January 25, 2024Date of Patent: May 6, 2025Assignee: Micron Technology, Inc.Inventors: Paolo Papa, Luigi Esposito, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara, Carminantonio Manganelli, Salvatore Del Prete
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Patent number: 12287969Abstract: Systems and methods for dynamic throttling of input/output queues in data storage device arrays are described. Data storage devices are connected through the slots and corresponding lanes of a storage interface switch. A storage controller uses a delay inserted between host submission queues and backend submission queues to manage the priority of host storage commands using slot groups.Type: GrantFiled: August 3, 2023Date of Patent: April 29, 2025Assignee: Western Digital Technologies, Inc.Inventors: Rahul Gandhi Dhatchinamoorthy, Kumar Ranjan, Senthil Kumar Veluswamy
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Patent number: 12282404Abstract: Embodiments provide a storage system, including: a basis chip and memory chips, where the memory chip includes memory cells, the storage system has channels, each of the channels includes a partial number of memory cells in all the memory chips, a partial region of each of the channels corresponds to one memory chip, and each channel is electrically connected to the basis chip; and a temperature processing circuit configured to obtain first temperature codes corresponding to the memory chips, to obtain a second temperature code representing a temperature of the basis chip, and to compare the first temperature codes with the second temperature code to output a high temperature representation code, where the first temperature code represents a maximum temperature in the partial regions of all the channels, and the high temperature representation code is one of the first temperature codes or the second temperature code representing a higher temperature.Type: GrantFiled: January 8, 2023Date of Patent: April 22, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Weijie Cheng
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Patent number: 12277979Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.Type: GrantFiled: December 4, 2023Date of Patent: April 15, 2025Assignee: Micron Technology, Inc.Inventors: Carminantonio Manganelli, Paolo Papa, Massimo Iaculo, Giuseppe D'Eliseo, Alberto Sassara
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Patent number: 12271615Abstract: Systems and methods for memory management are described. An example method can include: performing a first determination that may include: comparing a first parameter associated with a storage device to a second parameter associated with an application. In addition, the method may include performing a second determination based on the first determination, where the second determination may include: inserting data into a storage partition of the storage device; and determining to store a minimum processing unit associated with the data in the storage device.Type: GrantFiled: March 3, 2023Date of Patent: April 8, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yangwook Kang, Yang Seok Ki, Changho Choi
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Patent number: 12271629Abstract: The present technology relates to an electronic device. According to the present technology, a host device may include a garbage collection controller and an idle time processor. The garbage collection controller may provide, to a storage device, a health information request command for requesting health information including a host write amount and a storage device write amount, provide, to the storage device, a first garbage collection control command for requesting garbage collection cost information based on the health information, provide, to the storage device, a second garbage collection control command for instructing to perform garbage collection based on the garbage collection cost information and an idle time of the storage device. The idle time processor may process information on the idle time.Type: GrantFiled: December 14, 2022Date of Patent: April 8, 2025Assignee: SK hynix Inc.Inventors: Jeong Ho Jeon, Kang Rak Kwon
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Patent number: 12272404Abstract: A memory device includes selected word lines coupled to first memory cells, a first group of unselected word lines coupled to second memory cells, a second group of unselected word lines coupled to third memory cells; and a peripheral circuit coupled to the selected word lines, the first group of unselected word lines, and the second group of unselected word lines. The peripheral circuit is configured to apply program voltages on the selected word lines, apply first pass voltages on the first group of unselected word lines; and apply second pass voltages on the second group of unselected word lines. A first maximum value of the first pass voltages is different from a second maximum value of the second pass voltages.Type: GrantFiled: December 12, 2023Date of Patent: April 8, 2025Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Haibo Li, Joohyun Jin, Chao Zhang
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Patent number: 12265733Abstract: Methods and apparatus for efficiently handling large data files and their updates in NAND memory. In one example, provided is a data-storage system configured to reduce the frequency of data relocations by segregating a large data file into a plurality of subfiles. The size of such subfiles is appropriately selected to reduce the probability of occurrence for host-relocation conflicts and the magnitude of write amplification, thereby enabling the data-storage system to provide better quality of service while substantially maintaining acceptable levels of other pertinent performance characteristics. In some examples, a sequence of host read-modify-write commands is handled by generating a copy of implicated subfiles in a data buffer, applying subfile updates to the copy in the data buffer in accordance with the sequence, and relocating the implicated subfiles in the NAND memory using the updated versions thereof from the data buffer.Type: GrantFiled: August 14, 2023Date of Patent: April 1, 2025Assignee: Sandisk Technologies, Inc.Inventors: Niles Yang, Daniel J. Linnen, Judah Gamliel Hahn
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Patent number: 12265711Abstract: Methods that may be performed by a universal flash storage (UFS) device of a computing device for configuring flash memory cells. Various embodiments may include setting a number of degraded triple-level cells (TLCs) attribute, and configuring at least one degraded TLC as at least one single-level cell (SLC) based on the number of degraded TLCs attribute, the at least one degraded TLC being not functional as a TLC and functional as an SLC. Some embodiments may include identifying the at least one degraded TLC based on at least one degradation attribute associated with the at least one degraded TLC, the at least one degradation attribute configured to indicate that the at least one degraded TLC is not functional as a TLC, and identifying an amount of degraded TLCs that are not functional as a TLC.Type: GrantFiled: January 15, 2024Date of Patent: April 1, 2025Assignee: QUALCOMM IncorporatedInventors: Ashwini Pandey, Pratibind Kumar Jha, Manish Garg
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Patent number: 12265729Abstract: This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes detecting, by the memory controller, a flush operation associated with a write buffer. The method also includes detecting, by the memory controller during the flush operation, a command for placement into a command queue. The method further include prioritizing, by the memory controller, the flush operation to by placing the command in a wait queue and maintaining the flush operation. Other aspects and features are also claimed and described.Type: GrantFiled: January 16, 2024Date of Patent: April 1, 2025Assignee: QUALCOMM IncorporatedInventors: Vamsi Krishna Sambangi, Sai Naresh Gajapaka, Venkatesha M Iyengar, Madhu Yashwanth Boenapalli, Sai Praneeth Sreeram
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Patent number: 12260108Abstract: A method for discarding personal information comprises at least one among partial overwriting, SLC programming, and applying an erase pulse. The method for discarding personal information comprises a step for acquiring the program status of personal information-containing data of a memory block to be erased, generating data having a status that is equal to or higher than the program status corresponding to the personal information, and carrying out a partial overwriting operation on the personal information by using the generated data.Type: GrantFiled: January 11, 2024Date of Patent: March 25, 2025Assignee: Korea University Research and Business FoundationInventors: Dong Hoon Lee, Na Young Ahn
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Patent number: 12260101Abstract: Apparatuses and methods for read source determination are provided. One example apparatus can include a controller configured to determine a source for read requests and to direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount, and direct read requests for the first portion of data to a first block of quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount.Type: GrantFiled: September 29, 2023Date of Patent: March 25, 2025Assignee: Micron Technology, Inc.Inventors: Tom V. Geukens, Byron D. Harris
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Patent number: 12254204Abstract: A data storage device and method are disclosed for host-controlled data compression. In one embodiment, a data storage device is provided comprising a memory and a controller configured to communicate with the memory. The controller is further configured to selectively compress target data, wherein the target data is only compressed in response to receiving a compression request from a host; receive the compression request from the host; and in response to receiving the compression request from the host, compress the target data. Other embodiments are disclosed.Type: GrantFiled: July 26, 2023Date of Patent: March 18, 2025Assignee: Sandisk Technologies, Inc.Inventors: Prabhakar Ballapalle, ANup Srikanth
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Patent number: 12248711Abstract: A storage device configured to be connected to a redundant array of inexpensive disk (RAID) controller includes a plurality of non-volatile memories. A memory controller is configured to control the plurality of non-volatile memories to store data distributed by the RAID controller based on a RAID configuration signal received from the RAID controller. The memory controller is configured to perform self-diagnosis on the plurality of non-volatile memories to determine whether at least one of the plurality of non-volatile memories has an uncorrectable error when a RAID configuration signal is deactivated.Type: GrantFiled: November 15, 2022Date of Patent: March 11, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyunjoon Yoo, Dongouk Moon
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Patent number: 12248363Abstract: A storage device non-fatal error debug system includes a storage device including a storage device chassis, storage device subsystems housed in the storage device chassis, and a non-fatal error debug subsystem provided in the storage device chassis and coupled to each of the storage device subsystems. The non-fatal error debug subsystem provides a counter system for each of a plurality of data path stages performed by the storage device subsystems to provide data path(s) in the storage device, and monitors each counter system during the execution of commands by the storage device subsystems via the performance of the data path stages. When the non-fatal error debug subsystem determines that a counter system provided for a data path stage performed by a storage device subsystem to provide a data path in the storage device indicates a non-fatal error, it collects debug information associated with that data path stage.Type: GrantFiled: February 6, 2023Date of Patent: March 11, 2025Assignee: Dell Products L.P.Inventors: Girish Desai, Alex Liu
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Patent number: 12248703Abstract: In some exception flows, a device controller may need to store and subsequently recover a current state of a host queue. In these particular exception flows, recovering the current state of the host queue is complex due to the varying states a host queue may be in at the time of storing, including having pending commands in the host queue. Examples of such exception flows include low power modes in client SSDs and live migrations in enterprise SSDs. Using dummy host submission and completion queues during the host queue recovery process allows the device controller to efficiently operate even when there are pending commands in the host queue. The dummy queues may be stored in the HMB, internal DRAM, or any other system dummy buffer (i.e., in a different device or tenant).Type: GrantFiled: November 3, 2023Date of Patent: March 11, 2025Assignee: Sandisk Technologies, Inc.Inventor: Shay Benisty
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Patent number: 12235766Abstract: A CXL memory module, a memory data swap method and a computer system. The CXL memory module may include a flash memory chip, a memory chip, and a controller chip connected with the flash memory chip and the memory chip. The controller chip is configured to be able to swap a part of data in the memory chip into the flash memory chip.Type: GrantFiled: March 19, 2024Date of Patent: February 25, 2025Assignee: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGYInventor: Jin Dai
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Patent number: 12235760Abstract: Apparatus might include a first plurality of signal lines, a second plurality of signal lines, a controller, a first die, and a second die. The controller, the first die, and the second die might each be connected to the first plurality of signal lines and connected to the second plurality of signal lines. The first die and the second die might each include termination circuitry connected to a particular signal line of the second plurality of signal lines. The first die might be configured to activate its termination circuitry in response to receiving a particular combination of signal values on the first plurality of signal lines. The second die might be configured to deactivate its termination circuitry in response to receiving the particular combination of signal values on the first plurality of signal lines.Type: GrantFiled: June 28, 2022Date of Patent: February 25, 2025Assignee: Lodestar Licensing Group LLCInventor: Terry Grunzke
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Patent number: 12236117Abstract: One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.Type: GrantFiled: September 1, 2023Date of Patent: February 25, 2025Assignee: PURE STORAGE, INC.Inventors: Hari Kannan, Gordon James Coleman, Yijie Zhao, Peter E. Kirkpatrick, Robert Lee, Yuhong Mao, Boris Feigin
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Patent number: 12236139Abstract: A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.Type: GrantFiled: June 8, 2023Date of Patent: February 25, 2025Assignee: Kioxia CorporationInventors: Akio Sugahara, Masahiro Yoshihara
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Patent number: 12235727Abstract: Client data layout retention across server disruption can be performed and managed. In response to a data layout request from a client device (CD), a server can communicate, to CD, metadata, comprising a mapping of a group of blocks, in a data store of the server, to which CD is able to write data to the file, a file offset associated with the file, and a filesystem block number (FSBN) associated with the file offset. CD can write data to the group of blocks. CD can communicate data layout commit request, comprising the metadata relating to data layout, including file offset and FSBN, to the server. If server disruption occurs prior to committing data layout, CD can communicate reclaim request, comprising the metadata, to server, and server can recreate the data layout and commit the data layout to the data store based on the metadata.Type: GrantFiled: July 21, 2023Date of Patent: February 25, 2025Assignee: DELL PRODUCTS L.P.Inventors: Soumyadeep Sen, JeanPierre Bono, Sitaram Pawar, Ahsan Rashid
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Patent number: 12229412Abstract: A memory system includes a nonvolatile memory that includes a plurality of regions; a volatile memory; and a controller that is connected to the nonvolatile memory and the volatile memory. The controller is configured to store in the volatile memory a plurality of first counter values each indicating the number of times each of the plurality of regions has been accessed and a plurality of second counter values respectively corresponding to the plurality of first counter values, and write the first counter value of a first region of the plurality of regions to the nonvolatile memory in response to the second counter value of the first region being equal to or more than a threshold value.Type: GrantFiled: February 28, 2023Date of Patent: February 18, 2025Assignee: Kioxia CorporationInventor: Kazuhiro Fukutomi
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Patent number: 12230232Abstract: Methods, systems, and devices for configurable types of write operations are described. A memory device may receive a write command to write data in a zone of a memory system. The memory device may identify a physical address to store the data using a cursor associated with the zone based at least in part on receiving the write command. In some examples, the cursor may be associated with a type of a write operation based on a quantity of data associated with the cursor. As such, the memory device write, using a first type of the write operation or a second type of the write operation in accordance with the quantity of data, the data, and an indication of the type of the write operation used to write the data into the memory system.Type: GrantFiled: August 9, 2022Date of Patent: February 18, 2025Assignee: Micron Technology, Inc.Inventor: Giuseppe Cariello
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Patent number: 12223169Abstract: A far memory device includes a far memory controller, a memory device coupled to the controller, a first port coupled to the far memory controller to support communication with a host processor over a first serial computer expansion bus, and a second port coupled to the far memory controller to support communication with a non-volatile data storage drive over a second serial computer expansion bus. The far memory device serves as a cache between the host processor and the non-volatile data storage drive and may perform aspects of cache management on behalf of the host processor.Type: GrantFiled: March 17, 2022Date of Patent: February 11, 2025Assignee: Lenovo Global Technology (United States) Inc.Inventor: Jonathan Hinkle
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Patent number: 12224778Abstract: According to one embodiment, a dictionary compressor for compressing input first data includes a buffer and a search unit. The buffer stores data input to the dictionary compressor prior to the first data. The search unit acquires, from the first data, partial data strings each having a first data length and having head positions in the first data, respectively, that are sequentially shifted by a second data length shorter than the first data length. The search unit performs search processes in parallel and acquires search results respectively corresponding to the search processes, the search processes searching the buffer to acquire respective match data strings that at least partially match the partial data strings, respectively.Type: GrantFiled: March 7, 2023Date of Patent: February 11, 2025Assignee: KIOXIA CORPORATIONInventors: Keiri Nakanishi, Sho Kodama, Daisuke Yashima
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Patent number: 12216571Abstract: According to an embodiment of the present disclosure, a storage device may include a memory device, and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command may include a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the read command is a command for requesting data stored in the memory device, a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses, and an extra header segment including information on the at least two or more logical addresses.Type: GrantFiled: October 13, 2023Date of Patent: February 4, 2025Assignee: SK hynix Inc.Inventors: Byung Jun Kim, Jea Young Zhang, Young Kyu Jeon, Kyoung Ku Cho
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Patent number: 12217797Abstract: A method of operating a storage device includes: sensing an external voltage supplied from a host device; selecting a data transfer mode, where the data transfer mode is either a normal mode or a brown-out mode according to the external voltage; and performing a write operation or a read operation according to the selected mode, wherein: the data transfer mode is selected as the normal mode when the external voltage is within a normal range between a first operation voltage and a second operation voltage, and the data transfer mode is selected as the brown-out mode when the external voltage is within a low power range below the normal range and between the second operation voltage and a power-off detection voltage; and wherein one or more types of input/output operations of the host device are supported in both the normal mode and the brown-out mode.Type: GrantFiled: June 10, 2022Date of Patent: February 4, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hojin Chun, Jiwon Park
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Patent number: 12216931Abstract: A host stores “context” metadata for logical block addresses (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data; in another embodiment, the context can point to other metadata.Type: GrantFiled: January 15, 2024Date of Patent: February 4, 2025Assignee: Radian Memory Systems, LLCInventors: Alan Chen, Craig Robertson, Robert Lercari, Andrey V. Kuzmin
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Patent number: 12216933Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes establishing a connection between the memory storage device and a host system; receiving a first request from the host system via the connection; detecting a status of the memory storage device in a time range according to the first request; and determining whether to use a memory in the host system according to the status.Type: GrantFiled: September 19, 2023Date of Patent: February 4, 2025Assignee: PHISON ELECTRONICS CORP.Inventor: Kok-Yong Tan
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Patent number: 12216572Abstract: Methods, systems, and devices for atomic write operations are described. A host system may receive a sequence of data that includes a first set of data and a second set of data. The host system may determine, based on the sequence of data, a first set of contiguous logical addresses for the first set of data and a second set of contiguous logical address for the second set of data. The host system may then transmit to a memory system a write command that indicates the first set of contiguous logical addresses and the second set of contiguous logical addresses. The first set of contiguous logical addresses may be discontiguous with the second set of contiguous logical addresses.Type: GrantFiled: February 29, 2024Date of Patent: February 4, 2025Assignee: Micron Technology, Inc.Inventor: Giuseppe Cariello
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Patent number: 12216916Abstract: Provided are a storage device and an operating method thereof. The storage device includes a non-volatile memory including a plurality of memory regions and a storage controller configured to control the non-volatile memory through a performance path and at least one direct path, the storage controller including a buffer memory configured to store recovery data, wherein the storage controller writes the recovery data to the non-volatile memory through the at least one direct path in response to power being cut off and a fault being detected in the performance path, the performance path is a path for performing a write operation, a read operation, and an erase operation, and the at least one direct path is a path for performing only a write operation.Type: GrantFiled: November 1, 2022Date of Patent: February 4, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Youngsik Lee, Seunghyun Shin, Sunmi Yoo