Programmable Read Only Memory (prom, Eeprom, Etc.) Patents (Class 711/103)
  • Patent number: 11928061
    Abstract: A data management method is applied to a computing system. The computing system includes a plurality of NUMA nodes, each NUMA node includes a processor and a memory, and each memory is used to store a data block. In the method, a processor in a NUMA node receives an operation request for a data block, and the processor processes the data block, and allocates a replacement priority of the data block in cache space of the NUMA node based on an access attribute of the data block, where the access attribute of the data block includes a distance between a home NUMA node of the data block and the NUMA node.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: March 12, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Chang Song
  • Patent number: 11928054
    Abstract: As one aspect of the present disclosure, an electronic device is disclosed. The device may include: a volatile memory device; and a controller configured to be connected with a host processor and the volatile memory device, wherein the controller may be further configured to receive a request related to data access from the host processor, determine whether data corresponding to address information is compressed based on the address information included in the request, and communicate with the volatile memory device and process the request based on a result of determining whether the data is compressed.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: March 12, 2024
    Assignee: METISX CO., LTD.
    Inventors: Ju Hyun Kim, Jin Yeong Kim, Jae Wan Yeon
  • Patent number: 11928053
    Abstract: A system controller determines a to-be-collected first logical chunk group. The first logical chunk group includes a first data logical chunk located in a first solid state disk of the plurality of solid state disks. Valid data is stored in a first logical address in the first logical chunk group, and there is a correspondence between the first logical address and an actual address in which the valid data is stored. The system controller creates a second logical chunk group. At least one second data logical chunk in the second logical chunk group is distributed in the solid state disk in which the first data logical chunk storing a valid data is located in order to ensure that the valid data is migrated from the first logical chunk group to the second logical chunk group, but an actual address of the valid data remains unchanged.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: March 12, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Guiyou Pu, Yang Liu, Qiang Xue
  • Patent number: 11921627
    Abstract: Methods, systems, and devices for usage level identification for memory device addresses are described. Systems, techniques, and devices are described herein in which a memory device may determine where to store data according to a level of usage of the data. The memory device may receive a write command indicating data to be written, a type of the data, and a logical address of a memory array for writing the data. The memory device may identify an entry associated with the logical address in a table that maps the logical address to a physical address of the memory array. The entry may include a field configured to maintain a level of usage for the logical address. The memory device may update the level of usage value according to a process and write the data to a physical address of the memory array based on the level of usage value.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 5, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Luca Porzio, Roberto Izzi, Giuseppe Cariello
  • Patent number: 11921649
    Abstract: Various implementations described herein relate to systems and methods for a solid state drive (SSD) that includes a first controller and a NAND package. The NAND package includes a plurality of dies grouped into a plurality of subsets. The NAND package includes a second controller operatively coupled to each of the plurality of subsets via a corresponding one of a plurality of parallel mode channels. The first controller is operatively coupled to the NAND package via a serial link.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: March 5, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Tiruvur Radhakrishna Ramesh, Avadhani Shridhar, Senthilkumar Diraviam, Gary Lin
  • Patent number: 11923016
    Abstract: Systems, apparatuses and methods may provide for technology that resumes a program operation with respect to NAND memory during a first tier in response to a suspension counter reaching a first threshold and resumes the program operation with respect to the NAND memory during a second tier in response to the suspension counter reaching a second threshold. The technology may also resume the program operation with respect to the NAND memory during a third tier in response to the suspension counter reaching a third threshold. Additionally, the technology may service one or more read operations with respect to the NAND memory until the suspension counter reaches the first threshold during the first tier, until the suspension counter reaches the second threshold during the second tier, and until the suspension counter reaches the third threshold during the third tier.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Aliasgar S. Madraswala, Sagar Upadhyay, Jiantao Zhou
  • Patent number: 11922028
    Abstract: According to one embodiment, when it is determined that a first storage device of a plurality of storage devices is to be removed and an additional storage device is connected to a storage controller, the storage controller writes update data portions corresponding to data portions already written to the first storage device to any storage device selected from remaining one or more storage devices of the plurality of storage devices except for the first storage device and the additional storage device. Further, the storage controller writes update data portions corresponding to data portions already written to the remaining one or more storage devices to any storage device selected from the remaining one or more storage devices and the additional storage device.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: March 5, 2024
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11915782
    Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Min Lee, Nam Hyung Kim, Dae Jeong Kim, Do Han Kim, Min Su Kim, Deok Ho Seo, Won Jae Shin, Yong Jun Yu, Il Gyu Jung, In Su Choi
  • Patent number: 11914882
    Abstract: Embodiments of a system and method to prevent mass deletion of data in a data storage system. A data deletion operation comprises a delete operation marking blocks to be deleted followed by a garbage collection (GC) operation to remove marked blocks from storage media. Based on historical information regarding deletions per GC cycle and certain user-defined thresholds based on data age, the storage system can detect any significant deviations as potentially dangerous. If a deletion in excess of a deviation threshold is detected, the next GC operation is skipped to provide a delay period during which time the user can investigate the data delete command and restore data if necessary. De-risking conditions such as known abnormal high deletion periods or new system installation can be used to override any garbage collection delay.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: February 27, 2024
    Assignee: Dell Products L.P.
    Inventors: Senthil Ponnuswamy, Mahadev Karadigudda, Madhu Agrahara Gopalakrishna, Praveen Kumar Lakkimsetti
  • Patent number: 11915748
    Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Noboru Shibata, Yasuyuki Matsuda
  • Patent number: 11914897
    Abstract: Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include enabling a subset of memory die of a memory system having multiple memory die, starting an active timer for each active memory die, initializing execution of a buffered memory command at each active die based on a timestamp associated with the buffered memory command, and disabling a first memory die of the subset of memory die when the active timer for the first die expires to maintain compliance with a power budget of the memory system.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventor: David Aaron Palmer
  • Patent number: 11907574
    Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform a program operation and in response to the command to perform the program operation, begin execution of the program operation. The controller might be further configured to while executing the program operation, receive a command to perform a read operation; in response to the command to perform the read operation, suspend the execution of the program operation; and with the execution of the program operation suspended, execute the read operation.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Siciliani, Floriano Montemurro
  • Patent number: 11907059
    Abstract: An abnormal power loss recovery method, a memory control circuit unit, and a memory storage device are provided. The method is configured for a memory storage device including a rewritable non-volatile memory module having a plurality of super-physical units. The super-physical units include at least two physical erasing units, and each of the physical erasing units belongs to a different operation unit and includes a plurality of physical programming units. The method includes: reading data stored in a first super-physical unit without a corresponding RAID ECC code when a memory storage device is powered on again and detected as an abnormal power loss to obtain first data, and the first super-physical unit is a last super-physical unit to which data is written before the abnormal power loss occurs; and copying the first data to a second super-physical unit.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: February 20, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 11907114
    Abstract: In certain aspects, dynamic remapping of memory addresses is provided and includes initiating a remapping of a logical block from a “mapped block” to a “remapped block.” Logical address locations for the logical block are mapped to physical address locations in the mapped block. The mapped and remapped blocks include non-volatile memory. A read command is received and determined to be for reading from a logical address location of the logical block, and the logical address location is determined to be mapped to a physical address location. Data is read from the physical address location of the mapped block. A write command is received and determined to be for writing data to the logical address location. Data is written to the physical address location of the remapped block. The read command is received after the initiation of the remapping and before the writing of the data to the remapped block.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: February 20, 2024
    Assignee: SMART IOPS, INC.
    Inventors: Ashutosh Kumar Das, Manuel Antonio d'Abreu
  • Patent number: 11907567
    Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a non-volatile memory and a controller electrically connected to the non-volatile memory and configured to control the non-volatile memory. The controller is configured to specify a partition format of a predetermined partition included in the non-volatile memory based on master boot record information stored in the non-volatile memory. The controller is configured to specify a file system that manages the predetermined partition. The controller is configured to specify logically erased first data and physically erase the first data when logical erasure of data in the predetermined partition is detected by a method consistent with the specified file system.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: February 20, 2024
    Assignee: Kioxia Corporation
    Inventor: Tadashi Nagahara
  • Patent number: 11909423
    Abstract: According to one embodiment, a compression circuit generates substrings from input data for (3+M) cycles, the input data being N bytes per cycle, a byte length of each substring being greater than or equal to (N×(1+M)+1); obtains a set of matches, each of the matches including at least one past input data which input past and corresponds to at least a part of each of the substrings; selects a subset of matches from the set of matches including the input data of one cycle; and outputs the subset of matches. M is zero or a natural number. N is a positive integer which is two or more.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: February 20, 2024
    Assignee: Kioxia Corporation
    Inventors: Sho Kodama, Keiri Nakanishi, Daisuke Yashima
  • Patent number: 11900136
    Abstract: A method for ahead of time (AoT) compiling during a play of a legacy game is provided. The method includes scanning a memory device for an executable code of the legacy game, decoding the executable code, and translating the executable code into a first source code. The method further includes compiling the first source code to output a first compiled code, determining whether a user input during the play of the legacy game is received, and determining whether a fiber for servicing the user input is created. The fiber provides directionality of execution between the first compiled code and a second compiled code. The method includes executing the fiber in response to determining that the fiber for servicing the user input is created. The fiber is executed to generate one or more image frames of the legacy game.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: February 13, 2024
    Assignee: Sony Interactive Entertainment LLC
    Inventors: Ernesto Corvi, George Weising, David Thach
  • Patent number: 11899574
    Abstract: Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: February 13, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Qing Liang
  • Patent number: 11899938
    Abstract: Methods, systems, and devices for techniques to reduce write amplification are described. A memory device may receive a write command from a host device and may determine that a quantity of commands stored in a buffer for execution by a memory array satisfies a first threshold. In some examples, the memory device may identify whether a write amplification parameter associated with the memory array satisfies a second threshold. The memory device may write data associated with the write command to the memory array using a first mode to write the data or a second mode to write the data based on determining that the quantity of commands satisfies the first threshold and/or identifying whether the write amplification parameter satisfies the second threshold. In some examples, the memory device may adjust a value of the first threshold or the second threshold or both based on the write amplification parameter.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: February 13, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Yanhua Bi
  • Patent number: 11899958
    Abstract: A method for discarding personal information comprises at least one among partial overwriting, SLC programming, and applying an erase pulse. The method for discarding personal information comprises a step for acquiring the program status of personal information-containing data of a memory block to be erased, generating data having a status that is equal to or higher than the program status corresponding to the personal information, and carrying out a partial overwriting operation on the personal information by using the generated data.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: February 13, 2024
    Assignee: Korea University Research and Business Foundation
    Inventors: Dong Hoon Lee, Na Young Ahn
  • Patent number: 11899952
    Abstract: A system can log data access activity to a memory array with a metadata module while the memory array is logically divided into multiple namespaces. A workload can be determined for each namespace by the metadata module and a metadata strategy can be created with the metadata module in view of the respective namespace workloads. A first metadata and second metadata may be generated for respective first and second user-generated data for storage into a first namespace of the multiple namespaces. The first metadata can be compressed with a compression level prescribed by the metadata strategy in response to a detected or predicted workload to the first namespace before the first metadata, second metadata, first user-generated data, and second user-generated data are each stored in the first namespace.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 13, 2024
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, David W. Claude, Daniel J. Benjamin, Thomas V. Spencer, Matthew B. Lovell
  • Patent number: 11899966
    Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: February 13, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Mark A. Helm, Giuseppina Puzzilli, Peter Feeley, Yifen Liu, Violante Moschiano, Akira Goda, Sampath K. Ratnam
  • Patent number: 11894046
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is further configured to receive a key value (KV) pair data, determine a size of a value length and a size of a target wordline of the memory device for programming of the KV pair data, determine a size of residual data, store the residual data in a location separate from the target wordline and the KV pair data minus the residual data to the target wordline, and read the residual data from the location separate and the target wordline data in response to a read command for the KV pair data. The size of the value length is greater than the size of the target wordline. The size of the residual data is the size of the value length minus the size of the target wordline.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alexander Bazarsky, David Avraham, Ran Zamir
  • Patent number: 11894079
    Abstract: A memory controller includes an over-program controller that preprograms and then erases the memory cells such that each of the memory cells has a first threshold voltage level, wherein fast cells are detected among the memory cells according to a threshold voltage less than or equal to a second threshold voltage less than the first threshold voltage, and a processor that generates fast cell information identifying the fast cells among the memory cells and stores the fast cell information in a buffer. The over-program controller controls the over-programming of the fast cells and normal programming of normal cells among the memory cells based on the fast cell information stored in the buffer.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: February 6, 2024
    Inventors: Hyeji Lee, Raeyoung Lee, Jinkyu Kang, Sejun Park, Jaeduk Lee
  • Patent number: 11893425
    Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a processor executing a trusted execution environment (TEE) comprising a field-programmable gate array (FPGA) driver to interface with an FPGA device that is remote to the apparatus; and a remote memory-mapped input/output (MMIO) driver to expose the FPGA device as a legacy device to the FPGA driver, wherein the processor to utilize the remote MMIO driver to: enumerate the FPGA device using FPGA enumeration data provided by a remote management controller of the FPGA device, the FPGA enumeration data comprising a configuration space and device details; load function drivers for the FPGA device in the TEE; create corresponding device files in the TEE based on the FPGA enumeration data; and handle remote MMIO reads and writes to the FPGA device via a network transport protocol.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: February 6, 2024
    Assignee: INTEL CORPORATION
    Inventors: Reshma Lal, Pradeep Pappachan, Luis Kida, Soham Jayesh Desai, Sujoy Sen, Selvakumar Panneer, Robert Sharp
  • Patent number: 11893237
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: February 6, 2024
    Assignee: Kioxia Corporation
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • Patent number: 11886750
    Abstract: A system and method employing a distributed hardware architecture, either independently or in cooperation with an attendant data structure, in connection with various data processing strategies and data analytics implementations are disclosed. A compute node may be implemented independent of a host compute system to manage and to execute data processing operations. Additionally, an unique algorithm architecture and processing system and method are also disclosed. Different types of nodes may be implemented, either independently or in cooperation with an attendant data structure, in connection with various data processing strategies and data analytics implementations.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: January 30, 2024
    Inventors: Robert Bismuth, Mike Stengle
  • Patent number: 11875064
    Abstract: A solid state drive (SSD) enabled to process and store block addressable and byte addressable data, includes a first storage region for storing byte addressable data, a second storage region for storing block addressable data, and an SSD controller coupled to the first storage region and the second storage region by a bus. The SSD controller includes a processor and an interface for receiving data packets from a host. The SSD controller receives a data packet from the host at the interface, determines whether the data packet includes byte addressable data or block addressable data at the processor, selects either the first storage region or the second storage region based on the determination, and stores the data associated with the data packet in the selected storage region.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: January 16, 2024
    Assignee: Kioxia Corporation
    Inventors: Edward Xiao, Scott Stetzer
  • Patent number: 11875858
    Abstract: A memory device includes a memory array of memory cells and control logic operatively coupled to the memory array. The control logic to perform memory erase operations including: performing a true erase sub-operation by causing multiple pulse steps to be applied sequentially to a group of memory cells of the memory array, wherein each sequential pulse step of the multiple pulse steps occurs during a pulse-step period and at a higher voltage compared to an immediately-preceding pulse-step; in response to detecting an erase suspend command during a pulse step, suspending the true erase sub-operation at a start of a subsequent pulse-step period after the pulse step; and resuming the true erase sub-operation at an end of the subsequent pulse-step period.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: January 16, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Tomoharu Tanaka
  • Patent number: 11875062
    Abstract: Disclosed are systems and methods for proactively recovering files stored in flash storage devices. The method may be performed at a flash file system. The method may include receiving a write command targeting a first file in a flash memory. The method may also include generating a reference hash corresponding to the first file, and storing the reference hash in the flash memory. The method may also include receiving a read command targeting the first file. In response to receiving the read command, the method may also include: providing a request for a logical block address corresponding to the first file to the flash manager, and receiving a response for the read command. The method may also include, in accordance with a determination that one or more hashes do not map to the first file, performing a file recovery operation for a second file based on the one or more hashes.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: January 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Chakradhar Kommuri
  • Patent number: 11875041
    Abstract: A semiconductor device of an embodiment includes a seed generator circuit configured to generate a seed from inputted data by using first random number sequence data generated by an XorShift circuit; and a random number generator circuit configured to receive the seed as input to generate second random number sequence data by a second XorShift circuit.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: January 16, 2024
    Assignee: Kioxia Corporation
    Inventors: Tsuyoshi Atsumi, Yasuhiko Kurosawa
  • Patent number: 11869569
    Abstract: A semiconductor memory device includes a mammy cell array including a plurality of memory cells and a control logic circuit configured to control the semiconductor memory device. The control logic circuit includes a mode register and a remaining lifetime calculating device configured to count usage metrics based on one or more of the following: a number of clock signals received from a memory controller, an amount of data transmitted or received to or from the memory controller, and/or a number of commands received from the memory controller. The remaining lifetime calculating device generates a remaining lifetime code representing a remaining lifetime of the semiconductor memory device based on the usage metrics, and stores the remaining lifetime code in the mode register.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: January 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Kyu Kang, Jieun Shin, Hocheol Bang, Haewon Lee
  • Patent number: 11868245
    Abstract: Devices and techniques for improving memory access operations of a memory device are provided. In an example, a method can include loading multiple LBA-to-physical address (L2P) regions of an L2P table from memory arrays of the memory device to a mapping cache in response to determining the LBA of the memory access command is not within the L2P region including of a mapping cache. When the memory access command is a sequential command, the multiple L2P regions loaded to the mapping cache can provide improved memory access performance.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Xinghui Duan, Bin Zhao, Jianxiong Huang
  • Patent number: 11861237
    Abstract: A storage device includes a nonvolatile memory device having a plurality of memory cells and a storage controller. Each memory cell is set to one of a plurality of memory cell states, wherein distinct subsets of the memory cell states are associated with one of a plurality of data sets. The storage controller accesses data stored in one of the memory cells in a first state, performs a multiplier-accumulator (MAC) operation on the data, and sets the one memory cell to a second state corresponding to a result of the MAC operation to perform an in-place update.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Hyun Kim, Jong-Hoon Lee
  • Patent number: 11860798
    Abstract: Aspects disclosed herein relate to a method comprising: obtaining a list of data paths to at least one persistent storage device through a plurality of NUMA nodes; associating with each data path, access performance information; receiving a request to access one of the at least one persistent storage device; calculating a preferred data path to the one of the at least one persistent storage device using the access performance information; and accessing the one of the at least one persistent storage device using the preferred data path.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: January 2, 2024
    Assignee: Nyriad, Inc.
    Inventors: Stuart John Inglis, Leon Wiremu Macrae Oud, Dominic Joseph Michael Houston Azaris, Jack Spencer Turpitt
  • Patent number: 11861239
    Abstract: A device includes a memory array with first memory cell and second memory cell, and control logic, operatively coupled with the memory array, to cause a first threshold voltage (Vt) state read out of the first memory cell to be converted to a first integer value and a second Vt state read out of the second memory cell to be converted to a second integer value; index, within a decoding table using the first integer value and the second integer value, to determine a set of three logical bits; and output, as a group of logical bits to be returned in response to a read request, the set of three logical bits with a second set of logical bits corresponding to the first Vt state.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Tomoharu Tanaka
  • Patent number: 11860732
    Abstract: A request is received to program host data to a memory device of a memory sub-system. The host data is associated with a logical address. A redundancy factor that corresponds to the logical address associated with the host data is obtained. A first physical address associated with a first set of cells of the memory device and a second physical address associated with a second set of cells of the memory device are determined based on the redundancy factor. The first set of memory cells is to store the host data and the second set of memory cells is to store redundancy metadata associated with the host data. The host data is programmed to the first set of memory cells. The redundancy metadata associated with the host data is programmed to the second set of memory cells.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Juane Li, Fangfang Zhu, Seungjune Jeon, Yueh-Hung Chen
  • Patent number: 11860791
    Abstract: The disclosed technology relates to determining physical zone data within a zoned namespace solid state drive (SSD), associated with logical zone data included in a first received input-output operation based on a mapping data structure within a namespace of the zoned namespace SSD. A second input-output operation specific to the determined physical zone data is generated wherein the second input-output operation and the received input-output operation is of a same type. The generated second input-output operation is completed using the determined physical zone data within the zoned namespace SSD.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: January 2, 2024
    Assignee: NETAPP, INC.
    Inventors: Abhijeet Prakash Gole, Rohit Shankar Singh, Douglas P. Doucette, Ratnesh Gupta, Sourav Sen, Prathamesh Deshpande
  • Patent number: 11853612
    Abstract: A storage system includes two or more data storage devices and a controller coupled to the two or more data storage devices. Each data storage device of the two or more data storage devices includes zoned namespace (ZNS) architecture. The controller is configured to collect thermal statistics for each data storage device of the two or more data storage devices, analyze the collected thermal statistics, and designate a zone by selecting one or more dies within at least one data storage device of the two or more data storage devices based on the analyzed collected thermal statistics. The data storage device includes a memory device having a plurality of dies and a controller coupled to the memory device. The controller is configured to collect thermal statistics for each die of the plurality of dies, analyze the collected statistics, and allocate one or more dies to form a zone.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: December 26, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Avichay Haim Hodes, Judah Gamliel Hahn, Alexander Bazarsky
  • Patent number: 11853599
    Abstract: A memory system includes a non-volatile memory and a controller that includes a first memory and is configured to write log data to the first memory, including a history of commands for controlling the memory system. An information processing system includes the memory system and an information processing device configured to store an expected value and to transmit a signal that instructs the memory system to stop when a value of the log data transmitted from the memory system does not match the expected value. The expected value and the transmitted value are determined based on the log data of the memory system.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: December 26, 2023
    Assignee: Kioxia Corporation
    Inventors: Takeshi Nakano, Akihiko Ishihara, Shingo Tanimoto, Yasuaki Nakazato, Shinji Maeda, Minoru Uchida, Kenji Sakaue, Koichi Inoue, Yosuke Kino, Takumi Sasaki, Mikio Takasugi, Kouji Saitou, Hironori Nagai, Shinya Takeda, Akihito Touhata, Masaru Ogawa, Akira Aoki
  • Patent number: 11853238
    Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: December 26, 2023
    Assignee: Kioxia Corporation
    Inventors: Kenji Sakaue, Toshiyuki Furusawa, Shinya Takeda
  • Patent number: 11854657
    Abstract: A memory system includes at least one memory die and a controller coupled to the at least one memory die via a data path. The at least one memory die includes plural memory planes and a register storing operation statuses and operation results regarding the respective memory planes. The controller transfers a first status check command to the at least one memory die and receives a first response including the operation statuses and the operation results regarding the respective memory planes.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: December 26, 2023
    Assignee: SK hynix Inc.
    Inventors: Tae Hee You, Beom Ju Shin
  • Patent number: 11847350
    Abstract: According to one embodiment, a storage system performs a first allocation operation of allocating, for a first namespace, a plurality of first blocks included in the blocks of a nonvolatile memory. The storage system performs a read operation, a write operation or an erase operation on one of the first blocks in response to a command received from a host to read, write or erase the one first block, counts the total number of erase operations performed on the first blocks, and notifies the host of the counted number of erase operations in response to a command received from the host to obtain an erase count associated with the first namespace.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: December 19, 2023
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Kanno
  • Patent number: 11847333
    Abstract: A method, computer program product, and computer system for identifying duplicate sectors in a block of a plurality of blocks. The duplicate sectors in the block may be zeroed out. A data reduction operation may be performed on the block after the duplicate sectors are zeroed out.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 19, 2023
    Assignee: EMC IP Holding Company, LLC
    Inventors: Istvan Gonczi, Sorin Faibish, Ivan Basov
  • Patent number: 11847037
    Abstract: Example implementations include a method of receiving a host command identifier associated with a host command, determining a device command associated with the host command and a memory controller device, receiving a device command timestamp corresponding to a time of the determining the device command, and determining a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: December 19, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Paul Edward Hanham, Shigehiro Asano, Julien Margetts
  • Patent number: 11847098
    Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. A plurality of failure resilient address spaces are distributed across the plurality of storage devices such that each of the plurality of failure resilient address spaces spans a plurality of the storage devices. The plurality of computing devices maintains metadata that maps each failure resilient address space to one of the plurality of computing devices. The metadata is grouped into buckets. Each bucket is stored in a group of computing devices. However, only the leader of the group is able to directly access a particular bucket at any given time.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: December 19, 2023
    Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel
  • Patent number: 11847100
    Abstract: Methods and systems implement local file systems of computing nodes which translate random-access read and random-access write operation calls to append-based operation calls in accordance with a distributed file system (“DFS”) implemented across storage nodes of a cloud network. Computer-executable applications running on the computing nodes may generate kernel-level read and write system calls by application programming interfaces (“APIs”) such as the Portable Operating System Interface (“POSIX”) standard, to a local file system. The local file system may translate these read and write system calls to file operations at a DFS implementing an append-only file system, as well as perform storage reclamation upon the DFS periodically and/or upon storage thresholds being exceeded.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: December 19, 2023
    Assignee: Alibaba Group Holding Limited
    Inventors: Windsor Hsu, Jiesheng Wu
  • Patent number: 11842046
    Abstract: A storage fragment management method and a terminal. The method may be applied to a file system of the terminal, and the file system includes at least one segment. The method includes: first determining, by the terminal, a source segment from the file system based on an aging degree of the segment and a valid block ratio of the segment; then determining, by the terminal from the file system based on an aging degree of the source segment, a target segment whose aging degree is consistent with the aging degree of the source segment; and finally migrating, by the terminal, data of a valid block in the source segment to an idle block in the target segment. This method is used to resolve a problem that power consumption is high when data migration is performed on a storage fragment in an existing log-structured file system.
    Type: Grant
    Filed: June 30, 2018
    Date of Patent: December 12, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chao Yu, Hao Chen, Bifeng Tong, Chengliang Zheng, Xiyu Zhou
  • Patent number: 11842069
    Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer. A host sends the storage system a threshold indicating an amount of data that should be stored in the write buffer before the storage system flushes the write buffer to multi-level cell (MLC) blocks in the memory. Using this threshold can extend the amount of time that data is maintained in the write buffer, which can reduce the write-amplification factor and power consumption, as well as increase read performance of the data.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: December 12, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Hadas Oshinsky, Maayan Suliman
  • Patent number: 11836373
    Abstract: Apparatus and methods are disclosed, including receiving an indication to selectively erase first data stored on a first page of a first subset of a group of multi-level memory cells of the storage system, each multi-level memory cell comprising multiple pages and providing, in response the indication to selectively erase the first data, at least one soft erase pulse to the first page of memory cells associated with the first data to induce distribution overlap across different bit levels of the first page of the group of multi-level memory cell.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: December 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe Cariello, Fulvio Rori