Abstract: A memory device includes memory cells in rows, word lines respectively coupled to the rows, and a control circuitry coupled to the memory cells via the word lines. The control circuitry is configured to apply a first program voltage to a first word line of the word lines. The first word line is coupled to a first row of the memory cells. The control circuitry is also configured to, after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the word lines. The second word line is coupled to a second row of the memory cells. The control circuitry is also configured to, after applying the second program voltage to the second word line, apply a first pre-charge voltage to the first word line and a second pre-charge voltage to the second word line. The second pre-charge voltage is greater than the first pre-charge voltage.

Abstract: A method of performing a wear-leveling operation in a flash memory includes: determining a block age for each of a plurality of blocks in the flash memory according to a number of erase operations that have been performed on the flash memory after the block is erased; selecting one or more candidate source blocks from the plurality of blocks by comparing block ages of the plurality of blocks with an age limit; determining a source block from the one or more candidate source blocks according to erase counts or block ages of the one or more candidate source blocks; and performing the wear-leveling operation on the source block.

Abstract: The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.

Abstract: A storage device may include: a plurality of memory dies; and a memory controller for receiving a first read request from a first function, controlling at least one memory die to perform a read operation according to the first read request, and controlling, when receiving a second read request from a second function in the course of the read operation according to the first read request, the at least one memory die to suspend the read operation according to the first read request and to perform a read operation according to the second read request based on a result obtained by comparing performance requirement information of the second function with residual time information of the second read request, which is determined according to a performance degree of the read operation being performed according to the first read request.

Abstract: A storage device includes: a memory; and a storage controller configured to control the memory and to update meta data by controlling the memory. The storage controller includes a journal manager having a range table. The journal manager is configured to: generate a plurality of journal data associated with the update of the meta data, restore the meta data by sequentially performing a replay operation for each of the plurality of journal data, update the range table based on the plurality of journal data, and skip the replay operation for at least one of the plurality of journal data based on the range table.

Abstract: Systems and methods are disclosed including a controller and a memory device comprising a first plane and a second plane where each plane is associated with a respective queue maintained by the controller. The local media controller is configured to perform operations comprising storing, in a first queue associated with the first plane, a first plurality of memory access commands; storing, in a second queue associated with the second plane, a second plurality of memory access commands; and processing the first plurality of memory access commands from the first queue and the second plurality of memory access commands from the second queue.

Abstract: Apparatus, method, and system provided herein are directed to prioritizing cache line writing of compressed data. The memory controller comprises a cache line compression engine that receives raw data, compresses the raw data, determines a compression rate between the raw data and the compressed data, determines whether the compression rate is greater than a predetermined rate, and outputs the compressed data as data-to-be-written if the compression rate is greater than the predetermined rate. In response to determining that the compression rate is greater than the predetermined rate, the cache line compression engine generates a compression signal indicating the data-to-be-written is the compressed data and sends the compression signal to a scheduler of a command queue in the memory controller where writing of compressed data is prioritized.

Abstract: A method for performing data access management of a memory device in a predetermined communications architecture with aid of unbalanced table regions and associated apparatus are provided.

Abstract: A host can determine whether to train an AI accelerator of a memory sub-system. Responsive to determining to train the AI accelerator, the host can determine a training category corresponding to a memory access request. The host can also provide an indication to the memory sub-system that causes training of the AI accelerator to be performed based on the training category.

Abstract: Various implementations described herein relate to systems and methods for managing metadata for conditional update, including adding conditional entry to a list in an in-memory journal for a conditional update associated with a garbage collection write, configuring a base entry in the list to point to the conditional entry, and in response to determining that the conditional update is resolved such that a physical location identified in the conditional entry is valid, freeing the conditional entry.

Abstract: Disclosed herein are methods, systems, and processes to provide coherency across disjoint caches in clustered environments. It is determined whether a data object is owned by an owner node, where the owner node is one of multiple nodes of a cluster. If the owner node for the data object is identified by the determining, a request is sent to the owner node for the data object. However, if the owner node for the data object is not identified by the determining, selects a node in the cluster is selected as the owner node, and the request for the data object is sent to the owner node.

Abstract: A storage device includes nonvolatile memories each including an internal temperature sensor; a memory controller configured having a plurality of operation commands defined for different temperature and an external temperature sensor. The memory controller obtains an external temperature value from the external temperature sensor in a first cycle, obtains an internal temperature value of the internal temperature sensor in a second cycle different from the first cycle, determines a temperature range of a target nonvolatile memory based on the external temperature value when a difference between the external temperature value and the internal temperature value is equal to or less than a first threshold value, to determine the temperature range based on the internal temperature value when the difference exceeds the first threshold, and to provide an operation command corresponding to the temperature range to the target nonvolatile memory.

Abstract: A method of managing a garbage collection (GC) operation on a flash memory includes: dividing a GC operation into a plurality of partial GC operations; determining a default partial GC operation time period for each partial GC operation; determining a partial GC intensity according to at least a basic adjustment factor and an amplification factor; determining the basic adjustment factor according to a type of one or more source blocks corresponding to the GC operation; determining the amplification factor according to a percentage of invalid pages in the one or more source blocks corresponding to the GC operation; and performing the plurality of partial GC operations according to the partial GC intensity and the default partial GC operation time period.

Abstract: A memory device may include a plurality of non-volatile memory devices and a controller. The controller may be configured to generate first parity data for a portion of a data block stored in a plurality of memory blocks of the plurality of non-volatile memory devices, store the first parity data in a swap block that includes one or more non-volatile memory devices of the plurality of non-volatile memory devices, generate second parity data for the data block, store the second parity data in the swap block, perform a partial read back of the data block, store, after performing the partial read back, the second parity data in a subset of the plurality of memory blocks, and release the first parity data from the swap block after storing the second parity data in the subset of the plurality of memory blocks.

Abstract: A memory control component allocates a portion of an auxiliary signaling channel and corresponding memory storage, conventionally dedicated to error correction code (ECC) conveyance and storage, for conveyance of metadata and/or other types of component-level information—splitting the auxiliary channel between metadata and ECC conveyance/storage in proportions that obviate conventional metadata conveyance/storage via the primary data channel and thus maintaining full primary channel bandwidth/storage-capacity for user data.

Abstract: The present invention provides systems and methods for efficiently and effectively priming and initializing a memory. In one embodiment, a memory controller includes a normal data path and a priming path. The normal data path directs storage operations during a normal memory read/write operation after power startup of a memory chip. The priming path includes a priming module, wherein the priming module directs memory priming operations during a power startup of the memory chip, including forwarding a priming pattern for storage in a write pattern mode register of a memory chip and selection of a memory address in the memory chip for initialization with the priming pattern. The priming pattern includes information corresponding to proper initial data values. The priming pattern can also include proper corresponding error correction code (ECC) values. The priming module can include a priming pattern register that stores the priming pattern.

Abstract: A storage device may include a non-volatile memory including a plurality of zones, the non-volatile memory configured to sequentially store data in at least one of the plurality of zones, and a processing circuitry configured to, receive a first write command and first data from a host, the first write command including a first logical address, identify a first zone of the plurality of zones based on the first logical address, compress the first data based on compression settings corresponding to the first zone, and write the compressed first data to the first zone.

Abstract: Systems, apparatuses, and methods related to object management in tiered memory systems are discussed. An example method can include determining a type of characteristic set for each of a plurality of memory objects to be written to a memory system. The memory system can include a first memory device and a second memory device. The method can further include configuring each of the plurality of memory objects to be written to the memory system in the first memory device or the second memory device based on the determination of the type of characteristic set associated with each of the plurality of memory objects. The method can further include writing each of the plurality of memory objects to the first memory device or the second memory device based on the configuration of each of the plurality of memory objects.

Abstract: A storage device includes a memory module including a memory device, a module board including a memory controller configured to control the memory device, and a memory connector disposed on one side of the module board. The storage device also includes a first enclosure disposed on a first surface of the memory module, a second enclosure disposed on a second surface opposite to the first surface of the memory module, and a first sensor disposed on the first enclosure and configured to detect a state and provide a signal for the state to the memory controller. The first enclosure includes a first long side extending in a first direction and a first short side extending in a second direction perpendicular to the first direction. A ratio of the first long side to the first short side ranges from 1.2 to 3.5.

Abstract: A system includes one or more memory devices and a processing device coupled to the memory device(s) to perform operations including receiving a first set of data items from a host system to be programmed to the one or more memory devices. The operations include determining, in view of a first zone group identifier associated with the first set of data items, that each data item of the first set of data items is to be programed to one or more zones associated with a first zone group identified by the first zone group identifier. The operations include identifying a first set of zones across the one or more memory devices that match a size associated with the first zone group and that satisfy a programming parallelism criterion. The operations include programming each of the first set of data items to memory cells residing at the identified first set of zones.

Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.

Abstract: Techniques are provided for dynamic over-provisioning of storage devices. One method comprises obtaining a partitioning of a storage device associated into a first partition and an over-provisioning partition based on an over-provisioning ratio of the storage device, wherein portions of the over-provisioning partition are reallocated as portions of the first partition to replace portions of the first partition; storing user data associated with write operations in the first partition; monitoring a size of the over-provisioning partition; and dynamically adjusting the size of the over-provisioning partition in response to the size of the over-provisioning partition reaching a threshold. The dynamically adjusting the size of the over-provisioning partition may comprise reducing a size of the first partition.

Abstract: A system includes a memory and at least one processing device, operatively coupled to the memory, to perform operations including causing a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device. The PMR utilizes a power protection mechanism to prevent data loss in an event of power loss.

Abstract: A technique for operating a cache is disclosed. The technique includes utilizing a first portion of a cache in a directly accessed manner; and utilizing a second portion of the cache as a cache.

Abstract: Methods, systems, and devices for techniques for detection of shutdown patterns are described. A memory device may receive a set of commands from a host device. The memory device may determine whether the set of commands are associated with a shutdown procedure based on a pattern of the received set of commands. The memory device may initiate one or more operations associated with the shutdown procedure based on identifying that the set of commands are associated with the shutdown procedure. The memory device may receive a shutdown command for the shutdown procedure after initiating the one or more operations associated with the shutdown procedure. The memory device may determine that the set of commands are associated with the shutdown procedure based on a quantity of the set of commands, one or more types of the set of commands, other thresholds associated with the pattern, or a combination thereof.

Abstract: A data storage device comprising a non-volatile storage medium configured to store user data, where the storage medium is organized as one or more partitions, including at least one secure partition. The partitions are defined by a corresponding set of pre-specified physical memory blocks of the storage medium. The data storage device also includes a data path configured to provide data communication between a host computer system and the storage medium of the data storage device. A partition controller of the data storage device is coupled to a switch. In response to an actuation of the switch, the partition controller is configured to cause the data storage device to selectively transition between: a secure mode in which the set of physical memory blocks of each secure partition is connected to the host via the data path; and a non-secure mode in which the set of physical memory blocks of each secure partition is disconnected from the host via the data path.

Abstract: An LCS data compression/decompression system includes an orchestrator device in a resource system with a host operating system and coupled to a storage system via a network. The orchestrator device receives a read instruction from the host operating system directed to data stored in the storage system and, in response, retrieves and uses a data read decompression policy to select one of the storage system and the orchestrator device to perform data decompression operations on the data. The orchestrator device then provides a data read decompression instruction to the storage system to cause the storage system to provide the data to the orchestrator device such that the orchestrator device provides the data to the host operation system after the one of the storage system and the orchestrator device selected using the data read decompression policy performs the data decompression operations on the data.

Abstract: A method is described. The method includes executing solid state drive program code from system memory of a computing system to perform any/all of garbage collection, wear leveling and logical block address to physical block address translation routines for a solid state drive that is coupled to a computing system that the system memory is a component of.

Abstract: A system includes integrated circuit (IC) dice and a processing device that retrieves a first block group to be written to the IC dice, the first block group being a contiguous portion of a file and associated with a first stream ID. In response to determining there is allocable space available in a first group of memory cells assigned to the first stream ID, identify a write pointer of the first group and allocate, within the first group, a contiguous range of physical addresses beyond the write pointer to which to write the first block group. The processing device retrieves a second block group to be written to the IC dice, the second block group associated with a second file, allocates the second block group to a second group of the memory cells, and assigns a second stream ID associated with the second group to the second block group.

Abstract: Devices and techniques for NAND temperature-aware operations are disclosed herein. A device controller can receive a command to write data to a component in the device. A temperature corresponding to the component can be obtained in response to receiving the command. The command can be executed by the controller to write data to the component. Executing the command can include writing the temperature into a management portion of the device that is separate from a user portion of the device to which the data is written.

Abstract: Aspects of a storage device are provided that optimize stream oriented writing of sequential data streams for improved read and write performance. The storage device includes a non-volatile memory including a plurality of blocks, and a controller configured to receive a plurality of host write commands each including a sequential data stream. In response to determining the host write commands include sequential data streams, the controller writes each of the sequential data streams respectively to different sequential open blocks, where the blocks are respectively associated with the sequential data streams. The controller may afterwards read each of the sequential data streams respectively from the different blocks. As a result, sequential data from multiple streams may not be stored in a mixed pattern in a same sequential block, thereby allowing the controller to issue fewer read or relocate commands in a block for a given sequential data stream.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may: determine a first value associated with vibrations within an information handling system (IHS); determine that the first value meets or exceeds a first threshold value; after determining that the first value meets or exceeds the first threshold value: receive first data to store via at least one hard disk drive; and store the first data via at least one solid state memory medium; determine a second value associated with vibrations within the IHS; determine that the second value does not meet or exceed the first threshold value; and in response to determining that the second value does not meet or exceed the first threshold value: retrieve the first data from the at least one solid state memory medium; and store the first data via the at least one hard disk drive.

Abstract: A method may include storing at least a portion of a metadata buffer of a persistent data structure in volatile memory, and storing at least a portion of a data buffer of the persistent data structure in persistent memory. A system may include a processor, a volatile memory coupled to the processor, and a persistent memory coupled to the processor. The processor may be configured to execute procedures including storing at least a portion of a metadata buffer of a persistent data structure in volatile memory, and storing at least a portion of a data buffer of the persistent data structure in persistent memory. A method may include storing at least a portion of a transient part of a persistent data structure in volatile memory, and storing at least a portion of a persistent part of the persistent data structure in persistent memory.

Abstract: In one example, reads in a NAND memory device are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.

Abstract: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). An apparatus includes a main non-volatile memory (NVM) such as a NAND flash memory. A host command queue lists pending data transfer commands to transfer data between the NVM and a host. For each write command received by the NVM to store write data to an associated target location, a controller examines the host command queue. Based on this review, the controller may direct the NVM to read data adjacent the associated target location to which data are to be written by the write command and to transfer the read data to a read cache. The read data may use some or all of the same resources used to store the write data to the NVM. The read data may be subsequently transferred from the read cache to the host.

Abstract: Based on power on of an electronic device, a location of first data in a NAND flash memory of an electronic device is determined. The first data is transmitted to a shadow RAM of the electronic device, outputting the first data is output from the shadow RAM to a host device of the electronic device through a serial peripheral interface (SPI) when accessing the location of the first data in the NAND Flash memory.

Abstract: Techniques are provided for a recovery process with selective ordering and concurrent operations in order to recover from a failure. Representations of active log structures are rebuilt within memory according to ordering values assigned to I/O operations logged within the active log structures. Representation of certain active log structures may be concurrently rebuilt based upon the active log structures comprising I/O operations that are non-overlapping within a distributed file system, have no dependencies, relate to different services, and/or target independent files. Representation of stale log structures are concurrently rebuilt within memory. While rebuilding the log structures and executing the I/O operations, a key value map is concurrently rebuilt within the memory for locating data of the I/O operations. Concurrent operations during the recovery process reduces the time to complete the recovery process, and thus reduces client downtime during the recovery process.

Abstract: In some implementations, a memory device may cache a subset of one or more block family error avoidance (BFEA) lookup tables associated with a block family associated with host data in a first memory location. The block family may be based on at least one of a time window during which the host data was written or a temperature window at which the host data was written. The memory device may receive a read command associated with host data and determine, based on the block family and the subset of the one or more BFEA tables, a threshold voltage offset associated with the host data. The memory device may compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data. The memory device may read, using the modified threshold voltage, the host data from the first memory location.

Abstract: A method includes receiving a value and an identifier from a first memory and hashing the identifier to produce a memory block identifier. The method also includes routing, based on the memory block identifier, a read request to a memory block of a plurality of memory blocks and updating the value received from the first memory based on a property received from the memory block in response to the read request. The memory further includes storing the updated value in the first memory.

Abstract: Methods, systems, and computer program products are provided for field repair recalibration. A field repairable device with a field repairable component (e.g., field replaceable unit (FRU)) is recalibrated in the field. A light sensor dependent on one or more optical layers in a display module is recalibrated in the field based at least in part on the properties of a post-repair FRU that replaced a damaged/inoperable pre-repair FRU. A field recalibrator (e.g., in a field repairable device and/or in a field repair device) may be configured to generate an in-field recalibration of a sensor based at least in part on a pre-repair sample generated by the sensor before repair of a field repairable component and a post-repair sample generated by the sensor after repair of the field repairable component.

Abstract: A memory system having a mode indicator, a set of hardware resources, a set of media, and a controller. When the mode indicator identifies a factory mode, a first portion of the hardware resources is reserved for performance of factory functions by the controller and a second portion of the hardware resources is allocated for performance of normal functions. When the mode indicator identifies a user mode, both the first portion and the second portion are allocated for the performance of the normal function. The normal functions are performed by the controller to at least store data in and retrieve data from the set of media in response to requests from a host system.

Abstract: A method of a flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface includes: using a set-feature signal, which carries a set-feature command, a macro execution feature address, and corresponding macro execution parameter information, as a macro execution signal and transmitting the macro execution signal to the flash memory device to make the flash memory device execute multiple set-feature operations respectively having unique information defined by the corresponding macro execution parameter information carried in the macro execution signal.

Abstract: Systems and methods are disclosed for reducing idle power usage of a storage device. The storage device can include a storage media configured, a data interface configured to connect to the host device, a media controller, and a bridge controller. The bridge controller can be further configured to, in response to receiving an idle status message from the media controller, save state data of the media controller, send a shutdown command to the media controller to stop it from using power. The bridge controller can be further configured to, in response to receiving a read operation or a write operation from the host device, start power to the media controller, provide the media controller with the saved state data, receive data responsive to the read operation or the write operation from the media controller, and transmit the responsive data to the host device.

Abstract: A method of managing operation commands for a flash memory includes: providing a first command queue for receiving and storing a plurality of normal operation commands; providing at least one word line read (IWLR) command queue for receiving and storing a plurality of IWLR operation commands; issuing a lock state command between each two consecutive IWLR operation commands to the at least one second command queue; determining a selected command queue from the first command queue and the at least one IWLR command queues according to the lock state command; and delivering an operation command from the selected command queue to the flash memory.

Abstract: A processing device in a memory system connects a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting includes: for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.

Abstract: A memory system uses error detection codes to detect when errors have occurred in a region of memory. A count of the number of errors is kept and a notification is output in response to the number of errors satisfying a threshold value. The notification is an indication to a host (e.g., a program accessing or managing a machine learning system) that the threshold number of errors have been detected in the region of memory. As long as the number of errors that have been detected in the region of memory remains under the threshold number no notification need be output to the host.

Abstract: Systems and methods are disclosed for enabling a memory sub-system to perform firmware-based monitoring of system state information without adding latency to the memory sub-system. The memory sub-system controller can include multiple CPUs which can be employed to perform different tasks. The memory sub-system controller can employ one of the frontend CPUs as a monitoring CPU capable of executing a data-gathering task to retrieve system state information from another CPU.

Abstract: Upon determining that a reference condition is satisfied, a storage device may determine target memory dies among a plurality of memory dies included in the storage device on the basis of temperatures of the plurality of memory dies, and then write data according to the determination of the target memory dies. For example, the storage device may write data to the target memory dies in an interleaving manner, may write data to a memory die that is not a target memory die only when data is not being written to any other of the plurality of memory dies, or both. The reference condition may relate to a temperature of the storage device.

Abstract: A hyperscale artificial intelligence and machine learning infrastructure includes a plurality of racks, where: at least one or more of the racks include one or more GPU servers; at least one or more of the racks include one or more storage systems; each of the racks include one or more switches coupled to at least one switch in another rack; and the one or more GPU servers are configured to execute one or more artificial intelligence or machine learning applications, wherein data stored within the one or more storage systems is used as input to the one or more artificial intelligence or machine learning applications.