Programmable Read Only Memory (prom, Eeprom, Etc.) Patents (Class 711/103)
  • Patent number: 11144454
    Abstract: Metadata in volatile memory is selectively compressed and destaged to non-volatile storage in the event of an emergency shutdown due to loss of like power. Compression offload hardware that is normally used for data compression is used to compress the metadata, e.g. at line speed. The compressed metadata and any uncompressed metadata that was not selected for compression may be destaged to vault drives along with compressed and uncompressed data that is in the volatile memory. Compression during vaulting may decrease power consumption when operating under standby battery power.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: October 12, 2021
    Assignee: Dell Products L.P.
    Inventors: James Guyer, Jason Duquette
  • Patent number: 11144206
    Abstract: A method and system for sharing data reduction metadata with storage systems. Specifically, the disclosed method and system entail communicating, to a storage system, information known to host devices from which data (submitted to-be-written to the storage system) may originate. This a priori reduction-pertinent information, which may include the potential to improve storage system efficiency and/or performance at least with respect to data reduction processing of the data submitted to-be-written, had previously been considered incommunicable to the storage system. The disclosed method and system, however, lift this previous limitation and enable communication of any storage system performance-improving information, applicable to the data submitted to-be-written, to the storage system.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: October 12, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Jeremy O'Hare, Alexandre Lemay, Matthew Fredette, Sorin Faibish
  • Patent number: 11144453
    Abstract: In some examples, sectors of a solid-state drive are unmapped to initialize the sectors. The sectors include a data portion and a protection portion. When an unmapped sector is read, the solid-state drive can return a pre-set value for the unmapped sector, where the pre-set value includes a known fixed value to represent the protection portion of the unmapped sector. The storage controller is to recognize the known fixed value returned by the solid-state drive responsive to the read as representing the unmapped sector as being initialized, but not written to.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: October 12, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Siamak Nazari, Thomas David Evans, Faris Hindi, Daniel Aaron Harbaugh, Anahita Afkham
  • Patent number: 11144450
    Abstract: Methods, systems, and devices for maintaining sequentiality for media management of a memory sub-system are described. A plurality of read commands in connection with a set of media management operations for a plurality of transfer units are issued according to a read sequence. A plurality of entries associated with the set of media management operations are stored. A plurality of write commands in connection with the set of media management operations are issued based on the plurality of entries of the read sequence.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Antonio David Bianco
  • Patent number: 11144446
    Abstract: The disclosure concerns a flash memory interface having a memory management unit including a comparator configured to determine whether an address of a flash memory access operation corresponds to a logical address or a physical address by comparing the address with one or more address ranges and a logical memory unit configured to convert logical addresses into physical addresses and to provide the physical addresses to the flash memory. The memory management unit is configured to direct physical addresses to the flash memory and to direct logical addresses to the logical memory unit for conversion into physical addresses.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: October 12, 2021
    Assignee: Proton World International N.V.
    Inventors: Youssef Ahssini, Guy Restiau
  • Patent number: 11144210
    Abstract: A valid data merging method, a memory control circuit unit, and a memory storage device are provided. The method includes: obtaining a first system parameter corresponding to a first region and a second system parameter corresponding to a second region; determining whether the first system parameter is greater than the second system parameter; selecting a third physical erasing unit from the second region preferentially and performing a valid data merging operation by using the third physical erasing unit when the first system parameter is greater than the second system parameter; and selecting a fourth physical erasing unit from the first region preferentially and performing the valid data merging operation by using the fourth physical erasing unit when the first system parameter is not greater than the second system parameter.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 12, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11144237
    Abstract: Systems and methods for concurrent reading and writing in shared, persistent byte-addressable non-volatile memory is described herein. One method includes in response to initiating a write sequence to one or more memory elements, checking an identifier memory element to determine whether a write sequence is in progress. In addition, the method includes updating an ingress counter. The method also includes adding process identification associated with a writer node to the identifier memory element. Next, a write operation is performed. After the write operation, an egress counter is incremented and the identifier memory element is reset to an expected value.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: October 12, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Milind M. Chabbi, Yupu Zhang, Haris Volos, Kimberly Keeton
  • Patent number: 11144448
    Abstract: Method for managing flash translation layers (FTL) table updates in response to unmap commands starts with an unmap controller receiving unmap command that comprises a listing of regions in at least one memory component to be unmapped. Unmap controller updates an unmap regions list based on the unmap command. Unmap controller receives a write command to non-volatile memory component. Unmap controller determines, using the unmap regions list, if a write command occurs in a portion of an unmapped region of the non-volatile memory component. In response to determining that write command occurs in the portion of the unmapped region of the non-volatile memory component, unmap controller loads logical-to-physical (L2P) row to volatile memory. L2P row comprises a set of L2P entries mapping the portion of the unmapped region of the non-volatile memory component. Unmap controller then causes the set of L2P entries to be unmapped.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Christian M Gyllenskog
  • Patent number: 11144245
    Abstract: A memory control method is disclosed. The method includes: determining a mode for reading first data in a first management unit as a first mode or a second mode according to a data dispersion degree of the first data; reading the first data from the first management unit according to a physical distribution of the first data if the mode for reading the first data is determined as the first mode; and reading the first data from the first management unit according to a logical distribution of the first data if the mode for reading the first data is determined as the second mode. Furthermore, a memory storage device and a memory control circuit unit are also disclosed.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 12, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Che-Yueh Kuo
  • Patent number: 11139020
    Abstract: A memory controller includes a mapping data controller configured to generate extended mapping data including mapping information and an additional field in response to an extended mapping data request received from a host and to generate data generation information indicating that the extended mapping data has been generated, wherein the mapping information indicates a mapping relationship between a logical block address and a physical block address and a bitmap information generator configured to receive the data generation information and generate bitmap information. The bitmap information may include information for changing a bit value corresponding to a mapping data group including the extended mapping data, among bit values included in a bitmap, to indicate the extended mapping data, and the mapping data group may include a plurality of pieces of mapping data.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventors: Eu Joon Byun, Jea Young Zhang
  • Patent number: 11138109
    Abstract: A method for performing a sudden power-off recovery operation of a controller controlling a memory device, the method includes: obtaining open block information for open blocks of the memory device and read counts for the open blocks; updating each of the read counts by adding a set value to each of the read counts; storing the updated read counts in the memory device; sequentially reading pages in each of the open blocks without updating the read counts for the open blocks, based on the open block information, to detect a boundary page after the storing of the updated read counts in the memory device; and controlling the memory device to program dummy data in the detected boundary page.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: October 5, 2021
    Assignee: SK hynix, Inc.
    Inventor: Jong-Min Lee
  • Patent number: 11139042
    Abstract: Methods, systems, and devices for a capacitor health check are described. A health check manager may detect a trigger for a capacitor health check for a memory sub-system. The health check manager may determine a number of write commands in a set of one or more pending commands for a memory die of the memory sub-system and set a start time for the capacitor health check based on the number of write commands in the set of one or more pending commands. In some cases, the health check manager may perform the capacitor health check in accordance with the start time.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Daniel James Gunderson, Eugene Dvoskin, Vehid Suljic, Brandon R. Nixon
  • Patent number: 11138124
    Abstract: A computer-implemented method, according to one embodiment, includes: determining whether a number of blocks included in a RTU queue associated with a first block pool is in a first predetermined range. In response to determining that the number of blocks included in the RTU queue is not in the first predetermined range, a determination is made as to whether a current I/O workload is in a second predetermined range. In response to determining that the current I/O workload is in the second predetermined range, for each block in the first block pool having a desired amount of metadata associated with the pages in the given block: a subset of pages in the given block are selected and data is relocated therefrom to a block in the second block pool.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: October 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sasa Tomic, Radu Ioan Stoica, Nikolaos Papandreou, Nikolas Ioannou, Roman Alexander Pletka, Aaron Daniel Fry, Timothy Fisher
  • Patent number: 11132291
    Abstract: One embodiment facilitates data storage. During operation, the system receives data to be stored in a non-volatile memory of a storage device. The system determines, by a flash translation layer module of a control unit which is distinct from the storage device, a physical page address at which the data is to be stored in the non-volatile memory, wherein the flash translation layer module of the control unit determines physical page addresses for data to be stored in a plurality of storage devices. The system stores, by the flash translation layer module of the control unit, a mapping between a logical page address for the data and the physical page address. The system writes the data to the non-volatile memory at the physical page address.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: September 28, 2021
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventor: Shu Li
  • Patent number: 11132147
    Abstract: Methods, systems, and devices for performing memory command verification are described. A system may include a memory device and a memory controller, which may be external (e.g., a host device). The memory device may receive, from the memory controller, a command indicating a type of operation and an address. The memory device may decode the command and execute an operation (e.g., the operation corresponding to the decoded command) at an execution location on the memory device. The system (e.g., the memory device or the memory controller) may determine whether the executed operation and execution location match the type of operation and address indicated in the command, and the system may thereby determine an error associated with the decoding, the execution, or both of the command.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Patent number: 11132148
    Abstract: Provided herein is a semiconductor memory device including a memory cell array, a peripheral circuit, an operation information storage, and control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a read operation for setup information stored in the memory cell array. The operation information storage may store the setup information. The control logic may control a read operation of the peripheral circuit and a storage operation of the operation information storage. The control logic may control the peripheral circuit and the operation information storage such that a storage section in which the operation information storage stores first setup information and a read section in which the peripheral circuit reads second setup information from the memory cell array are at least partially overlapped with each other.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: September 28, 2021
    Assignee: SK hynix Inc.
    Inventor: Sung Ho Ahn
  • Patent number: 11132350
    Abstract: In various embodiments, methods and systems for optimizing database transactions based on replicable differential data store data structure are provided. A write operation request, having a key for a write operation on a replicable differential store data structure, is accessed. An intent write lock on a differential state and a write lock on the key are acquired. The differential state comprises a result set of currently committing transactions. A transaction instance, of the write operation, is generated for a write set, the transaction instance comprising a modification to the key. The write-set comprises an uncommitted set of writes for in-flight transactions. A determination is made that the write operation is committed. A result of the transaction instance is persisted when the write operation is committed. It is contemplated that the differential state and a consolidated state can be merged, the consolidated state comprises a result set of previously committed transactions.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: September 28, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mihail Gavril Tarta, Gopal Kakivaya, Preetha Lakshmi Subbarayalu
  • Patent number: 11132141
    Abstract: A system and a method of synchronizing, by a processor, between content of a first data container and content of at least one second data container may include: receiving one or more first data elements of the first data container and one or more second data elements of the at least one second data container; computing one or more first unique reference values (URVs) for the respective one or more first data elements; computing one or more second URVs for the respective one or more second data elements; storing the first data elements on a first storage element; storing the second data elements at a second storage element; comparing between a first URV and a second URV to identify data elements having diverged content; and synchronizing between content of the first data container and content of the at least one second data container based on the comparison.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: September 28, 2021
    Assignee: IONIR SYSTEMS LTD.
    Inventors: Jacob Cherian, Nir Peleg
  • Patent number: 11132298
    Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Raj K. Ramanujan, Rajat Agarwal, Glenn J Hinton
  • Patent number: 11132129
    Abstract: A method, non-transitory computer readable medium, and device that assists with reducing memory fragmentation in solid state devices includes identifying an allocation area within an address range to write data from a cache. Next, the identified allocation area is determined for including previously stored data. The previously stored data is read from the identified allocation area when it is determined that the identified allocation area comprises previously stored data. Next, both the write data from the cache and the read previously stored data are written back into the identified allocation area sequentially through the address range.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 28, 2021
    Assignee: NetApp Inc.
    Inventors: Ravikanth Dronamraju, Shivali Gupta, Kyle Sterling, Atul Goel
  • Patent number: 11133061
    Abstract: An example method includes determining a time between writes in place to a particular memory cell, incrementing a disturb count corresponding to a neighboring memory cell by a particular count increment that is based on the time between the writes to the particular memory cell, and determining whether to check a write disturb status of the neighboring memory cell based on the incremented disturb count.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Edward C. McGlaughlin, Samuel E. Bradshaw
  • Patent number: 11133067
    Abstract: Disclosed are systems and methods for providing multi-phased programming with balanced Gray coding. A method includes programming, in a first phase, a first portion of data into memory cells of a flash memory in a first-level cell mode. The method also includes retaining, in a cache, at least a subset of the data. The method also includes regenerating the data from at least the cache, wherein the regenerated data includes a second portion of the data. The method also includes programming, in a second phase, the regenerated data in a second-level cell mode based on a mapping from the first-level cell mode to the second-level cell mode. The mapping maps each state distribution in the first-level cell mode to at least two non-adjacent state distributions in the second-level cell mode, and a width of each state distribution in the first-level cell mode may be narrowed.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: September 28, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sergey Anatolievich Gorobets, Xinmiao Zhang, James Fitzpatrick
  • Patent number: 11126547
    Abstract: A memory controller includes a central processing unit (CPU) configured to translate a logical address corresponding to an operation that is to be performed by a memory device into a physical address, and an addressing component configured to acquire information about an addressing rule supported by the memory device, among a plurality of addressing rules, and to configure an addressing table corresponding to the operation using the acquired addressing rule information and the physical address.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: September 21, 2021
    Assignee: SK hynix Inc.
    Inventor: Dong Yeob Chun
  • Patent number: 11126366
    Abstract: A data erasing method, a memory control circuit unit and a memory storage device are provided. The method includes selecting a first physical erasing unit group from a plurality of physical erasing unit groups, and performing an erase operation to the first physical erasing unit group, wherein the first physical erasing unit group includes a plurality of first physical erasing units, and the number of at least one second physical erasing unit used to perform the erasing operation at the same time point of the plurality of first physical erasing units is different from the number of the plurality of first physical erasing units.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 21, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11126369
    Abstract: The present disclosure generally relates to efficiently reading data during a suspend resume operation. Once writing is suspended, and prior to reading the data, a determination is made regarding whether there are multiple reads of the same page type. If there are multiple reads of the same page type, those reads are paired up so that the two reads of the same page type can occur from two planes in parallel. If two different pages types are read in parallel on the two planes, the slowest page type will determine the duration of the read. By grouping reads of the same page type and proceeding with the read, the disruption during suspend resume operations is minimized.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: September 21, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Refael Ben-Rubi
  • Patent number: 11126368
    Abstract: A method for finding a last good page in a memory system includes determining a first number of write operations in a first queue at a first page in a memory block of the memory system. The method also includes determining whether the first number of write operations in the first queue is above a threshold. The method also includes based on a determination that the first number of write operations in the first queue is above the threshold, determining whether a second page in the memory block is empty. The method also includes identifying, based on a determination that the second page is empty, the last good page in the memory block using a binary search between the first page and the second page.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 21, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Tomer Eliash, Evgeny Mekhanik, David Rozman, Yair Chasdai
  • Patent number: 11126251
    Abstract: The present disclosure includes apparatuses and methods related to power management in memory. Memory devices with multiple input/output ports may have the ports separately managed to transfer data from the various to a host or other components of the module based on certain power management signaling or constraints. For example, a memory device with multiple ports may be managed to transfer data to a host from one set of ports in response to power management (or other) signaling, and the device may be managed to transfer other data to another memory device in response to different power management (or other signaling). Power management may be done onboard a memory module with or without direction from a host. Power management may be performed by a dedicated integrated circuit. Data may be transferred from or between different classes of memory devices, using different ports, based on power management, e.g., criteria.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Frank F. Ross, Matthew A. Prather
  • Patent number: 11126370
    Abstract: A memory controller for controlling an operation of a memory device includes a request receiving circuit and a data characteristic storage circuit. The request receiving circuit receives from a host a flush request and a logical address corresponding to the flush request, and generates a control signal in response to the received flush request. The data characteristic storage circuit stores a cold data list, and updates the cold data list in response to the control signal from the request receiving circuit.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: September 21, 2021
    Assignee: SK hynix Inc.
    Inventor: Se Hyun Kim
  • Patent number: 11126238
    Abstract: An open channel solid state drive includes a flash memory including a first block and a controller which controls the flash memory, the controller receiving write data and a physical address of the first block from a host and attempting a write of the data in the first block. The controller generates first data which is not written in the first block among the write data when a power-off occurs during writing attempt. The write data includes the first data and second data already written in the first block. The controller determines whether successive writing of the first data in the first block is possible or impossible. If the successive writing is possible, the controller successively writes the data in the first block. If the successive writing is impossible, the host or the controller writes the first data and the second data in a second block of the flash memory.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae Ok Kim, In Hae Kang, Min Seok Ko, Yang Woo Roh, In Hwan Doh, Jong Won Lee, Se Jeong Jang
  • Patent number: 11127468
    Abstract: Some embodiments include a method for addressing an integrated circuit for a non-volatile memory of the EEPROM type on a bus of the I2C type. The memory includes J hardware-identification pins, with J being an integer lying between 1 and 3, which are assigned respective potentials defining an assignment code on J bits. The method includes a first mode of addressing used selectively when the assignment code is equal to a fixed reference code on J bits, and a second mode of addressing used selectively when the assignment code is different from the reference code. In the first mode, the memory plane of the non-volatile memory is addressed by a memory address contained in the last low-order bits of the slave address and in the first N bytes received. In the second mode, the memory plane is addressed by a memory address contained in the first N+1 bytes received.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 21, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Marc Battista
  • Patent number: 11126568
    Abstract: Examples may include techniques to enable cache coherency of objects in a distributed shared memory (DSM) system, even where multiple nodes in the system manage the objects. Node memory space includes a tracking address space (TAS) where lines in the TAS correspond to objects in the (DSM). Access to the objects and the TAS is managed by a host fabric interface (HFI) caching agent in HFI of a node.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 21, 2021
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Robert G. Blankenship, Raj K. Ramanujan
  • Patent number: 11126550
    Abstract: Disclosed is a monolithic integrated circuit (IC) computing device with multiple independent process cores (multicore) and embedded, non-volatile resistive memory serving as system memory. The resistive system memory is fabricated above the substrate, and logic circuits embodying the process cores are fabricated on the substrate. In addition, access circuitry for operating on the resistive system memory, and circuitry embodying memory controllers, routing devices and other logic components is provided at least in part on the substrate. Large main memory capacities of tens or hundreds of gigabytes (GB) are provided and operable with many process cores, all on a single die. This monolithic integration provides close physical proximity between the process cores and main memory, facilitating significant memory parallelism, reduced power consumption, and eliminating off-chip main memory access requests.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: September 21, 2021
    Assignee: Crossbar, Inc
    Inventors: Donald Yeung, Bruce L. Jacob, Mehdi Asnaashari, Sylvain Dubois
  • Patent number: 11126567
    Abstract: Network protocols generally implement integrity protection, encryption and authentication as separate validation steps. Since each validation step contributes encoding and processing overhead associated with individual packet transfers over the network, such network protocols can make inefficient use of limited packet space. Systems and methods according to the present disclosure combine integrity protection, encryption and authentication into a single validation step thereby making efficient use of limited packet space.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: September 21, 2021
    Assignee: Google LLC
    Inventors: Daniel Earle Gibson, Monica C. Wong-Chan, Milo Martin
  • Patent number: 11126558
    Abstract: A high-performance data storage device is disclosed. A controller updates a sub mapping table on the temporary storage in response to a write command of the non-volatile memory issued by a host. The mapping sub-table corresponds to a logical group involved in the write command and is downloaded from the non-volatile memory. When the mapping sub-table has not been completely downloaded to the temporary storage memory, the controller pushes the write command to a waiting queue to avoid dragging the performance of the data storage device.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: September 21, 2021
    Assignee: SILICON MOTION, INC.
    Inventors: Wei-Lin Kao, Yang-Chih Shen, Jian-Yu Chen
  • Patent number: 11119934
    Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device includes a memory controller having a map manager and preload mapping information storage, and a memory device having logical-to-physical mapping information. The memory controller determines and obtains from the memory device, preloads mapping information, and then stores the preload mapping information in the preload mapping information storage, before a map update operation of the logical-to-physical mapping information is performed. The preload mapping information includes logical-to-physical mapping information to be updated.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: September 14, 2021
    Assignee: SK hynix Inc.
    Inventors: Byeong Gyu Park, Sung Hun Jeon, Young Ick Cho, Seung Gu Ji
  • Patent number: 11119954
    Abstract: Technology is described herein that provides a memory device configured to receive first memory access requests from a host system on a host connection while the non-volatile memory device is in a first mode. The first memory access requests to allow the host system to access the non-volatile memory cells in accordance with a memory access protocol. The memory device is configured to initiate second memory access requests internally in accordance with the memory access protocol while the non-volatile memory device is in a second mode. The memory device is configured to implement a memory controller side of the memory access protocol to respond to the first memory access requests while the non-volatile memory device is in the first mode and to respond to the second memory access requests while the non-volatile memory device is in the second mode.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: September 14, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 11119699
    Abstract: A data processing system includes a host suitable for generating a candidate logical block address (LBA) list including a plurality of candidate LBAs, a memory device suitable for storing a plurality of map segments and user data corresponding to the respective map segments, and a controller suitable for receiving the candidate LBA list from the host, and loading target map segments from the memory device, the target map segments corresponding to the plurality of candidate LBAs.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 14, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 11119680
    Abstract: A data writing method of a flash disk array is provided. The data writing method includes steps of: obtaining a first data quantity; receiving intermediate data to be written into the flash disk array; comparing a second data quantity of the intermediate data with the first data quantity; and writing the intermediate data into the flash disk array when the second data quantity is not less than the first data quantity. At most one data block is allocated from each of flash drives. Some of the allocated data blocks are written with the intermediate data, while others of the allocated data blocks are not written with the intermediate data and provided as reserved blocks. The number of the reserved blocks has at least two selectable values dependent on residual lives of the flash drives.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: September 14, 2021
    Assignee: QNAP SYSTEMS, INC.
    Inventor: Chin-Hsing Hsu
  • Patent number: 11119855
    Abstract: A computer-implemented method, according to one embodiment, is for selectively storing parity data in different types of memory which include a higher performance memory and a lower performance memory. The computer-implemented method includes: receiving a write request, and determining whether the write request includes parity data. In response to determining that the write request includes parity data, a determination is made as to whether a write heat of the parity data is in a predetermined range. In response to determining that that write heat of the parity data is in the predetermined range, another determination is made as to whether the parity data has been read since a last time the parity data was updated. Furthermore, in response to determining that the parity data has been read since a last time the parity data was updated, the parity data is stored in the higher performance memory.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nikolas Ioannou, Timothy Fisher, Roman Alexander Pletka, Nikolaos Papandreou, Radu Ioan Stoica, Sasa Tomic, Aaron Daniel Fry
  • Patent number: 11119658
    Abstract: A memory sub-system includes a memory sub-system controller comprising at least one host channel, a memory device comprising a plurality of memory die, and at least one input/output (I/O) expander circuit coupled to the at least one host channel of the memory sub-system controller and to the memory device. The at least one I/O expander circuit includes one or more I/O buffers to send and receive signals on the at least one host channel, a selection circuit coupled to the one or more I/O buffers, and command processing logic to enable the selection circuit to route the signals on a selected one of a plurality of expansion channels coupled to the at least one I/O expander circuit. Each of the plurality of expansion channels is coupled to a corresponding subset of the plurality of memory die.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Edward McGlaughlin
  • Patent number: 11119659
    Abstract: A memory device comprises a memory array including memory cells programmable as single level memory cells (SLCs) and memory cells programmable as triple level memory cells (TLCs); a memory control unit operatively coupled to the memory array and including a processor, the processor configured to program the memory cells with SLC data and TLC data; and a write buffer to buffer data for writing to the memory array, the write buffer including both SLC data memory space and TLC data memory space, wherein the memory control unit is configured to store TLC data in the SLC data memory space when there is overflow of the TLC data memory space.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Giuseppe Cariello
  • Patent number: 11119946
    Abstract: Methods, systems, and devices for codeword rotation for zone grouping of media codewords are described. A value of a first pointer may be configured to correspond to a first memory address within a region of memory and a value of a second pointer may be configured to correspond to a second memory address within the region of memory. The method may include monitoring access commands for performing access operations within the region of memory, where the plurality of access command may be associated with requested addresses within the region of memory. The method may include updating the value of the second pointer bases on a quantity of the commands that are monitored satisfying a threshold and executing the plurality of commands on locations within the region of memory. The locations may be based on the requested address, the value of the first pointer, and the value of the second pointer.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Joseph Thomas Pawlowski
  • Patent number: 11119915
    Abstract: A method to map a plurality of feature maps of a neural network onto a memory hierarchy includes mapping a first feature map of the plurality of feature maps to a memory in a memory hierarchy having available memory space and providing quickest access to the first feature map. The method also includes, when the first feature map expires, removing the first feature map from the memory used to store the first feature map.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: September 14, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chenchi Luo, Hyejung Kim, Seok-Jun Lee, David Liu, Michael Polley
  • Patent number: 11119909
    Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: September 14, 2021
    Assignee: Texas Instmments Incorporated
    Inventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Samuel Paul Visalli
  • Patent number: 11119950
    Abstract: A memory controller may control a memory device, which includes two or more planes each including a plurality of memory blocks, which are capable of being simultaneously operated, wherein each of two or more memory blocks in different planes, among the two or more planes, stores a plurality of data chunks. The memory controller may include a data map generator configured to generate a data map indicating locations of stored valid data chunks, among the plurality of data chunks, a read sequence determinator configured to determine a read sequence in which the valid data chunks are to be read based on the data map, and a command input controller configured to provide a read command for the valid data chunks to the memory device based on the read sequence.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: September 14, 2021
    Assignee: SK hynix Inc.
    Inventor: Gi Pyo Um
  • Patent number: 11112974
    Abstract: Technologies are provided for dynamically changing a size of a cache region of a storage device. A storage device controller writes data to the cache region of the storage device using a particular storage format. The storage device controller then migrates the cached data to a storage region of the device, where the data is written using a different storage format. A dynamic cache manager monitors input and output activity for the storage device and dynamically adjusts a size of the cache region to adapt to changes in the input and/or output activity. The dynamic cache manager can also adjust a size of the storage region. The storage device controller can automatically detect that the storage device has dynamic cache support and configure the storage device by creating the cache region and the storage region on the device.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: September 7, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Munif M. Farhan, Phyllis Ng, Darin Lee Frink, Nafea Bshara
  • Patent number: 11112990
    Abstract: Managing storage device evacuation that includes a plurality of storage devices, including: detecting, by the storage system, an occurrence of a storage device evacuation event associated with a source storage device within a write group, wherein the write group is a subset of storage devices storing a data set; responsive to detecting the occurrence of the storage device evacuation event, identifying, by the storage system, a target storage device for receiving data stored on the source storage device; and migrating, by the storage system, the data stored on the source storage device to the target storage device.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: September 7, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Andrew Bernat, John Colgrove, Taher Vohra, Andrew Kleinerman, Xiaohui Wang, Benjamin Scholbrock
  • Patent number: 11113159
    Abstract: An embodiment of a memory apparatus may include a logger to log memory access data in persistent storage media, a log indexer communicatively coupled to the logger to index the memory access log data in an index table in a system memory, and a key compressor communicatively coupled to the log indexer to compress an index key for the index table. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Zhiyuan Zhang, Xiangbin Wu, Xinxin Zhang, Qianying Zhu, Haitao Ji, Yingzhe Shen
  • Patent number: 11112976
    Abstract: A data storage device includes a non-volatile memory, including a first region and a second region different from the first region, and a controller which stores first and second data in a first region of the non-volatile memory. The first region of the non-volatile memory includes first and second storage regions. A part of the first data is stored in the first storage region, and another part of the first data is stored in the second storage region. The second data is stored in the second storage region, and an offset value of the second storage region in which the second data is started is stored in the second region of the non-volatile memory.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: September 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung Chul Jang, Jae Ju Kim, Young-Ho Park, Chan Soo Kim, Ju Pyung Lee
  • Patent number: 11113189
    Abstract: Provided herein is a memory system and a method of operating the same. According to the present technology, a memory system performs a garbage collection operation based on a ratio of a read count value of a memory block with reference to a read count threshold value of a read reclaim operation. Consequently, the read reclaim operation and the garbage collection operation may be prevented from overlapping with each other.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: September 7, 2021
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun