Programmable Read Only Memory (prom, Eeprom, Etc.) Patents (Class 711/103)
  • Patent number: 10811089
    Abstract: Apparatuses, systems, and methods are disclosed for adjusting a programming setting such as a programming voltage of a set of non-volatile storage cells, such as an SLC NAND array. The non-volatile storage cells may be arranged into a plurality of word lines. A subset of the non-volatile storage cells may be configured to store a programming setting. An on-die controller may be configured to read the programming setting from the setting subset, and write data to the non-volatile storage cells, using the programming setting. The on-die controller may further be configured to determine that the programming setting causes suboptimal programming of one or more of the non-volatile storage cells, and in response to the determination, store a revised programming setting on the setting subset.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: October 20, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • Patent number: 10811104
    Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: October 20, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 10810128
    Abstract: The present disclosure relates to caches, methods, and systems for using an invalidation data area. The cache can include a journal configured for tracking data blocks, and an invalidation data area configured for tracking invalidated data blocks associated with the data blocks tracked in the journal. The invalidation data area can be on a separate cache region from the journal. A method for invalidating a cache block can include determining a journal block tracking a memory address associated with a received write operation. The method can also include determining a mapped journal block based on the journal block and on an invalidation record. The method can also include determining whether write operations are outstanding. If so, the method can include aggregating the outstanding write operations and performing a single write operation based on the aggregated write operations.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: October 20, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Pulkit Misra
  • Patent number: 10811112
    Abstract: Apparatuses, systems, and methods are disclosed for wear leveling for non-volatile memory. An apparatus may include one or more non-volatile memory elements, and a controller. A controller may perform a wear-leveling process for one or more non-volatile memory elements, by periodically updating a logical-to-physical mapping and moving data based on the updated mapping. A controller may detect a wear-based attack for one or more non-volatile memory elements. A controller may change a wear-leveling process in response to detecting a wear-based attack.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: October 20, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Daniel Helmick, Amir Gholamipour, James Fitzpatrick
  • Patent number: 10810132
    Abstract: Logical to physical mapping of managed units (“MUs”) of object data in a flash memory system storing MUs that are being created continuously by applications running on a client system is maintained in an extent based tree in DRAM for extents of contiguous MUs and in an override tree in DRAM for individual MUs. Extent mapping data in the extent tree for extents comprises a starting address and a length. Mapping data for individual MUs in the override tree comprises individual pointers from logical addresses to physical addresses. Source erase blocks in flash memory are reorganized asynchronously by iteratively moving individual MUs of an object in order from a source erase block to a free erase block to empty the source erase block and free up associated DRAM.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: October 20, 2020
    Assignee: EMC IP Holding Company, LLC
    Inventor: Richard H. Van Gaasbeck
  • Patent number: 10802959
    Abstract: A storage device for performing a garbage collection operation using a partial block erase operation includes: a memory device including a plurality of main blocks each including a plurality of sub-blocks; and a memory controller configured to perform a garbage collection operation for securing free blocks in which no data is stored, among the main blocks, wherein the memory controller includes a write handler configured to erase at least a portion of a target block, among the main blocks, according to whether an amount of valid data in at least one victim block exceeds a storage capacity of one main block.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: October 13, 2020
    Assignee: SK hynix Inc.
    Inventor: Byoung Sung You
  • Patent number: 10805422
    Abstract: A memory device includes a memory array including a first communication circuit element configured to communicate a first signal between components in the memory device; a second communication circuit element configured to communicate a second signal between the components in the memory device; and a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between: operating the first communication circuit element and the second communication circuit element independent of each other, where in the first signal and the second signal are independent signals, and operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matthew D. Rowley, Mark Bauer
  • Patent number: 10803063
    Abstract: In a distributed database, an inner join of very large data sets is performed by distributing smaller jobs to a plurality of computing devices. For each key, values in a first input are partitioned into a first set block set, and values in a second input are partitioned into a second block set. For each key, the first block set is replicated by a number of blocks in the second block set, and the second block set is replicated by a number of blocks in the first block set. Each replicated block is assigned a block-key including the key and additional information to identify the replicated block. Each pair of replicated blocks having matching block-keys are distributed to one of a plurality of computing devices. Results for the inner join are received from the plurality of computing devices.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 13, 2020
    Assignee: Google LLC
    Inventor: Yaacov Dar
  • Patent number: 10803960
    Abstract: A method for operating a memory device includes: receiving a program command, a memory address, and a program data from a controller; performing a first temperature sensing operation for measuring an internal temperature to produce a first result of the first temperature sensing operation; performing a program operation on the program data based on the first result of the first temperature sensing operation; performing a second temperature sensing operation for measuring an internal temperature to produce a first result of the second temperature sensing operation; and performing a temperature comparison operation for deciding whether the program operation failed when a difference between the first result of the first temperature sensing operation and the first result of the second temperature sensing operation is greater than or equal to a threshold value.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: October 13, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyun-Woo Lee
  • Patent number: 10802748
    Abstract: Disclosed herein is a persistent memory (PMEM)-based distributed memory object system, referred to as the PMEM DMO system, that provides affordable means of integrating low-latency PMEM spaces with other devices, including servers that do not directly support PMEM. One embodiment comprises providing a cluster of servers with PMEM storage (PMEM servers) and connecting the PMEM servers to a plurality of applications servers using a low-latency network, such as a remote direct memory access; background processes on each of the application servers are tasked to perform input/output operations for the application servers to locally materialize objects from and synchronize/persist objects to the remote PMEM spaces on the PMEM servers. Data materialized from the PMEM servers is stored to the local cache of the application server for use. Also disclosed are data eviction policies for clearing the local cache of the application servers to make space for new data read.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: October 13, 2020
    Inventors: Yue Zhao, Wei Kang, Yue Li, Jie Yu
  • Patent number: 10803930
    Abstract: According to one embodiment, a memory system comprising includes a semiconductor memory and a memory controller. The memory controller is configured to obtain first data read from the semiconductor memory using a first voltage, obtain second data read from the semiconductor memory using a second voltage, calculate a first value for a first section of the first data using the first data and the second data, calculate a second value for a second section of the first data using the first data and the second data, calculate a third value for a third section of the first data using the first data and the second data, and correct an error of the first data using the first to third values.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masahiro Kiyooka, Yoshihisa Kojima, Toshikatsu Hida
  • Patent number: 10802976
    Abstract: Provided herein may be a storage device configured to perform a cache read operation by each memory device. The storage device may include a plurality of memory devices each including a plurality of memory blocks, and a memory controller configured to store and set cache setting information for each of the plurality of memory device, and control the plurality of memory devices such that, as a read operation on a select one of the plurality of memory devices, one of a cache read operation and a normal read operation is performed based on the cache setting information set for of the select memory device.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: October 13, 2020
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 10802960
    Abstract: A flash medium access method, including selecting, by a controller, a target function queue from N function queues according to a predefined rule, where the target function queue is a non-empty queue, a flash medium in which a die associated with the target function queue is located is in an idle state, obtaining a basic instruction from the target function queue, determining, according to preset queue mapping information, the die associated with the target function queue, where the controller is connected to at least one flash medium, and the queue mapping information indicates that the N function queues are in a one-to-one mapping relationship with the N dies, generating, according to a preset signal generation rule, a time sequence signal corresponding to the basic instruction, and sending the time sequence signal to the flash medium in which the associated die is located.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: October 13, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Tao Li, Guanfeng Zhou, Sheng Li
  • Patent number: 10802720
    Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: October 13, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Chin-Pang Chang, Chun-Yi Lo
  • Patent number: 10802733
    Abstract: The present disclosure, in various aspects, describes technologies and techniques for use by a non-volatile memory (NVM) controller to provide multiple data storage tiers in a solid state drive (SSD). In an illustrative example, the NVM controller receives information from a host device for partitioning the NVM device into multiple data storage tiers, and configures one or more memory blocks in the NVM device based on the information to provide the multiple data storage tiers where each comprises data storage cells configured to store a different number of bits relative to other data storage cells of the multiple data storage tiers. For example, each of the multiple data storage tiers in the SSD may be configured to store a different type of data, such as “hot data”, “warm data”, or “cold data.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 13, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Rajiv Madabhushi
  • Patent number: 10802734
    Abstract: The disclosure relates to optimizing a mount process at a data storage device. The storage device communicates with a host using a mount process and mounts a master table, the master table caching translation table pointers associated with a boot partition. The storage device then sends a ready signal to the host indicating that the storage device is ready to receive a boot partition read command from the host. The storage device suspends the mount process for a window of time to receive the boot partition read command and executes the boot partition read command if the boot partition read command is received during the window of time. Accordingly, by caching boot partition pointers in the master table, the mount time of the boot partition is shortened to allow the storage device to send the ready signal earlier and provide the host with earlier access to the boot partition.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 13, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Shaharabany, Ivo Faldini, Arseniy Aharonov, Miki Sapir
  • Patent number: 10795586
    Abstract: One embodiment facilitates global data placement in a storage device. The system receives a request to write first data. The system selects one of a plurality of physical media of the storage device to which to directly write the first data, based on a frequency of access, a block size, and a latency requirement of the first data, wherein the plurality of physical media includes a fast cache medium, a solid state drive, and a hard disk drive. In response to determining that the frequency of access of the first data is greater than a predetermined threshold, or in response to determining that the block size associated with the first data is not greater than a predetermined size and determining that the first data is an update to existing data, the system selects the fast cache medium. The system writes the first data to the selected one physical medium.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 6, 2020
    Assignee: Alibaba Group Holding Limited
    Inventors: Shu Li, Ping Zhou
  • Patent number: 10795828
    Abstract: A computer device reads an indicator from a configuration file that identifies a granularity of units of data at which to track validity. The granularity is one of a plurality of granularities ranging from one unit of data to many units of data. The computer device generates a machine-readable file configured to cause a processing device of a memory system to track validity at the identified granularity using a plurality of data validity counters with each data validity counter in the plurality of data validity counters tracking validity of a group of units of data at the identified granularity. The computer device transfers the machine-readable file to a memory of the memory system.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: October 6, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Boon Leong Yeap, Karl D. Schuh
  • Patent number: 10798108
    Abstract: A method and a system embodying the method for a multi-entity secure software transfer are disclosed, the method operating by: configuring a communication interface controller at each trusted hardware entity of a first hardware entity and a second hardware entity to disallow all external access except a communication link configuration access; establishing the communication link between the first hardware entity and the second hardware entity; configuring write access from the second hardware entity to only a first storage at the first hardware entity; and writing the secure software received from the second hardware entity via the communication link to the first storage at the first hardware entity.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: October 6, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: Wilson Parkhurst Snyder, II
  • Patent number: 10795835
    Abstract: A storage device and an interface chip thereof are provided, wherein the interface chip can be applied to the storage device. The interface chip comprises a slave interface circuit, a master interface circuit, and a control circuit. The storage device comprises a memory controller and a non-volatile (NV) memory, and the NV memory comprises a plurality of NV memory chips. The slave interface circuit is arranged for coupling the interface chip to the memory controller. The master interface circuit is arranged for coupling the interface chip to a set of NV memory chips within the plurality of NV memory chips. A hierarchical architecture in the storage device comprises the memory controller, the interface chip, and the set of NV memory chips. The control circuit is arranged for controlling operations of the interface chip.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: October 6, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 10796026
    Abstract: A data storage system comprising: a detachable data storage device; an alarm device; where the alarm device is connected to the detachable data storage device and where the alarm device is configured to initiate an alarm event if the alarm device is sufficiently far away from the detachable data storage device.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: October 6, 2020
    Assignee: Wildfi Proprietary Limited
    Inventor: Mark Rodney Anson
  • Patent number: 10795810
    Abstract: A wear-leveling process for a memory subsystem selects a source chunk to be removed from a usable address space of the memory subsystem to distribute wear across all available chunks in the memory subsystem. The memory subsystem has a plurality of non-volatile memory components. The plurality of non-volatile memory components includes a plurality of chunks including at least one chunk in an unusable address space of the memory subsystem. The wear-leveling process copies valid data of the source chunk to a destination chunk in the unusable address space of the memory subsystem and assigns the destination chunk to a location in the usable address space of the memory subsystem occupied by the source chunk.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 6, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Samuel E. Bradshaw, Justin Eno
  • Patent number: 10795589
    Abstract: A memory system includes a nonvolatile memory device and a controller circuit. The nonvolatile memory device includes a plurality of physical blocks, each including a storage area which is accessible in units of pages. The controller circuit is configured to control reading and writing of data which are performed on the plurality of physical blocks in units of pages. The controller circuit is also configured to execute a first process on the plurality of physical blocks by performing a second process of reading and a third process of data verification on a first page across each of the plurality of physical blocks and then performing the second process of reading and the third process of data verification on a second page across each of the plurality of physical blocks.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 6, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takahiro Masakawa
  • Patent number: 10795811
    Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element including a plurality of physical blocks includes: obtaining a first host address and first data from a received first access command; obtaining a second host address and second data from a received second access command; linking the first host address to at least a first page of the physical block and linking the second host address to at least a second page of the physical block; storing the first data and second data into the physical block; and selectively erasing a portion of the physical block according to a valid/invalid page count of the physical block, the valid/invalid page count corresponding to accessing pages of the physical block. A difference value of the first host address and the second host address is greater than a number of pages of the physical block.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: October 6, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Tsai-Cheng Lin, Chun-Kun Lee
  • Patent number: 10795827
    Abstract: Storage devices that can perform adaptive management of intermediate storage memory, and methods for use therewith, are described herein. Such a storage device includes non-volatile memory, wherein a portion thereof is designated as intermediate storage (IS) memory and another portion thereof designated as main storage (MS) memory. The IS memory has lower write and read latencies, greater endurance, and lower storage density and capacity than the MS memory. In certain embodiments, a host activity pattern is predicted, a relocation schemes is selected based on the predicted host activity pattern, and the selected relocation scheme is executed to thereby selectively relocate one or more portions of the data from the IS memory to the MS memory in accordance with the selected relocation scheme. The relocation scheme that is selected and executed can change over time. Additionally relocation schemes can be generated based on activity log(s) and thereafter selected for execution.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: October 6, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Judah Gamliel Hahn, Alexander Bazarsky, Shay Benisty, Ariel Navon
  • Patent number: 10789011
    Abstract: Embodiments described herein provide a system for facilitating performance enhancement of a storage device. During operation, the system obtains a write request for storing a data page in the storage device. The system then stores the page in a non-volatile accumulation buffer integrated with the storage device and determines whether the accumulation buffer has accumulated at least one block of data. The block of data can indicate a unit of an erasure operation on the storage device. If the accumulation buffer has accumulated the one block of data, the system transfers the block of data to a first block in the storage device from the accumulation buffer.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: September 29, 2020
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 10790026
    Abstract: A non-volatile memory device includes a non-volatile memory cell array, an input/output pad unit, and a peripheral circuit. The non-volatile memory device executes an operation requested by a controller. The input/output pad component provides a path through which a command and data related to the operation requested by the controller are input to the non-volatile memory device, and through which a result of execution of the requested operation is output to the controller. The peripheral circuit is configured to be loaded with a plurality of commands provided by the controller, to temporarily store program data provided by the controller to be written in the non-volatile memory cell array and data read from the non-volatile memory cell array, to adjust an execution order of the commands asynchronously with the controller based on an internal operation status of the non-volatile memory device, and to execute the commands in the adjusted execution order.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: September 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Il-Su Han, Sung-Joon Kim, Jong-Hwa Kim, Da-Hee Jeong
  • Patent number: 10789164
    Abstract: A memory system includes: a memory device including a closed memory block; an update block detector detecting a total sum of valid page decrease amounts and the number of update blocks based on the number of valid pages of the closed memory block that are counted before and after a map update operation; and a garbage collector performing a garbage collection operation on a victim block, based on the number of free blocks in the memory device, the counted number of the update blocks and the calculated total sum of the valid page decrease amounts.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyeong-Ju Na, Jong-Min Lee
  • Patent number: 10789167
    Abstract: According to one embodiment, an information processing apparatus stores first data to be written to one destination block of a nonvolatile memory in a write buffer on a memory of the information processing apparatus. The information processing apparatus transmits, to a storage device, a write request including a first identifier associated with the one write destination block and storage location information indicating a location in the write buffer in which the first data is stored. The information processing apparatus transfers the first data from the write buffer to the storage device every time a transfer request including the storage location information is received from the storage device.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: September 29, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 10790035
    Abstract: Disclosed is a method of operating a storage device including a NAND flash memory including memory cells grouped into blocks, each block being divided into pages. According to the method, a controller in the storage device loads, onto a memory region, a look-up table containing first read reference voltage sets corresponding to respective retention degradation stages of the NAND flash memory and second read reference voltages sets corresponding to respective pages which vary in terms of the threshold voltages. Subsequently, the controller performs a read operation on the memory cells on a per-block basis by using the first read reference voltage set corresponding to a current retention degradation stage, the second read reference voltage set corresponding to a current page, or both, until all of the memory cells in a current block are correctly read.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 29, 2020
    Assignees: ESSENCORE LIMITED
    Inventors: Young Joon Choi, Seok Cheon Kwon
  • Patent number: 10789160
    Abstract: A method of operating a storage device which includes a non-volatile memory including a normal unit configured to store normal data and a swap unit configured to store swap data and a controller configured to control the non-volatile memory is provided. The method includes receiving the swap data and a unit selection signal for selecting the swap unit from a host; and processing the swap data according to a data processing policy of the swap unit and writing the processed swap data to the swap unit. The data processing policy of the swap unit may be different from a data processing policy of the normal unit.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: September 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Yong Seo, Kyung Ho Kim, Seung Uk Shin, Yeong Jae Woo, Hyun Ju Kim, Jeong Hoon Cho
  • Patent number: 10789134
    Abstract: A technique restores a file system of a storage input/output (I/O) stack to a deterministic point-in-time state in the event of failure (loss) of non-volatile random access memory (NVRAM) of a node. The technique enables restoration of the file system to a safepoint stored on storage devices, such solid state drives (SSD), of the node with minimum data and metadata loss. The safepoint is a point-in-time during execution of I/O requests (e.g., write operations) at which data and related metadata of the write operations prior to the point-in-time are safely persisted on SSD such that the metadata relating to an image of the file system on SSD (on-disk) is consistent and complete. Upon reboot after NVRAM loss, the technique identifies (i) the most recent safepoint, as well as (ii) the inflight writes that were persistently stored on disk after the most recent safepoint. The data and metadata of those inflight writes are then deleted to place the on-disk file system to its state at the most recent safepoint.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: September 29, 2020
    Assignee: NetApp, Inc.
    Inventors: Ling Zheng, Jeffrey S. Kimmel
  • Patent number: 10782910
    Abstract: The invention introduces a method for internal data movements of a flash memory device, performed by a host, at least including the following steps: generating an internal movement command when detecting that a usage-status for an I/O channel of a solid state disk (SSD) has met a condition; and providing the internal movement command to direct the SSD to perform an internal data-movement operation in the designated I/O channel.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: September 22, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Sheng-Liu Lin
  • Patent number: 10782919
    Abstract: A command processing method and a storage controller are provided. The command processing method includes performing a command merging process on commands sequentially received by a command queue. The command merging process includes an initialization step and multiple iterations. The initialization step includes transmitting the commands from the command queue to a continuity checking pool (CCP), transmitting an initial command of the commands from the CCP to a continuity list (CL) and setting a range of the CL. Each of the iterations includes transmitting the commands from the command queue to the CCP; determining whether the commands in the CCP and the range of the CL conform to a continuity condition; and when the commands in the CCP and the range conform to the continuity condition, appending the first command to the CL and resetting the range of the CL according to the first command.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: September 22, 2020
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Ke-Wei Chan, Di-Hsien Ngu, Hung-Chih Hsieh
  • Patent number: 10782901
    Abstract: A method for performing initialization in a memory device, the associated memory device and the controller thereof, and an associated electronic device are provided. The method may include: after a non-volatile (NV) memory within the memory device is powered on, searching for an empty-memory indicator in the NV memory, wherein the empty-memory indicator is applicable to determining whether the NV memory is empty; and according to whether the empty-memory indicator is found or not, selectively skipping or performing a program code search in the NV memory, to complete an initialization process, wherein the initialization process includes at least one initial setting of the memory device, and if the empty-memory indicator is found, the program code search is skipped, otherwise, the program code search is performed.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: September 22, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Po-Wei Wu
  • Patent number: 10783072
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
  • Patent number: 10783074
    Abstract: A controller includes a memory device storing data and including a memory interface a processor; and a memory, wherein, when data is stored in all pages of an open block of a memory device, the processor determines a number of valid pages in the open block and performs a garbage collection on the open block when the number of valid page(s) is determined to be less than or equal to a threshold value, wherein the number ranges from zero to the total number of pages in the open block.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: September 22, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyeong-Ju Na
  • Patent number: 10783069
    Abstract: A data storage device utilized for storing a plurality of data, wherein the data storage device includes a memory and a controller. The memory includes a plurality of blocks, and each of the blocks includes a plurality of physical pages. The controller is coupled to the memory and maps the logical pages to the physical pages of the memory, and it performs a leaping linear search for the logical pages. The controller searches the Nth logical page of the logical pages according to a predetermined value N. N is a positive integer greater than 1. When the Nth logical page is a currently-used logical page, the controller incrementally decreases the predetermined value N to keep searching the logical pages until a non-currently-used logical page is detected.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: September 22, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Chiu-Han Chang
  • Patent number: 10782895
    Abstract: A metadata management method for a memory device includes generating a virtual address layer in a memory space of a non-volatile memory of the memory device; establishing a mapping table in the virtual address layer to store at least one metadata corresponding to at least one storing block, wherein the at least one storing block comprises at least one physical address and the at least one physical address is related to the memory space; when writing at least one datum to the memory device, writing the at least one datum to at least one memory block of the memory space according to the at least one physical address; and updating the at least one metadata of the at least one storing block when finishing writing the at least one datum.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: September 22, 2020
    Assignee: Wiwynn Corporation
    Inventors: Cheng-Kuang Hsieh, Chia-Hao Hsu
  • Patent number: 10783970
    Abstract: A method for performing a write operation in a random access memory (RAM) includes selecting a target block in a RAM with a greatest number of invalid pages, reading valid pages from target block, when a number of invalid pages is greater than a predetermined threshold, performing a bitline-wise block erase of the target block in said RAM, and copying-back valid data to the erased target block in a row-by-row set operation, wherein the erased target block is written with the valid data. Performing the bitline-wise block erase includes sequentially powering on each bitline with a predetermined reset voltage where all other bitlines and wordlines are grounded.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: September 22, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Amit Berman, Ariel Doubchak, Noam Livne
  • Patent number: 10785231
    Abstract: A validation-ready preprocessing block in a current consensus round is obtained by a blockchain node and in a service consensus stage. The validation-ready preprocessing block is validated. If it is determined that the validation-ready preprocessing block is validated, validation is started on a next validation-ready preprocessing block and parallel data processing is performed on service data stored in the validated validation-ready preprocessing block.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: September 22, 2020
    Assignee: Alibaba Group Holding Limited
    Inventor: Shifeng Wang
  • Patent number: 10785041
    Abstract: A method for providing a space puzzle includes computing, by a puzzle generating entity (PGE), a master secret key (MSK), a public key (PK), a random predicate (RP), and a secret key (SK) using the computed MSK and the computed RP; providing, by the PGE, a challenge comprising the PK and the SK to a proving computing entity; computing, by the proving computing entity, a response to the challenge using a size of the RP by computing a higher dimensional virtual structure; encrypting each row of the higher dimensional structure with the PK; decrypting the encrypted rows using the SK to obtain a decrypted predicate; recomputing the RP using the decrypted predicate and the higher dimensional virtual structure to provide a recomputed random predicate; and verifying the provided challenge by comparing the recomputed random predicate with the RP.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: September 22, 2020
    Assignee: NEC CORPORATION
    Inventors: Sebastian Gajek, Ghassan Karame
  • Patent number: 10776315
    Abstract: Storing data is disclosed, including: creating a clone of a snapshot comprising a first set of metadata associated with a source data, at least in part by generating for the clone a second set of metadata that includes an active index that is associated with the snapshot and is configured to store metadata associated with data values that are written to the clone; receiving a write operation to write a requested data value to the clone; and in response to the write operation, updating the active index based at least in part on the requested data value.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: September 15, 2020
    Assignee: Tintri by DDN, Inc.
    Inventors: Raj Ashok Sudarsanam, Pratap V. Singh, Edward K. Lee, Mark G. Gritter, Rose F. Liu
  • Patent number: 10777271
    Abstract: In one embodiment, an apparatus comprises a first memory array comprising a plurality of phase change memory (PCM) cells; and a controller to track a first cycle count metric based at least in part on a number of writes performed to at least a portion of the first memory array; and adjust, based on the first cycle count metric, a demarcation voltage to be applied during read operations performed on PCM cells of the first memory array.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Wei Fang, Prashant S. Damle, Nevil N. Gajera
  • Patent number: 10776264
    Abstract: A power recovery technique for a data storage device having a non-volatile memory and a control unit is provided. When the data storage device regains power, the control unit writes dummy data to the nonvolatile memory, starting from the next page of a final page indicated by a final page indicator until the first word line group is finished. The first word line group contains an empty page indicated by an empty page indicator. In this manner, user data is protected from being written to an unreliable area.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 15, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Wen-Sheng Lin
  • Patent number: 10776228
    Abstract: A data storage device includes a flash memory, a controller and a random-access memory. The flash memory includes a plurality of planes, and each plane includes a plurality of blocks. A portion of blocks in each of the planes constitutes a super block, so that the flash memory includes a plurality of super blocks. The controller is coupled to the flash memory. When a first block of at least one first super block of the super blocks is damaged, and a second block of a second super block in the position corresponding to the damaged block is normal, the controller merges the second block of the second super block with the first super block to replace the first block. The random-access memory stores a compression table to record position information about the first block in the first super block and the number information of the second block.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: September 15, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Kuan-Yu Ke, Guan-Yao Huang, Shen-Ting Chiu
  • Patent number: 10776048
    Abstract: An electronic apparatus includes a data storage device including a plurality of plane groups and a controller configured to control the data storage device. The controller includes a temporary storage configured to store a command received from a host apparatus, a processor configured to define a plurality of queue regions corresponding to the plurality of plane groups within the temporary storage, and queue the command for each of the plurality of plane groups to a queue region matching with a corresponding plane group, and a plurality of pointer registers corresponding to the plurality of queue region, respectively, and configured to indicate positions of the plurality of queue regions. The processor changes a number of the queue regions, sizes of the queue regions, and sizes of the pointer registers according to a number of the plane groups.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventors: Injae Yoo, Dong Yeob Chun
  • Patent number: 10776268
    Abstract: Techniques for management of IS memory in a non-volatile storage device, and methods for use therewith, are described herein. The non-volatile storage device can include non-volatile memory, wherein a portion of the non-volatile memory is designated as intermediate storage (IS) memory and another portion of the non-volatile memory is designated as main storage (MS) memory. The IS memory may have lower read and write latencies than the MS memory. A host device may provide priority addresses to a memory controller with an indication that host data having one of the priority addresses is to receive priority to remain in IS memory over other host data.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: September 15, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: In-Soo Yoon, Chandrasekar Sundaresan
  • Patent number: 10776049
    Abstract: a memory system may include: a memory device including a plurality of memory blocks; and a controller configured to manage the plurality of memory blocks as a plurality of super blocks, the controller may classify and may manage super blocks formed by mixing and grouping at least one bad memory block and normal memory blocks as first super blocks, and may classify and may manage super blocks formed by grouping only normal memory blocks as second super blocks, the controller may check an accumulated size of write data received from a host, may group the write data into a plurality of data groups based on a result of the checking of the accumulated size, and may store, each time one data group is formed, the formed one data group in N first super blocks and M second super blocks.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventor: Se-Hyun Kim
  • Patent number: 10776308
    Abstract: Apparatuses, methods and storage medium associated with smart memory data store/load technology, are disclosed herein. In embodiments, an apparatus may include a processor; a plurality of memory units; a memory controller coupled with the processor and the plurality of memory units to control access of the plurality of memory units, that includes hardware physical memory interleaving support; and one or more hardware data processing logic blocks coupled to the plurality of memory units to provide near data processing of data received by the plurality of memory units. The apparatus may further include a driver to support applications operated by the processor to perform location-aware memory-mapped device accesses to selectively store or load data into selected ones or aggregation of selected ones of the plurality of memory units contiguously. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Soo Keong Ong, Jayson Strayer