Abstract: Apparatuses and methods for read source determination are provided. One example apparatus can include a controller configured to determine a source for read requests and to direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount, and direct read requests for the first portion of data to a first block of quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount.

Abstract: A method for discarding personal information comprises at least one among partial overwriting, SLC programming, and applying an erase pulse. The method for discarding personal information comprises a step for acquiring the program status of personal information-containing data of a memory block to be erased, generating data having a status that is equal to or higher than the program status corresponding to the personal information, and carrying out a partial overwriting operation on the personal information by using the generated data.

Abstract: A data storage device and method are disclosed for host-controlled data compression. In one embodiment, a data storage device is provided comprising a memory and a controller configured to communicate with the memory. The controller is further configured to selectively compress target data, wherein the target data is only compressed in response to receiving a compression request from a host; receive the compression request from the host; and in response to receiving the compression request from the host, compress the target data. Other embodiments are disclosed.

Abstract: A storage device configured to be connected to a redundant array of inexpensive disk (RAID) controller includes a plurality of non-volatile memories. A memory controller is configured to control the plurality of non-volatile memories to store data distributed by the RAID controller based on a RAID configuration signal received from the RAID controller. The memory controller is configured to perform self-diagnosis on the plurality of non-volatile memories to determine whether at least one of the plurality of non-volatile memories has an uncorrectable error when a RAID configuration signal is deactivated.

Abstract: A storage device non-fatal error debug system includes a storage device including a storage device chassis, storage device subsystems housed in the storage device chassis, and a non-fatal error debug subsystem provided in the storage device chassis and coupled to each of the storage device subsystems. The non-fatal error debug subsystem provides a counter system for each of a plurality of data path stages performed by the storage device subsystems to provide data path(s) in the storage device, and monitors each counter system during the execution of commands by the storage device subsystems via the performance of the data path stages. When the non-fatal error debug subsystem determines that a counter system provided for a data path stage performed by a storage device subsystem to provide a data path in the storage device indicates a non-fatal error, it collects debug information associated with that data path stage.

Abstract: In some exception flows, a device controller may need to store and subsequently recover a current state of a host queue. In these particular exception flows, recovering the current state of the host queue is complex due to the varying states a host queue may be in at the time of storing, including having pending commands in the host queue. Examples of such exception flows include low power modes in client SSDs and live migrations in enterprise SSDs. Using dummy host submission and completion queues during the host queue recovery process allows the device controller to efficiently operate even when there are pending commands in the host queue. The dummy queues may be stored in the HMB, internal DRAM, or any other system dummy buffer (i.e., in a different device or tenant).

Abstract: A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.

Abstract: Apparatus might include a first plurality of signal lines, a second plurality of signal lines, a controller, a first die, and a second die. The controller, the first die, and the second die might each be connected to the first plurality of signal lines and connected to the second plurality of signal lines. The first die and the second die might each include termination circuitry connected to a particular signal line of the second plurality of signal lines. The first die might be configured to activate its termination circuitry in response to receiving a particular combination of signal values on the first plurality of signal lines. The second die might be configured to deactivate its termination circuitry in response to receiving the particular combination of signal values on the first plurality of signal lines.

Abstract: Client data layout retention across server disruption can be performed and managed. In response to a data layout request from a client device (CD), a server can communicate, to CD, metadata, comprising a mapping of a group of blocks, in a data store of the server, to which CD is able to write data to the file, a file offset associated with the file, and a filesystem block number (FSBN) associated with the file offset. CD can write data to the group of blocks. CD can communicate data layout commit request, comprising the metadata relating to data layout, including file offset and FSBN, to the server. If server disruption occurs prior to committing data layout, CD can communicate reclaim request, comprising the metadata, to server, and server can recreate the data layout and commit the data layout to the data store based on the metadata.

Abstract: One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.

Abstract: A CXL memory module, a memory data swap method and a computer system. The CXL memory module may include a flash memory chip, a memory chip, and a controller chip connected with the flash memory chip and the memory chip. The controller chip is configured to be able to swap a part of data in the memory chip into the flash memory chip.

Abstract: A memory system includes a nonvolatile memory that includes a plurality of regions; a volatile memory; and a controller that is connected to the nonvolatile memory and the volatile memory. The controller is configured to store in the volatile memory a plurality of first counter values each indicating the number of times each of the plurality of regions has been accessed and a plurality of second counter values respectively corresponding to the plurality of first counter values, and write the first counter value of a first region of the plurality of regions to the nonvolatile memory in response to the second counter value of the first region being equal to or more than a threshold value.

Abstract: Methods, systems, and devices for configurable types of write operations are described. A memory device may receive a write command to write data in a zone of a memory system. The memory device may identify a physical address to store the data using a cursor associated with the zone based at least in part on receiving the write command. In some examples, the cursor may be associated with a type of a write operation based on a quantity of data associated with the cursor. As such, the memory device write, using a first type of the write operation or a second type of the write operation in accordance with the quantity of data, the data, and an indication of the type of the write operation used to write the data into the memory system.

Abstract: According to one embodiment, a dictionary compressor for compressing input first data includes a buffer and a search unit. The buffer stores data input to the dictionary compressor prior to the first data. The search unit acquires, from the first data, partial data strings each having a first data length and having head positions in the first data, respectively, that are sequentially shifted by a second data length shorter than the first data length. The search unit performs search processes in parallel and acquires search results respectively corresponding to the search processes, the search processes searching the buffer to acquire respective match data strings that at least partially match the partial data strings, respectively.

Abstract: A far memory device includes a far memory controller, a memory device coupled to the controller, a first port coupled to the far memory controller to support communication with a host processor over a first serial computer expansion bus, and a second port coupled to the far memory controller to support communication with a non-volatile data storage drive over a second serial computer expansion bus. The far memory device serves as a cache between the host processor and the non-volatile data storage drive and may perform aspects of cache management on behalf of the host processor.

Abstract: Methods, systems, and devices for atomic write operations are described. A host system may receive a sequence of data that includes a first set of data and a second set of data. The host system may determine, based on the sequence of data, a first set of contiguous logical addresses for the first set of data and a second set of contiguous logical address for the second set of data. The host system may then transmit to a memory system a write command that indicates the first set of contiguous logical addresses and the second set of contiguous logical addresses. The first set of contiguous logical addresses may be discontiguous with the second set of contiguous logical addresses.

Abstract: A method of operating a storage device includes: sensing an external voltage supplied from a host device; selecting a data transfer mode, where the data transfer mode is either a normal mode or a brown-out mode according to the external voltage; and performing a write operation or a read operation according to the selected mode, wherein: the data transfer mode is selected as the normal mode when the external voltage is within a normal range between a first operation voltage and a second operation voltage, and the data transfer mode is selected as the brown-out mode when the external voltage is within a low power range below the normal range and between the second operation voltage and a power-off detection voltage; and wherein one or more types of input/output operations of the host device are supported in both the normal mode and the brown-out mode.

Abstract: A host stores “context” metadata for logical block addresses (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data; in another embodiment, the context can point to other metadata.

Abstract: According to an embodiment of the present disclosure, a storage device may include a memory device, and a memory controller configured to receive a read command from an external host and control the memory device according to the read command, wherein the read command may include a basic header segment commonly included in commands transferred between the external host and the memory controller and including information indicating that the read command is a command for requesting data stored in the memory device, a transaction specific field including information indicating that the read command is a read command for at least two or more logical addresses, and an extra header segment including information on the at least two or more logical addresses.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes establishing a connection between the memory storage device and a host system; receiving a first request from the host system via the connection; detecting a status of the memory storage device in a time range according to the first request; and determining whether to use a memory in the host system according to the status.

Abstract: Provided are a storage device and an operating method thereof. The storage device includes a non-volatile memory including a plurality of memory regions and a storage controller configured to control the non-volatile memory through a performance path and at least one direct path, the storage controller including a buffer memory configured to store recovery data, wherein the storage controller writes the recovery data to the non-volatile memory through the at least one direct path in response to power being cut off and a fault being detected in the performance path, the performance path is a path for performing a write operation, a read operation, and an erase operation, and the at least one direct path is a path for performing only a write operation.

Abstract: An example method for optimizing data deletion in a storage system comprises: monitoring one or more attributes associated with a storage volume associated with a file system; and setting, based on the monitoring of the one or more attributes, a discard option to be either enabled or disabled for the storage volume, wherein when the discard option is enabled, the file system is configured to automatically issue a discard request in response to a request to delete data stored on one or more blocks within a storage device associated with the storage volume, the discard request configured to command the storage device to free the one or more blocks for use by the file system to store additional data; and when the discard option is disabled, the file system does not automatically issue the discard request in response to the request to delete the data.

Abstract: An apparatus includes circuitry couplable to a host system and a memory device. The circuitry is configured to determine whether a page table maintained on the circuitry includes a physical address of the memory device corresponding to a virtual address associated with a TLB fill request from the host system. Responsive to determining that the page table includes the physical address, the circuitry provides signaling indicative of a completion to the TLB fill request to the host system, prefetch a page of data at the physical address from the memory device using the physical address from the page table, and provide signaling indicative of the page of data to the host system.

Abstract: A memory system or memory controller may calculate a first data size, which is the sum of sizes of data requested to be written by write requests from outside the memory system after a first reference time point, calculate a second data size, which is the sum of sizes of data updated by the write requests among data already stored in the memory device from a second reference time point, and control execution of garbage collection on data stored in the memory device based on the first data size and the second data size.

Abstract: Techniques of memory tiering include retrieving, from a first tier in a first memory, data from a data portion and metadata from a metadata portion of the first tier upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first tier currently contains data corresponding to the system memory section in the received request. In response to determining that the first tier currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the first or second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.

Abstract: A system and method for providing storage virtualization (SV) is disclosed. According to one embodiment, a system includes a storage device having a tier 1 cache and a Tier 2 storage, an operating system and a file system having a Tier 0 memory cache that stores application data. The Tier 0 memory cache synchronizes the application data with the tier 1 cache and the Tier 2 storage.

Abstract: Aspects disclosed herein relate to a method comprising: obtaining a list of data paths to at least one persistent storage device through a plurality of NUMA nodes; associating with each data path, access performance information; receiving a request to access one of the at least one persistent storage device; calculating a preferred data path to the one of the at least one persistent storage device using the access performance information; and accessing the one of the at least one persistent storage device using the preferred data path.

Abstract: The present disclosure describes techniques of metadata management for transparent block level compression. A first area may be created in a backend solid state drive. The first area may comprise a plurality of entries. The plurality of entries may be indexed by addresses of a plurality of blocks of uncompressed data. Each of the plurality of entries comprises a first part configured to store metadata and a second part configured to store compressed data. Each of the plurality blocks of uncompressed data may be compressed individually to generate a plurality of compressed blocks. Metadata and at least a portion of compressed data associated with each of the plurality of compressed blocks may be stored in one of the plurality of entries based on an address of a corresponding block of uncompressed data. A second area may be created in the backend solid state drive for storing the rest of the compressed data.

Abstract: An example device includes: a compute core configured to: send a first request to flash manager circuitry, the first request to store write data in a flash memory; and send a second request to the flash manager circuitry, the second request sent after the first request, the second request to transfer an XIP read operation to the flash memory; the flash manager circuitry configured to: receive the first request; transmit the write data to the flash memory for storing in the flash memory; receive the second request before the storing of the write data is complete; determine whether to preempt the storing of the write data, transmit, in response to a determination to preempt, the XIP read operation to the flash; and the flash memory configured to provide data to the compute core based on the transmitted XIP read operation.

Abstract: A hybrid mode system containing an external device and a field-programmable gate array (“FPGA”) capable of providing configuration data to FPGA via a hybrid communication channel is disclosed. The system is able to identify a first communication protocol in accordance with at least a portion of address bits presented on a serial data line (“SDA”) wherein SDA is used as a connection between FPGA and the external device. The clock signals for receiving data are adjusted to a first clock frequency in accordance with the first communication protocol and clock cycles presented on a serial clock line (“SCL”). SCL is used to connection between FPGA and the external device. After transmitting the configuration data, a portion of FPGA is programmed to perform user-defined logic functions in response to the configuration data.

Abstract: A shingled magnetic recording (SMR) hard disk drive (HDD) receives a read command for data associated with a range of logical block addresses (LBAs). In situations where a first portion of valid data associated with the range of LBAs is stored in an SMR region of the HDD and a second portion of valid data associated with the range of LBAs is stored in a non-SMR region of the HDD, the first portion is read from the SMR region in a single disk access and copied to a first buffer of the HDD, and the second portion is read from the non-SMR region in one or more disk accesses and copied to a second buffer of the HDD. The valid data associated with the range of LBAs stored in the second buffer are copied to the first buffer to be combined with valid data associated with the range of LBAs stored in the first buffer, and the combined valid data is then transferred to the host to complete execution of the read command.

Abstract: A storage system calculates relative writability of SSDs and biases storage of data from write IOs to the SSD that has the greatest relative writability, where writability is a value calculated as a function of remaining wear-life and drive capacity. When the remaining wear-life of an SSD falls below a threshold, unstable data is evicted from that drive, where data stability is an indication of likelihood of data being changed. The drive with the greatest relative writability is selected as the target for the unstable data. The drive with the greatest relative writability is also selected as the donor for stable data that is moved to the free space created by eviction of the unstable data. Consequently, the SSD that triggers the low wear-life threshold processes fewer write IOs.

Abstract: A storage device includes a memory device including user memory blocks providing a user data region; and a controller configured to: map logical addresses used in a host to a portion of the user data region, and use a remaining portion of the user data region as an over-provisioning region, wherein the controller is further configured to control the memory device to: erase the user memory blocks based on a sanitize command from the host, provide, to the host, block address information of the user memory blocks based on a block address request from the host, access the user memory blocks based on block state check requests from the host, and provide, to the host, state information indicating whether the user memory blocks are erased according to access results.

Abstract: Systems and methods for secure booting of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine. The secure PLD is configured to retrieve a pre-authentication status associated with the configuration image from the NVM, determine or verify the retrieved pre-authentication status associated with the configuration image includes a valid status, and boot the PLD fabric of the secure PLD using the configuration image.

Abstract: The present disclosure provides storage devices and methods for operating the same. In some embodiments, a storage device includes a non-volatile memory including a plurality of sub-blocks that are independently erasable, and a processor configured to control a garbage collection operation on the plurality of sub-blocks. The plurality of sub-blocks includes a plurality of first sub-blocks that have a first block size and a plurality of second sub-blocks that have a second block size. The second block size is different from the first block size. The processor is further configured to select a victim sub-block with a lowest ratio of a valid page count to an invalid page count from among the plurality of sub-blocks, and copy a valid page of the victim sub-block to a target sub-block from among the plurality of sub-blocks.

Abstract: Containers are generated including data containers storing segments of files, segment tree containers storing upper-level segments of segment trees representing the files, and cloud containers storing headers from the data and segment tree containers. A header for a data container includes fingerprints identifying the segments of files. A header for a segment tree container includes fingerprints identifying the upper-level segments. The containers are sent to cloud storage for storage as a cloud unit. The cloud unit is attached to a deduplicated storage appliance by storing at the appliance the segment tree and cloud containers, cloud configuration details, and an index. The cloud configuration details identify the cloud storage having the cloud unit. The index maps the fingerprints to the containers. When a cloud unit is to be detached, the segment tree and cloud containers, and index from the local storage are deleted, but the cloud configuration details are maintained.

Abstract: A method and apparatus are described. The method comprises receiving a data packet comprising data to be written into the memory of a computing system and address data comprising an address in a set of addresses of a first address space of the computing system, identifying a subset of the set of addresses of the first address space with a subset of addresses in a second address space associated with the memory of the computing system, determining an address from a further subset of addresses in the second address space, writing the data to the region of the memory associated with the determined address and updating an address translation table on the computing system on the basis of the determined address.

Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation in a first mode to write a first portion of data to a single-level cell (SLC) cache, determining whether a logical saturation of the first portion of the data satisfies a first threshold condition based on the first maximum size, and in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache. The SLC cache includes a dynamic SLC cache having a first maximum size corresponding to the first mode and a second maximum size greater than the first maximum size corresponding to a second mode.

Abstract: Disclosed herein are related to an age detector for determining an age of a memory block, and a method of operation of the age detector. In one configuration, a memory system includes a memory block and an age detector coupled to the memory block. In one aspect, the memory block generates a first set of data in response to a first power on, and generates a second set of data in response to a second power on. In one configuration, the age detector includes a storage block to store the first set of data from the memory block, and inconsistency detector to compare the first set of data and the second set of data. In one configuration, the age detector includes a controller to determine an age of the memory block, based on the comparison.

Abstract: The progress of an erase operation for a memory device is monitored using an erase credit mechanism. In one approach, an erase operation is performed to erase a memory. Erase pulse slices used in the erase operation are monitored. Erase credits associated with the erase operation are determined. The erase credits include an erase credit associated with each of the erase pulse slices. Based on the erase credits, an extent of erasure of the memory is determined. In response to determining that the extent of erasure has reached a predetermined threshold, the erase operation is terminated.

Abstract: Methods and apparatus relating to techniques for region-based deterministic memory safety are described. In some embodiment, one or more instructions may be used to encrypt, decrypt, and/or check a pointer to a portion of the data stored in memory. The portion of the data is stored in a first region of the memory. The first region of the memory includes a plurality of identically sized allocation slots. Other embodiments are also disclosed and claimed.

Abstract: A storage system is operable to transition from operation in accordance with a first storage scheme to operation in accordance with a second storage scheme by, for each storage device of the plurality of storage devices, expanding a storage size of a single storage structure of the corresponding plurality of data storage structures identified to implement the second storage scheme from an initial size to a final size consuming full storage resources of the each storage device based on writing all new data of a plurality of write requests to the single storage structure in accordance with the second storage scheme, performing at least one expansion of the single storage structure within the each storage device in response to an expansion condition being met, and completing transition based on the single storage structure reaching the final size consuming the full storage resources of the each storage device.

Abstract: A storage device may select N number of candidate memory blocks among a plurality of memory blocks according to whether a target operation is garbage collection or wear leveling. The storage device may determine one or more victim memory blocks for the target operation among the candidate memory blocks, on the basis of a deviation in a reference factor among the candidate memory blocks.

Abstract: Techniques for providing a “bin-less” metadata page allocator for clustered systems with log-structured metadata storage. The techniques include providing a mapping structure in memory of a storage node of a clustered system. The mapping structure can have multiple layers configured to map logical addresses of metadata pages to physical addresses of storage drives within a storage array. The techniques include providing a translation table configured to translate logical addresses of metadata pages to corresponding current physical addresses of storage drives within the storage array. The techniques include, in response to an allocated logical address of a metadata page no longer being in-use, replacing its corresponding current physical address with a predefined value in the translation table, freeing the logical address, and inserting the freed logical address into a free logical address array. The techniques include allocating the freed logical address from the free logical address array.

Abstract: Provided is a data input/output (I/O) method using a storage node-based key-value store in a storage disaggregation environment. The data I/O method using the storage node-based key-value store includes receiving a command converted from a key-value write request of an application from a calculation node according to a communication protocol used in the storage node, converting the command into an I/O request using a key included in the command, the I/O request including a logical block address and a value corresponding to the key, and storing the value in a storage device of the storage node using the logical block address of the I/O request.

Abstract: A computing system receives a data packet comprising data to be written to the computing system and address data comprising an address in a set of addresses of a first address space of the computing system. An address is determined in a second address space of the computing system identified with the address of the data packet and writing the data to the computing system on the basis of the determination. A first subset and a second subset of the set is identified and the first subset of addresses of the second address space is associated with a region of memory of the computing system and the second subset of addresses of the second address space is associated with a region of a data storage area.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller uses a first predetermined memory block as a buffer to receive data from a host device. In response to a write command received from the host device, the memory controller determines a sub-region corresponding to the write command, determines whether the sub-region is a hot-write sub-region according to a write count corresponding to the sub-region and accordingly determines whether to use a second predetermined memory block as another buffer to receive data from the host device. When the memory controller determines that the sub-region corresponding to the write command is a hot-write sub-region, the memory controller writes the data into the second predetermined memory block. When the memory controller determines that the sub-region is not a hot-write sub-region, the memory controller writes the data into the first predetermined memory block.

Abstract: Techniques for supporting a native pipeline element abstract for use in processing and storing data objects in a storage environment. The techniques include providing a data object processing pipeline for execution on a storage system, ingesting, by the data object processing pipeline, data objects collected by a plurality of computerized devices coupled to the storage system, performing queuing and processing of the data objects at a series of processing elements of the data object processing pipeline, and providing the processed data objects from the storage system to a host computer for subsequent use or analysis. In this way, the number of storage requests needed to be handled by the storage system can be reduced. Moreover, because the data object processing pipeline can be implemented and executed on the storage system, the processing and storage of data objects in the storage environment can be performed more efficiently and optimized more easily.

Abstract: A data processing system is provided to include a storage unit and a controller in communication with the storage unit and configured to program write data to a first area as at least one of the plurality of storage areas with a priority over a second area as at least one of the plurality of storage areas and transfer data of the first area to the second area. The controller is further configured to adjust a size of the first area based on 1) a number of times saturated by the write data for the first area, a saturation occurring due to a size of the write data written to the first area being greater than a certain size and 2) an overflow size of the write data corresponding to a difference between the size of the write data and the certain size.

Abstract: A memory system includes a memory device with a memory cell array including a first and second plane and first and second caches. A controller is configured to output status information in response to a status read command. The status information indicating the states of the caches. The controller begins a first process in response to a command addressed to the first plane if the status information indicates the first and second caches are in the ready state, and begins a second process on the second plane according to a second command to the second plane if the status information indicates at least the second cache is in the ready state.