Programmable Read Only Memory (prom, Eeprom, Etc.) Patents (Class 711/103)
  • Patent number: 10353628
    Abstract: A method includes: receiving a plurality of host commands from a host to access storage media of a solid-state drive (SSD); monitoring a raw rate for performing the plurality of host commands; calculating an average rate by taking an average of the raw rate over a time unit; comparing the average rate against a threshold; detecting that the average rate falls below the threshold indicating an opening of an opportunity window; providing hints for the opportunity window; and determining whether to perform pending or imminent background operations during the opportunity window.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: July 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ramdas Kachare, Jongmin Gim, Yang Seok Ki
  • Patent number: 10353604
    Abstract: A device transmits the capabilities of the device for performing transformations on offloaded objects, to a host. The device receives an object definition command from the host, where the object definition command indicates one or more transformations to apply to an object. One or more transformations are performed on the object to generate one or more transformed objects. A completion command is transmitted to the host to indicate completion of the one or more transformations on the object.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Jawad B. Khan, Kelvin D. Green, Vasanthi Jagatha
  • Patent number: 10353627
    Abstract: The invention relates to a memory device and a memory system having the same. The memory device includes a memory block including a plurality of pages, a peripheral circuit including a plurality of buffers sensing data stored in a selected page of the plurality of pages, temporarily storing high usage frequency data, and outputting the data, and a control circuit controlling the peripheral circuit to output the data after performing a sensing operation on the selected page, storing the high usage frequency data to at least one of the buffers, or outputting the high usage frequency data without performing the sensing operation in response to a read command.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: July 16, 2019
    Assignee: SK hynix Inc.
    Inventors: Yong Hwan Hong, Byung Ryul Kim
  • Patent number: 10353588
    Abstract: In a data storage system a host I/O request is received from a host-side interface, the host I/O request specifying a range of logical block addresses (LBAs) of a mapped logical unit (MLU). Mapping information is obtained for a plurality of extents of the underlying logical units of storage. If there are a sufficient number of free sub-I/O request tracking structures to track completion of a plurality of respective sub-I/O requests for the extents, then the sub-I/O requests are concurrently issued to the device-side interface, using the mapping information. Upon receiving transfer initiation responses for the sub-I/O requests to initiate transfer of the respective extents, they are forwarded to the host-side interface to cause the respective extents to be transferred to/from the host. As the transfer initiation responses are forwarded to the host-side interface, the respective sub-I/O request tracking structures are freed for use in processing subsequent host I/O requests.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 16, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Milind Koli, Timothy C. Ng
  • Patent number: 10353614
    Abstract: A RAID system and method based on a solid-state storage medium. The system includes a plurality of solid-state storage devices and a main control unit. Each solid-state storage device includes a solid-state storage medium and a controller for controlling reading and writing of the solid-state storage medium. The main control unit is electrically connected to the controller of each of the solid-state storage devices in a RAID array. The main control unit is used for performing address mapping from a logical block address in the RAID array to a physical block address of the flash memory solid-state storage device. The address mapping and the RAID function can be integrated to solve the problems of write amplification and low performance. The unified management of address mapping of the solid-state storage devices can be implemented to improve the efficiency of garbage collection and wear leveling of the solid-state storage system.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: July 16, 2019
    Assignee: SHANNON SYSTEMS LTD.
    Inventor: Xueshi Yang
  • Patent number: 10353813
    Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to determine a first value of a first checkpoint associated with a first snapshot, receive a second value of a second checkpoint associated with a translation table entry from an additional source, determine whether the second value of the second checkpoint is after the first value of the first checkpoint, in response to determining that the second value of the second checkpoint is after the first value of the first checkpoint, retrieve the translation table entry associated with the second checkpoint from the additional source, and reconstruct the translation table using the translation table entry associated with the second checkpoint.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: July 16, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ajith Kumar Battaje, Tanay Goel, Sandeep Sharma, Saurabh Manchanda, Ashish Singhai, Vijay Karamcheti
  • Patent number: 10346268
    Abstract: Systems and methods are provided for flash memory devices to improve the write performance in case of write path errors and to hide the write path error correction latency. Some embodiments can provide instant parity correction to allow user data sharing the same strip with the data block having an error to be programmed into the flash memory before the failed data is corrected. Additionally, selected stalling can allow some independent data in different flash memory dies or planes to be programmed during the time of write path error correction.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: July 9, 2019
    Assignee: SK Hynix Inc.
    Inventors: Yu Cai, Fan Zhang, Sangcheol Lee
  • Patent number: 10346432
    Abstract: A compaction policy imposing soft limits to optimize system efficiency is used to select various rowsets on which to perform compaction, each rowset storing keys within an interval called a keyspace. For example, the disclosed compaction policy results in a decrease in a height of the tablet, removes overlapping rowsets, and creates smaller sized rowsets. The compaction policy is based on the linear relationship shared between the keyspace height and the cost associated with performing an operation (e.g., an insert operation) in that keyspace. Accordingly, various factors determining which rowsets are to be compacted, how large the compacted rowsets are to be made, and when to perform the compaction, are considered within the disclosed compaction policy. Furthermore, a system and method for performing compaction on the selected datasets in a log-structured database is also provided.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: July 9, 2019
    Assignee: Cloudera, Inc.
    Inventor: Todd Lipcon
  • Patent number: 10346096
    Abstract: Implementations disclosed herein include a method comprising receiving a TRIM request for a media cache in a storage media from a host, determining whether a TRIM range in the TRIM request overlaps with an active operation, invalidating the TRIM range responsive to determining that the TRIM range does not overlap with an active operation, and inserting at least one null node in the media cache. The method may comprise receiving a host read request, performing a media cache search for a read LBA range, and determining where data is located. If all the data is located in the media cache, the system reads from the media cache. If the data is located in a null node, patterning for the null node occurs. If the data is located partially in the main store, the media cache, or a null node, the data may be read, combined, and returned to the host.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: July 9, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Yan Naing, Harry Tiotantra, PohGuat Bay, Thein Than Zaw, CheeHou Peng
  • Patent number: 10346052
    Abstract: A memory system includes a nonvolatile memory device; and a controller suitable for processing a write request of first data transmitted from a host device. The controller includes a first processing circuit suitable for generating a read command afforded with a priority, based on the write request; and a second processing circuit suitable for processing the read command according to the priority and thereby reading second data including old data of the first data from the nonvolatile memory device.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 9, 2019
    Assignee: SK hynix Inc.
    Inventors: Seung Gu Ji, Duck Hoi Koo
  • Patent number: 10346040
    Abstract: A memory management method is provided according to an exemplary embodiment. The method includes: receiving first data; performing a first programming process and a data merging process; and stopping the data merging process before the total number of first-type physical unit reaches a second threshold value if the first data is first-type data. Accordingly, an influence caused by the data merging process on the writing speed for specific type of data may be reduced.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: July 9, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Jyun-Kai Huang
  • Patent number: 10347305
    Abstract: A memory device includes a page buffer group configured to read normal data stored in a memory cell array, a control logic configured to store logic data, and a pipe latch control unit configured to latch the normal data outputted from the page buffer group in synchronization with a read enable pipe signal and latch the logic data outputted from the control logic in synchronization with the read enable pipe signal.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 9, 2019
    Assignee: SK hynix Inc.
    Inventor: Kyeong Min Chae
  • Patent number: 10346404
    Abstract: A database table is partitioned with column-major layout by limiting partitioning one or more columns containing join-column values for a join operator. Join operations are executed for joining the partitioned columns.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stefan Arndt, Gopi K. Attaluri, Ronald J. Barber, Guy M. Lohman, Lin Qiao, Vijayshankar Raman, Eugene J. Shekita, Richard S. Sidle
  • Patent number: 10346312
    Abstract: A method for using a variable-size flash translation layer. The method includes reading an entry in a map based on a read logical block address in a read request to obtain both a physical address of a particular page in a memory and information regarding compressed data with a variable size; converting the information to both an address in the particular page and a number of read units in the memory that contain the compressed data; and reading the compressed data from at least the particular page in the memory based on the address and the number of read units.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: July 9, 2019
    Assignee: Seagate Technology LLC
    Inventor: Earl T. Cohen
  • Patent number: 10338985
    Abstract: According to the embodiments, an external storage device switches to an interface controller for supporting only a read operation of nonvolatile memory when a shift condition for shifting to a read only mode is met. A host device switches to an interface driver for supporting only the read operation of the nonvolatile memory when determining to recognize as read only memory based on information acquired from the external storage device.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Daisuke Hashimoto
  • Patent number: 10339071
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
  • Patent number: 10338998
    Abstract: The invention introduces a method for priority writes in an SSD (Solid State Disk) system, performed by a processing unit, including at least the following steps. After a priority write command instructing the processing unit to write first data whose length is less than a page length in a storage unit is received, a buffer controller is directed to store the first data from the next available sub-region of a buffer, which is associated with a priority write, in a first direction. After a non-priority write command instructing to write second data whose length is less than page length in the storage unit is received, the buffer controller is directed to store the second data from the next available sub-region of the buffer, which is associated with a non-priority write, in a second direction.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: July 2, 2019
    Assignee: SHANNON SYSTEMS LTD.
    Inventors: Ningzhong Miao, Zhen Zhou
  • Patent number: 10340019
    Abstract: A semiconductor memory device includes a memory cell array including first and second groups of memory strings respectively coupled to first and second groups of bit-lines, wherein the first and second groups of memory strings respectively include first and second groups of selection transistor cells; a peripheral circuit suitable for applying a program voltage, and performing program verification operation for the memory cell array; and a control logic suitable for controlling the peripheral circuit to perform a first program verification operation for the first group of selection transistor cells and a second program verification operation for the second group of selection transistor cells.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: July 2, 2019
    Assignee: SK hynix Inc.
    Inventor: Eun Young Park
  • Patent number: 10338839
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of nonvolatile memory dies, and a controller. The controller classifies the nonvolatile memory dies into a plurality of physical sets such that each of the nonvolatile memory dies belongs to only one physical set. The controller creates a plurality of storage regions which share each of the physical sets and each of which spans the physical sets. The controller sets one of the physical sets to a first mode for permitting a write operation and a read operation, and sets each of the other physical sets to a second mode for permitting a read operation and inhibiting a write operation.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: July 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • Patent number: 10338843
    Abstract: A method for moving data internally, performed by a processing unit, including at least the following steps. The processing unit transmits partial copyback read commands to a storage sub-unit through an access interface, where each partial copyback read command is used to direct logic circuits of the storage sub-unit to store partial data of a page of the storage sub-unit in a designated location of a data buffer of the storage sub-unit. The processing unit further transmits a copyback write command to the storage sub-unit through the storage sub-unit for programming the data of the data buffer in a new page of the storage sub-unit.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: July 2, 2019
    Assignee: Silicon Motion, Inc.
    Inventors: Hsu-Ping Ou, Chih-Kang Kung
  • Patent number: 10338821
    Abstract: Approaches, techniques, and mechanisms are disclosed for improving the performance of memory controllers for memory devices. A system may have a memory controller that interfaces with a memory device to store or retrieve information. When the system needs to retrieve information from the memory device, the memory controller sends an address and a command to instruct the memory device to read the information stored at the address. The memory device reads the information, and after a specific amount of time, the memory device sends the information to the memory controller. According to an embodiment, “dummy” data is sent first prior to the availability of the data read out of the memory devices, while waiting for the requested data to be accessed, and then the actual data is sent immediately following the dummy data. According to an embodiment, a geometry of a memory device has only one column of memory cells that are used to store information.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 2, 2019
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Rajesh Ananthanarayanan, Jinying Shen, Amir Alavi
  • Patent number: 10339045
    Abstract: A valid data management method and a storage controller are provided. The method includes creating a valid data mark table and a valid logical addresses table corresponding to a target physical unit according to a logical-to-physical table and a target physical-to-logical table corresponding to the target physical unit, wherein the valid data mark table records a plurality of mark values respectively corresponding to a plurality of target logical addresses, the mark values respectively indicate whether the corresponding logical addresses is valid or invalid, and the valid logical addresses table only records one or more valid target logical addresses according to an order of one or more first bit values in the valid data mark table; and identifying one or more valid data of the target physical unit according to the logical-to-physical table, the valid data mark table and the valid logical addresses table corresponding to the target physical unit.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: July 2, 2019
    Assignee: SHENZHEN EPOSTAR ELECTRONICS LIMITED CO.
    Inventors: Hsiu-Hsien Chu, Hung-Chih Hsieh, Yu-Hua Hsiao
  • Patent number: 10339050
    Abstract: An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. The memory controller orchestrates direct data transfer by issuing a first direct transfer command to a first memory module and a second direct transfer command to a second memory module. The first memory module is responsive to receipt of the first direct transfer command to directly transmit the data for receipt by the second memory module in a way that bypasses the memory controller. The second memory module is responsive to the second direct transfer command to receive the data from the first memory module directly, rather than via the memory controller. One of the first and second memory modules may be used as a cache for data stored in the other memory module. The direct data transfer may comprise a data move or a data copy operation.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 2, 2019
    Assignee: Arm Limited
    Inventors: Andreas Hansson, Wendy Arnott Elsasser, Michael Andrew Campbell
  • Patent number: 10338664
    Abstract: A control module used with a peripheral unit having configuration information through a system bus includes a storage unit, a state machine unit and an event detector. The storage unit is configured to store a program. The state machine unit is configured to operate under the program. The event detector is configured to receive a hardware interrupt signal from the peripheral unit via an additional wire, wherein the event detector triggers the state machine to perform one of storing and retrieving the configuration information respectively to and from the storage unit via the system bus.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: July 2, 2019
    Assignee: M2 COMMUNICATION INC.
    Inventors: Fabien Petitgrand, Huang-Lun Lin
  • Patent number: 10339343
    Abstract: A storage system is provided comprising a memory and a controller. The controller is configured to receive a write command, data, and a logical address; determine a physical address associated with the logical address; generate protection information for the data using the data and at least one of the logical address and physical address; and store the data and the protection information in the memory without storing the at least one of the logical address and physical address in the memory.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: July 2, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel Helmick, Majid Nemati Anaraki, Mai Ghaly
  • Patent number: 10339062
    Abstract: In general, embodiments of the technology relate to a method and system for storing and reading data from persistent storage. More specifically, embodiments of the technology relate to a method and system for storing data in persistent storage, where the data written to the persistent storage is not immediately accessible in the persistent storage (i.e., during the inaccessibility period). In such instances, embodiments of the technology provide a method and system to enable the storage system to service read requests for the data using a primary cache entry table (PCET) and an overflow table.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: July 2, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Todd Wilde, Samir Rajadnya, Karthik Ramachandran, Michael Nishimoto
  • Patent number: 10331518
    Abstract: A method for execution by an integrity processing unit includes performing a deterministic function on data for storage to produce an integrity value. The data and the integrity value are combined in accordance with a combining function to produce a data package. The processing system determines an encryption approach in response to determining to encrypt the data package. The data package is encrypted in accordance with the encryption approach to produce a secure package. The secure package is encoded to produce a set of slices. The set of slices is decoded to reproduce the secure package. The secure package is decrypted to reproduce the data package. The data package is de-combined in to generate reproduced data and a received integrity value. The deterministic function is performed on the data to produce a calculated integrity value, and the received integrity value is compared to the calculated integrity value.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason K. Resch, Wesley B. Leggette
  • Patent number: 10332604
    Abstract: Apparatuses, systems, and methods are disclosed for managing configuration parameters for non-volatile data storage. A control module is configured to limit erase dwell times for blocks of a non-volatile memory medium to satisfy a threshold. A block classification module is configured to group blocks of a non-volatile memory medium based on retention times for the blocks. A block access module is configured to access at least one group of blocks using a read voltage threshold selected based on a grouping.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 25, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: James Peterson, Gary Janik, Jea Hyun
  • Patent number: 10331553
    Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Daniel J. Hubbard, Renato C. Padilla, Ashutosh Malshe, Harish R. Singidi
  • Patent number: 10331457
    Abstract: In one example, a computer having a processor and a byte-addressable non-volatile read-write main memory. The memory is partitioned into plural regions, each region having at least one defined operational property. At least one of the regions is a metadata region to store plural data sets. Each data set specifies a location in memory, and the at least one operational property, of a corresponding one of the regions.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: June 25, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Carlos Haas Costa, Taciano Dreckmann Perez, Diego Rahn Medaglia, Mauricio Nunes Porto, Roberto Bender, Joao Claudio Ambrosi
  • Patent number: 10333557
    Abstract: According to one embodiment, a memory system includes a first volatile memory, a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of chips. The controller generates a second error correcting code using data stored in the first volatile memory. The second error correcting code is a code for correcting data which cannot be corrected included in a first data group using a first error correcting code. The controller releases an area of the first volatile memory corresponding to the first data group written in the nonvolatile memory, before completion of writing of all of the data which are stored in the first volatile memory and includes in a codeword of the second error correcting code to the nonvolatile memory.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Erika Kaku, Yoshihisa Kojima
  • Patent number: 10331551
    Abstract: According to one embodiment, an information processing device includes a transmission unit and reception unit. The transmission unit transmits write data and a logical address of the write data to a memory device. The memory device includes a plurality of erase unit areas. Each of the erase unit areas includes a plurality of write unit areas. The reception unit receives, from the memory device, area information including data identification information indicative of data written to an erase unit area to be subjected to garbage collection.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: June 25, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • Patent number: 10331356
    Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi Kunimatsu, Kenichi Maeda
  • Patent number: 10331366
    Abstract: A method of operating a data storage device configured to allow a plurality of non-volatile memory devices, including a first non-volatile memory device and second non-volatile memory devices, to lead control of power consumption. The method includes receiving, by each of the second non-volatile memory devices, a state signal indicating operation or non-operation of the first non-volatile memory device and determining, by each of the second non-volatile memory device, whether to operate based on the state signal.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: June 25, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Pil Lee, Seok Won Ahn, Hyun Ju Yi, Jun Ho Choi
  • Patent number: 10334334
    Abstract: Examples may include a sled for a rack of a data center including physical storage resources. The sled comprises an array of storage devices and an array of memory. The storage devices and memory are directly coupled to storage resource processing circuits which are themselves, directly coupled to dual-mode optical network interface circuitry. The circuitry can store data on the storage devices and metadata associated with the data on non-volatile memory in the memory array.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: June 25, 2019
    Assignee: INTEL CORPORATION
    Inventors: Steven C. Miller, Michael Crocker, Aaron Gorius, Paul Dormitzer
  • Patent number: 10324833
    Abstract: A memory control device includes a host interface, a memory interface, and a controller configured to control the memory interface to output data to a non-volatile semiconductor memory for writing therein. The data include first data that the host interface received from a host, second data read out from the non-volatile semiconductor memory for memory refresh, and third data read out form the non-volatile semiconductor memory for garbage collection. When the memory refresh is not carried out, the controller adjusts a ratio of the first data with respect to the third data to be a first value. When the memory refresh is carried out, the controller calculates a second value based on the first value, and adjusts a ratio of the first data with respect to a total of the second data and the third data to be the second value.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: June 18, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Yosuke Mitsumasu
  • Patent number: 10324639
    Abstract: A data storage device includes a plurality of solid state disks (SSDs) and a controller configured to control the SSDs. The controller respectively writes a first data segment and duplicated data of the first data segment to first-type memories of two respective SSDs among the plurality of SSDs in response to a first write request of a host, respectively writes a second data segment and duplicated data of the second data segment to first-type memories of two respective SSDs among the plurality of SSDs in response to a second write request of the host, and writes parity data generated based on the duplicated data to a first-type memory or a second-type memory of a parity SSD. The data storage device may be included in a data processing system.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung Min Seo
  • Patent number: 10324630
    Abstract: A memory system includes a controller and a plurality of nonvolatile memories; a temperature control unit suitable for measuring a temperature of each of the plurality of nonvolatile memories, and comparing each measured temperature with a predetermined threshold value; a signal generation unit generating busy signals corresponding to one or more of the nonvolatile memories when the measured temperature is higher than the predetermined threshold value; and an interface unit transmitting the busy signal to the controller.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventors: Duck-Hoi Koo, Yong Jin
  • Patent number: 10324650
    Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: June 18, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Arkaprava Basu, Mitesh R. Meswani, Dibakar Gope, Sooraj Puthoor
  • Patent number: 10324661
    Abstract: A storage device including a nonvolatile memory device and an operating method of the storage device. The method includes receiving first data from an external device, compressing the received first data based on a first compression ratio, programming the compressed first data in the nonvolatile memory device, reading second data from the nonvolatile memory device, compressing the second data based on a second compression ratio that may be higher than the first compression ratio, and programming the compressed second data in the nonvolatile memory device.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: June 18, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong Hyun Yoon, Jupyung Lee
  • Patent number: 10324628
    Abstract: The disclosed computer-implemented method for reducing data fragmentation may include (1) identifying update data which updates an initial data set; (2) categorizing, using a database manager, the update data based on how the update data is expected to impact digital storage device resources; (3) storing the update data in a physical storage device in a physical order based on the category of the update data; and (4) updating, after storing the update data, an extent map indicating a mapping of logical locations of the update data to physical locations at which the update data is stored. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: June 18, 2019
    Assignee: Veritas Technologies LLC
    Inventors: Shuangmin Zhang, Shengzhao Li, Xianbo Zhang, Kai Li, Weibao Wu
  • Patent number: 10324869
    Abstract: A storage device includes random access memories, nonvolatile memory devices, a controller configured to control the nonvolatile memory devices, and a driver circuit configured to receive a command and an address from an external device, output a buffer command according to the command and the address, and transmit the command and the address to one of a first channel connected to the random access devices and a second channel connected to the controller according to the command and the address. The storage device further includes a plurality of data buffers configured to communicate with the external device and electrically connect the external device to one of a third channel connected to the random access memory devices and a fourth channel connected to the controller in response to the buffer command. Each of the data buffers includes a FIFO (first-in first-out) circuit.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Ju Lee, Youngkwang Yoo, Youngjin Cho
  • Patent number: 10324793
    Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Kiran Pangal, Prashant S. Damle, Rajesh Sundaram, Shekoufeh Qawami, Julie M. Walker, Doyle Rivers
  • Patent number: 10324786
    Abstract: A method for managing data stored in a flash memory is provided, where the flash memory includes a plurality of blocks. The method includes: providing a program list, where the program list records information about programmed blocks of the plurality of blocks and sequence of write times of the programmed blocks; detecting quality of a first block of the plurality of blocks to generate a detecting result, where the first block is the programmed block that has an earliest write time; and determining whether to move contents of the first block to a blank block, and to delete the contents of the first block according to the detecting result.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: June 18, 2019
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Li-Sheng Kan
  • Patent number: 10325668
    Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Gary F. Besinga, Scott A. Stoller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
  • Patent number: 10318182
    Abstract: A semiconductor memory apparatus may include a first memory apparatus and a second memory apparatus, and may perform various operation modes. The first and second memory apparatuses may independently perform a write operation and a read operation in a first operation mode. The first memory apparatus may perform a write operation and a read operation and the second memory apparatus may perform a write operation in a second operation mode. The second memory apparatus may perform a write operation and a read operation in a third operation mode.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: June 11, 2019
    Assignee: SK hynix Inc.
    Inventors: Hyun Jung Park, Kyung Hoon Kim
  • Patent number: 10318382
    Abstract: A method includes determining, by a computing device of a dispersed storage network (DSN), a source name for a data object to be scanned for missing encoded data slices. The method further includes issuing list source requests to the set of storage units. When a list source response is not received from a storage unit of the set of storage units within a response timeframe, the method further includes identifying one or more encoded data slices stored on the storage unit as potentially missing encoded data slices; determining a next level missing encoded data slice determination approach for the storage unit based on one or more of: a number of potentially missing encoded data slices, a performance goal, a network loading level, a rebuilding loading level, a predetermination, and an entry of a system registry; and executing the next level missing encoded data slice determination approach.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Thomas F. Shirley, Jr., Gary W. Grube, Bart R. Cilfone, Ravi V. Khadiwala, Greg R. Dhuse, Thomas D. Cocagne, Michael C. Storm, Yogesh R. Vedpathak, Wesley B. Leggette, Jason K. Resch, Andrew D. Baptist, Ilya Volvovski
  • Patent number: 10318185
    Abstract: An apparatus is described. The apparatus can include non-volatile memory, an embedded processor, and a memory controller. The memory controller can access data from the byte addressable non-volatile memory using at least one of: a first addressing scheme or a second addressing scheme. The memory controller can provide the data to a host system over a first interface when the data is accessed using the first addressing scheme. The memory controller can provide the data to the embedded processor over a second interface when the data is accessed using the second addressing scheme.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventor: Frank Hady
  • Patent number: 10318180
    Abstract: A storage array uses both high endurance SSDs and low endurance SSDs for metadata paging. Wear cost values are calculated for each page of metadata in cache. The wear cost values are used to select pages for swapping out of the cache to the SSDs. The wear cost values may be calculated as a function of a first term that is indicative of whether the respective page of metadata will be written to high endurance or low endurance SSDs; a second term that is indicative of likelihood of data associated with the respective pages of metadata that will possibly be changed due to a write; and a third term that is indicative of age of the respective page of metadata in the cache since most recent use. The terms may be estimated and independently weighted. The portion of cache allocated for the metadata may be increased to avoid exceeding DWPD targets.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 11, 2019
    Assignee: EMC IP Holding Cmpany LLC
    Inventors: Gabriel Benhanokh, Assaf Natanzon, Alexandr Veprinsky, Arieh Don, Felix Shvaiger
  • Patent number: 10318167
    Abstract: A memory system includes: a memory device; and a controller suitable for controlling the memory device, wherein the controller performs a read operation in a first region of the memory device in response to a read command from a host, and sets a second region of the memory device, into which data stored in the first region is to be copied, based on a read number of the first region.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: June 11, 2019
    Assignee: SK hynix Inc.
    Inventor: Soong-Sun Shin