Programmable Read Only Memory (prom, Eeprom, Etc.) Patents (Class 711/103)
  • Patent number: 11456025
    Abstract: A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: September 27, 2022
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Kenneth L. Wright
  • Patent number: 11455243
    Abstract: A data merge method for a rewritable non-volatile memory module including multiple physical units is provided. The method includes: starting a first data merge operation, and selecting at least one first physical unit for executing the first data merge operation and at least one second physical unit for executing a second data merge operation from the physical units; reading first mapping information from the rewritable non-volatile memory module, and copying first valid data collected from the at least one first physical unit to at least one third physical unit in the physical units; identifying second valid data in the at least one second physical unit according to the first mapping information in the first data merge operation; and starting the second data merge operation, and copying the second valid data collected from the at least one second physical unit to at least one fourth physical unit in the physical units.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: September 27, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11455240
    Abstract: A memory system includes: a memory device including a plurality of memory blocks each having a plurality of pages suitable for storing data; and a controller suitable for: receiving a plurality of commands from a host; controlling the memory device to perform a plurality of command operations in response to the plurality of commands; identifying parameters for the memory blocks affected by the command operations performed to the memory blocks; selecting first memory blocks among the memory blocks according to the parameters; and controlling the memory device to swap data stored in the first memory blocks to second memory blocks among the memory blocks.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: September 27, 2022
    Assignee: SK hynix Inc.
    Inventors: Jong-Min Lee, Duk-Rae Lee
  • Patent number: 11455252
    Abstract: Techniques for generating a model for predicting when different hybrid prefetcher configurations should be used are disclosed. Techniques for using the model to predict when different hybrid prefetcher configurations should be used are also disclosed. The techniques for generating the model include obtaining a set of input data, and generating trees based on the training data. Each tree is associated with a different hybrid prefetcher configuration and the trees output certainty scores for the associated hybrid prefetcher configuration based on hardware feature measurements. To decide on a hybrid prefetcher configuration to use, a prefetcher traverses multiple trees to obtain certainty scores for different hybrid prefetcher configurations and identifies a hybrid prefetcher configuration to used based on a comparison of the certainty scores.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: September 27, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Paul S. Keltcher, Mayank Chhablani, Alok Garg, Furkan Eris
  • Patent number: 11455170
    Abstract: The present application pertains to a processing device or a distributed processing system using the processing device.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: September 27, 2022
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Gang Shan, Ye Yang, Jingzhong Yang
  • Patent number: 11455123
    Abstract: A data storage apparatus may include a storage and a controller configured to operate in a throttling mode including a first performance mode and a second performance mode based on measured temperature of the storage. The controller comprises a performance adjusting component configured to determine target performance of the first performance mode based on at least one of temperature of the storage and the number of entries into the second performance mode when the temperature of the storage is greater than or equal to a first threshold value.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: September 27, 2022
    Assignee: SK hynix Inc.
    Inventor: Ji Ho Moon
  • Patent number: 11455249
    Abstract: Provided herein may be a storage device, a method of operating the storage device, a computing system including the storage device and a host device for controlling the storage device, and a method of operating the computing system. A memory controller may include a host interface configured to receive bad block information on one or more bad blocks of a second memory device from a host device; and a bad block processor configured to store data of one or more source bad blocks of the first memory device in one or more available memory blocks of the first memory device by controlling the first memory device, the source bad blocks of the first memory device corresponding to the bad block information, the available memory blocks being different from the source bad blocks.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 27, 2022
    Assignee: SK hynix Inc.
    Inventor: Seok Jun Lee
  • Patent number: 11455112
    Abstract: A non-volatile memory device includes a non-volatile memory unit, a control unit, and an interface. The control unit receives a write request, determines whether data is an object of a write of sequential management when a write size of the received data is smaller than a management unit of erasure, performs first write processing in which the received data smaller than the management unit of the erasure is sequentially written when the data is the object of the write of the sequential management, and performs second write processing in which the received data smaller than the management unit of the erasure is written by the management unit of the write when the data is not the object of the write of the sequential management.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: September 27, 2022
    Assignee: Sony Group Corporation
    Inventors: Hiroaki Yamazoe, Daisuke Nakajima, Toshifumi Nishiura, Kan Nagashima
  • Patent number: 11449382
    Abstract: A memory system includes a non-volatile memory device and controller circuitry. The non-volatile memory device includes an array of memory cells that includes memory blocks and pages. Each separate memory block includes a separate, respective set of one or more pages. The controller circuitry is configured to control an operation of the non-volatile memory device. The controller circuitry includes processing circuitry configured to perform a recovery operation for the non-volatile memory device in response to a determination that a specific event has occurred at the memory system during a program operation of the non-volatile memory device. The recovery operation includes determining status information associated with a first group including at least one page, determining a quantity of a set of pages included in a second group based on the status information, and programming dummy data for one or more pages of the set of pages included in the second group.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: September 20, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hee-Tai Oh
  • Patent number: 11450394
    Abstract: A controller that controls a nonvolatile memory apparatus may include a first memory configured to temporarily store user data, a second memory including a plurality of memory regions composed of one or more meta regions for storing meta data and at least one spare region, and a processor configured to control the first memory and the second memory and perform first start-gap wear leveling on at least one meta region using the at least one spare region as a gap.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: September 20, 2022
    Assignees: SK hynix Inc., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Soo Hong Ahn, Eui Young Chung, Young Min Park
  • Patent number: 11449386
    Abstract: A system is provided to receive a first request to write data to a storage system, which comprises an MRAM, a NOR, a DRAM, and a NAND. The system writes the data to the MRAM. The system copies the data from the MRAM: to the NOR in response to determining that the data is read at a frequency greater than a first predetermined threshold and is updated at a frequency less than a second predetermined threshold; to the DRAM in response to determining that the data is read at a frequency less than the first predetermined threshold and is updated at a frequency greater than the second predetermined threshold; and to the NAND in response to determining that the data is read at a frequency less than the first predetermined threshold and is updated at a frequency less than the second predetermined threshold.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: September 20, 2022
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 11449232
    Abstract: A scheduling system for a memory controller is provided. The system includes a scheduler configurable to receive a plurality of operation requests from a plurality of masters. The scheduler is configurable to form a sequence of one or more phases from each of the operation requests. The scheduler is configurable to arbitrate the plurality of operation requests and the one or more phases through one or more configurable policies. The system includes a sequencer configurable to receive the one or more phases and communicate with at least two flash memory devices having differing types of flash memory device interfaces through a plurality of channels.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: September 20, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Hari Kannan, Nenad Miladinovic, Randy Zhao
  • Patent number: 11449430
    Abstract: Provided is a method of data storage, the method including receiving a write request including a user key, determining the user key exists in a cache, generating or updating metadata corresponding to the user key, writing data corresponding to the write request to a storage device, converting the metadata to a device format corresponding to the storage device, and storing the metadata on the storage device.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: September 20, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heekwon Park, Ho bin Lee, Ilgu Hong, Yang Seok Ki
  • Patent number: 11449443
    Abstract: Increases in efficiency of storage device operation may be realized if the limited number of available high-priority communication channels are better optimized and assigned among hosts that may best utilize them. This assignment can occur in response to an evaluation of the overall zone usage or by received metadata and/or indicia from the host. The storage device may periodically, or in response to a command, reevaluate the assigned priority status of each communication channel and associated host/zone pair. For example, the storage device may demote or remove a communication channel from high-priority to low-priority. This process can be continued during a preconfigured time window which can be adjusted before, during, or after priority evaluation. The continuous operation of this process can allow for adjustments being made to priority levels within the storage device that may further increase total operational efficiency.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 20, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Oleg Kragel, Xiangyu Tang, Vijay Sivasankaran, Mikhail Palityka
  • Patent number: 11449439
    Abstract: Periodic signal timing calibration is implemented in time-distributed fragments executed concurrently with occasional system-idling maintenance operations to maintain reliable synchronous communication between interconnected system components without impacting system availability.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: September 20, 2022
    Assignee: Rambus Inc.
    Inventors: Kartik Dayalal Kariya, Sreeja Menon
  • Patent number: 11449252
    Abstract: A method includes the steps of storing non-header data into a plurality of logical pages (“Lpages”) of a non-volatile memory (“NVM”), each Lpage including a number of read units, wherein at least one of the read units is a spanning read unit that spans Lpage boundaries and includes a first byte of at least one Lpage starting in the read unit, storing, in each of the at least one spanning read units that include the first byte of the at least one Lpage starting in the read unit, an Lpage identification header per each of the at least one Lpages starting in the spanning read unit, each Lpage identification header identifying a location of the first byte of the respective Lpage starting within the respective spanning read unit, and locating an Lpage of data stored in the NVM by referring to an entry stored a flash memory controller map table.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: September 20, 2022
    Assignee: Seagate Technology LLC
    Inventor: Earl T. Cohen
  • Patent number: 11449244
    Abstract: A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information are provided. The method may include: sending internal information of the memory device to a host device, to allow the host device to store the internal information of the memory device in a memory within the host device as host side table information at the host device; generating and storing multiple entries of at least one address mapping control table into a random access memory (RAM) as at least one portion of device side table information at the memory device; determining at least two physical addresses associated with at least two logical addresses according to the at least one address mapping control table; and reading data from the NV memory according to the at least two physical addresses.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: September 20, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Yu-Ta Chen
  • Patent number: 11442628
    Abstract: A data processing system includes a host configured to handle data in response to an input received by the host, and a plurality of memory systems engaged with the host and configured to store or output the data in response to a request generated by the host. A first memory system among the plurality of memory systems can perform generation, erasure, or updating of metadata for the plurality of memory systems.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventor: Ik-Sung Oh
  • Patent number: 11442662
    Abstract: A data writing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes: receiving a write command from a host system; and determining whether to write a data corresponding to the write command into a first area or a second area according to a write amplification factor of the first area, where if it is determined to write the data into the second area, copying the written data to the first area after writing the data.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: September 13, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ping-Chuan Lin, Hsiang-Jui Huang, Ping-Yu Hsieh, Tsung-Ju Wu
  • Patent number: 11443217
    Abstract: It is possible to perform a stochastic process based on a metropolis algorithm while reducing a physical quantity of a circuit. Provided is an information processing apparatus including one or a plurality of array circuits. In this apparatus, each of the array circuits includes a plurality of units, and each of the plurality of units includes a first memory that stores a value indicating a state of one node of a coupling model, a second memory that stores a coupling coefficient indicating coupling from a node of another unit connected to an unit of the second memory, and a logic circuit that determines a value indicating a subsequent state of the one node based on a value indicating a state of the node of the other unit and the coupling coefficient. Further, the logic circuit sets a first random variable in accordance with an exponential distribution of a parameter ? as an input.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: September 13, 2022
    Assignee: Hitachi, Ltd.
    Inventors: Takuya Okuyama, Masato Hayashi, Masanao Yamaoka
  • Patent number: 11442525
    Abstract: Methods of operating a die might include determining an expected peak current magnitude of the die for a period of time, and outputting the expected peak current magnitude from the die prior to completion of the period of time. Apparatus might be configured to perform similar methods.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Xiaojiang Guo
  • Patent number: 11443811
    Abstract: A data erase operation is performed on the memory system. The directed data erase operation performed on the memory system erases blocks of the memory device including blocks that are indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as valid without erasing those groups of memory cells (e.g., blocks) indicated as invalid. In some embodiments, a data erase operation that can be performed on a memory system may obtain information associated with failing scenes of groups of memory cells (e.g., blocks) prior to obtaining the information, and erase the blocks (e.g., invalid blocks) subsequently.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Brandt, Adam J. Hieb, Jonathan Tanguy, Preston A. Thomson
  • Patent number: 11442950
    Abstract: Disclosed methods and systems allow a central server to monitor electronic units of work accessible to a group of computers and generate a nodal data structure representing the units of work. The server then uses various protocols, such as hashing algorithms and/or executing artificial intelligence and machine learning models to identify similar and/or related units of work. The server then merges/links the nodes corresponding to the similar/related units of work. The server also monitors all user activities. When a user or a software system/service accesses electronic content on his, her, or its electronic device, the server identifies a node corresponding to the accessed electronic content and associated unit(s) of work and presents searchable data and actions related to the identified node and any related/linked nodes.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: September 13, 2022
    Assignee: COMAKE, INC.
    Inventors: Andres Gutiérrez, Adler Faulkner
  • Patent number: 11436136
    Abstract: According to one embodiment, a memory system includes a non-volatile memory including first and second block groups, and a controller that performs a first write operation for the first block group and the first or a second write operation for the second block group. A first or second number of bits is written into a memory cell in the first or the second write operation. The second number of bits is larger than the first number of bits. The controller allocates a block to a buffer as a write destination block in the first write operation based on a degree of wear-out of at least one block, and writes data from an external device into the buffer in the first write operation.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: September 6, 2022
    Assignee: Kioxia Corporation
    Inventors: Takehiko Amaki, Toshikatsu Hida, Shunichi Igahara, Yoshihisa Kojima, Suguru Nishikawa
  • Patent number: 11436101
    Abstract: According to one general aspect, an apparatus may include a storage element configured to store both data and metadata, wherein each piece of data is associated with and stored with a corresponding piece of metadata. The apparatus may include a controller processor. The controller processor may be configured to, in response to a piece of data being written to the apparatus: generate a piece of metadata that includes a set of parameters to facilitate a at least partial repair of a block information map, and embed the piece of metadata with the corresponding piece of data.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: September 6, 2022
    Inventors: Jian Zhao, Hui-Juan Li, Rong Zheng
  • Patent number: 11436148
    Abstract: A memory controller may include a host interface controller, a first queue, a second queue, and a cache memory. The host interface controller may be configured to generate, based on a request received from a host, one or more command segments corresponding to the request. The first queue may be configured to store the one or more command segments. The second queue may be configured to store a target command segment from among the one or more command segments. The memory controller caches a target map segment corresponding to the target command segment into the cache memory in response to the target command segment being transferred from the first queue to the second queue.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: September 6, 2022
    Assignee: SK hynix Inc.
    Inventor: Gi Jo Jeong
  • Patent number: 11437095
    Abstract: According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: September 6, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Noboru Shibata, Yasuyuki Matsuda
  • Patent number: 11436367
    Abstract: A technique includes, in a pre-operating system environment of a computer system, a hardware processor of the computer system executing machine executable instructions to determine whether a sanitization option was selected in a prior operating system environment of the computer system. In response to determining that the sanitization option was selected, the hardware processor executes the instructions in the pre-operating system environment to determine, for an adapter of the computer system, a storage inventory associated with the adapter and sanitize the storage inventory.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: September 6, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sriram Subramanian, Scotty M. Wiginton
  • Patent number: 11437103
    Abstract: A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Minucci, Tommaso Vali, Fernanda Irrera, Luca De Santis
  • Patent number: 11435902
    Abstract: A flash translation layer method, system, and computer program product, include performing a virtualization of a meta-flash translation layer by: instantiating a range in a NAND chip comprising the number of free blocks using a meta-FTL to create a compatible range of blocks for a type of a feature and a flash characteristic of a translation table if a number of free blocks are available in the NAND chip and instantiating a second range in the NAND chip comprising a second number of free blocks using the meta-FTL to create a second compatible range of blocks for a second type of feature and a second flash characteristic of the translation table, and dynamically programming data on the fly based on an input requirement of a request into the range and the second range.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: September 6, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kaoutar El Maghraoui, Hubertus Franke, Hillery C. Hunter, Gokul Bhargava Kandiraju, Hartmut Erhard Penner
  • Patent number: 11436140
    Abstract: A memory system may include a memory device including a plurality of memory blocks and a controller suitable for determining whether to change from a normal mode to a dirty mode based on a size of free space of a host a sum of an amount of restoration of garbage collection for victim blocks and a size of all free blocks in the memory device. In the dirty mode, the controller controls the memory device to perform a garbage collection operation on the victim blocks at a frequency greater than frequency at which a garbage collection operation is performed in the normal mode.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: September 6, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyeong Ju Na
  • Patent number: 11435908
    Abstract: Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: September 6, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: YungLi Ji, Yun-Tzuo Lai, Haining Liu, Yuriy Pavlenko
  • Patent number: 11435903
    Abstract: The present disclosure provides an operating method of a storage controller. The operating method includes receiving user data and environmental information, obtaining logical-characteristic information and physical-characteristic information, defining a current state, obtaining expectation values, and performing a write operation. User data and environmental information is received from a non-volatile memory. The current state may be defined based on the logical-characteristic information and the physical-characteristic information. Expectation values may be obtained based on policy information and the current state. The write operation may be performed on the user data through a physical stream corresponding to a maximum value among the expectation values.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: September 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungjun Yang, Kibeen Jung, Byeonghui Kim, Jungmin Seo
  • Patent number: 11435943
    Abstract: A storage device includes a memory device and a controller. The memory device stores attribute information associated with a host memory buffer allocated on a host memory. The controller communicates with the host memory such that a plurality of pieces of data associated with operations of the memory device is buffered, based on the attribute information, in a plurality of host memory buffers allocated on the host memory. The controller communicates with the host memory such that first data corresponding to a first attribute group managed in the attribute information is buffered in a first host memory buffer among the plurality of host memory buffers and second data corresponding to a second attribute group different from the first attribute group is buffered in a second host memory buffer separate from the first host memory buffer.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: September 6, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jison Im, Hyunseok Kim, Hyun-Sik Yun, Hoju Jung
  • Patent number: 11436023
    Abstract: A method of operating a storage system is provided. The method includes executing an operating system on one or more processors of a compute device that is coupled to one or more solid-state drives and executing a file system on the one or more processors of the compute device. The method includes configuring the compute device with one or more replaceable plug-ins that are specific to the one or more solid-state drives, and executing a flash translation layer on the one or more processors of the compute device, with assistance through the one or more replaceable plug-ins for reading and writing the one or more solid-state drives.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: September 6, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Russell Sears, Hari Kannan, Yuhong Mao
  • Patent number: 11435945
    Abstract: According to one embodiment, a memory apparatus includes a memory device and a controller. The memory device includes a plurality of memory chips. The controller includes a plurality of memories. The controller determines whether or not the memory chip is allocated to any one memory when receiving an access request related to the memory chip from a host apparatus. The controller newly allocates the memory chip to the memory to which none of the memory chips is allocated when it is determined that the memory chips is not allocated, and enqueues a command corresponding to the access request received from the host apparatus to the memory to which the memory chip is newly allocated.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: September 6, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Hajime Yamazaki, Mitsunori Tadokoro
  • Patent number: 11429306
    Abstract: A comparison unit configured to compare volume of unnecessary data of a first semiconductor memory to a threshold of the first semiconductor memory, which is set in advance, and a transmission unit configured to transmit a delete command to the first semiconductor memory in accordance with a comparison result indicating that the volume of the unnecessary data of the first semiconductor memory is larger than the threshold of the first semiconductor memory are provided, and the transmission unit transmits a delete command to the second semiconductor memory upon transmission of the delete command to the first semiconductor memory.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: August 30, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takehiro Ito
  • Patent number: 11429519
    Abstract: During operation, the system receives a chunk of data to be written to a non-volatile memory, wherein the chunk includes a plurality of sectors. The system assigns consecutive logical block addresses (LBAs) to the plurality of sectors. In response to determining that a first sector is associated with an existing stream for the chunk, the system appends the first sector to one or more other sectors stored in a first buffer associated with the existing stream. The system detects that a total size of the stored sectors in the first buffer is the same as a first size of a physical page in the non-volatile memory. The system writes the stored sectors from the first buffer to the non-volatile memory at a first physical page address. The system creates, in a data structure, a first entry which maps the LBAs of the written sectors to the first physical page address.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 30, 2022
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 11430538
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes: executing a single page encoding operation on first data stored in a first type physical unit to generate local parity data; executing a global encoding operation on second data stored in at least two of the first type physical unit, a second type physical unit, and a third type physical unit to generate global parity data; reading the second data from the at least two of the first type physical unit, the second type physical unit, and the third type physical unit in response to a failure of a single page decoding operation for the first data; and executing a global decoding operation on the second data according to the global parity data.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: August 30, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Pochiao Chou, Cheng-Che Yang
  • Patent number: 11429279
    Abstract: A storage device is disclosed. The storage device may include storage for data. A host interface logic may receive a dataset and a logical address from a host. A stream assignment logic may assign a stream identifier (ID) to a compressed dataset based on a compression characteristic of the compressed dataset. The stream ID may be one of at least two stream IDs; the compressed dataset may be determined based on the dataset. A logical-to-physical translation layer may map the logical address to a physical address in the storage. A controller may store the compressed dataset at the physical address using the stream ID.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: August 30, 2022
    Inventors: Jingpei Yang, Jing Yang, Rekha Pitchumani
  • Patent number: 11429483
    Abstract: A processing device performs operations including receiving a request to locate one or more distribution edges of one or more programming distributions of a memory cell, the request specifying a target error rate for the one or more programming distributions, measuring at least one error rate sample of a first programming distribution selected from the one or more programming distributions, and determining a location of a first distribution edge of the first programming distribution at the target error rate based on a comparison of the at least one error rate sample of the first programming distribution against the target error rate.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Larry J. Koudele
  • Patent number: 11429533
    Abstract: A method of reducing FTL address mapping space, including: S1, obtaining a mpa and an offset according to a logical page address; S2, determining whether the mpa is hit in a cache; S3, determining whether a NAND is written into the mpa; S4, performing a nomap load operation, and returning an invalid mapping; S5, performing a map load operation; S6, directly searching a mpci representing a position of the mpa in the cache and searching a physical page address gppa with reference to the offset; S7, determining whether a mapping from a logical address to a physical address needs to be modified; S8, modifying a mapping table corresponding to the mpci in the cache, and marking a mp corresponding to the mpci as a dirty mp; S9, determining whether to trigger a condition of writing the mp into the NAND; and S10, writing the dirty mp into the NAND.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 30, 2022
    Assignee: SHENZHEN UNIONMEMORY INFORMATION SYSTEM LIMITED
    Inventors: Jian Zuo, Yuanyuan Feng, Zhiyuan Leng, Jintao Gan, Weiliang Wang, Zongming Jia
  • Patent number: 11429480
    Abstract: Systems, apparatuses, and methods related to chiplets are described. A chiplet-based system may include a memory controller chiplet to control accesses to a storage array, and the memory controller chiplet can facilitate error correction and cache management in a manner to minimize interruptions to a sequence of data reads to write corrected data from a prior read back into the storage array. For example, a read command may be received at a memory controller device of the memory system from a requesting device. Data responsive to the read command may be obtained and determined to include a correctable error. The data may be corrected, transmitted to the requesting device and written to cache of the memory controller device with an indication that data is valid and dirty (e.g., includes an error or corrected error). The data is written back to the memory array in response to a cache eviction event.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bryan Hornung, David Patrick
  • Patent number: 11429453
    Abstract: Disclosed are various embodiments for replicating and maintaining aggregated descriptive data for cloud services. In one embodiment, updates to descriptive data that describes a resource of a customer provided by a cloud service are received by an aggregated descriptive data service from a backend service. An aggregated descriptive data store is then updated by the aggregated descriptive data service based at least in part on the received updates.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: August 30, 2022
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Richard Hamman, Kevin Pakiry, Gareth Lennox, Fernand Sieber, Thomas George Mathew, Pavel Tcholakov, Graeme Kruger, Bhavani Morarjee, Tarek Khaled Ismail Eltalawy, Sara Mohamed Ali, Paul Maree
  • Patent number: 11429528
    Abstract: Methods, systems, and devices for a split cache for address mapping data are described. A memory system may include a cache (e.g., including a first and second portion) for storing data that indicates a mapping between logical addresses associated with a host system and physical addresses of the memory system. The memory system may store data (e.g., the address mapping data) within the first portion of the cache. Additionally, the memory system may store an indication of whether the data is used for any access operations during a duration that the data is stored in the first portion of the cache. The memory system may transfer subsets of the data to the second portion of the cache if they are used for access operations during the duration.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Nicola Colella, Antonino Pollio
  • Patent number: 11422714
    Abstract: Optimizing copy operations in a storage array, including: receiving a plurality of copy operations; detecting a triggering event that causes a storage array controller to initiate execution of the plurality of copy operations; and combining, in dependence upon a metadata optimization policy, the plurality of copy operations into a single copy operation.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: August 23, 2022
    Assignee: PURE STORAGE, INC.
    Inventors: Christopher Golden, Scott Smith, Luke Paulsen, David Grunwald, Jianting Cao
  • Patent number: 11422538
    Abstract: An information processing device according to the present invention includes: a memory; and at least one processor coupled to the memory. The processor performing operations. The operations includes: constructing second data that is acquired, based on first data containing a plurality of observation values in a plurality of times, by stacking the first data with respect to the times, and extracting a constant pattern that is a combination of the observation values having temporal constancy in the first data, based on the second data; generating a difference between the first data and the constant pattern in the time; and extracting a random pattern that is a combination of the observation values without temporal constancy, based on the difference.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 23, 2022
    Assignee: NEC CORPORATION
    Inventor: Tsubasa Takahashi
  • Patent number: 11422723
    Abstract: A multi-storage device lifecycle management system includes a server computing system having a plurality of devices and an operating system engine. The operating system engine identifies an estimated first device remaining lifetime for a first device, identifies an estimated second device remaining lifetime for a second device, and determines whether a difference between the estimated first device remaining lifetime and the estimated second device remaining lifetime is less than an estimated multi-device minimum end-of-lifetime difference. If so, the computing system distributes workload operations between the first device and the second device in order to cause the difference between the estimated first device remaining lifetime and the estimated second device remaining lifetime to be greater than or equal to the estimated multi-device minimum end-of-lifetime difference.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: August 23, 2022
    Assignee: Dell Products L.P.
    Inventors: Wei Dong, Haifang Zhai
  • Patent number: 11423976
    Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jeremy Binfet, Mark Helm, William Filipiak, Mark Hawes
  • Patent number: 11422746
    Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: August 23, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Suguru Nishikawa, Yoshihisa Kojima, Takehiko Amaki