Solid-state Read Only Memory (rom) Patents (Class 711/102)
  • Patent number: 11222671
    Abstract: A method is for operating a nonvolatile dual in-line memory module (NVDIMM). The NVDIMM includes a dynamic random access memory (DRAM) and a nonvolatile memory (NVM) device, the DRAM including a first input/output (I/O) port and a second I/O port, and the second I/O port connected to the NVM device. The method includes receiving an externally supplied command signal denoting a read/write command and a transfer mode, driving a multiplexer to select at least one of the first and second I/O ports according to the transfer mode of the command signal, and reading or writing data according to the read/write command of the command signal in at least one of the DRAM and NVM device using the at least one of the first and second I/O ports selected by driving the multiplexer.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: January 11, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunyoung Lim, Jaegon Lee
  • Patent number: 11200925
    Abstract: A programmable memory device includes a read only memory (ROM) block to store instructions associated with functionality of the programmable memory device. The device includes a memory array having a set of reserved pages to store updates to be performed on the ROM block. The device includes a controller coupled to the ROM block and the memory array. The controller is to execute the instructions to: execute a set features command; program, in execution of the set features command, a set of sub-feature parameters to a specified feature address of the set of reserved pages, wherein the set of sub-feature parameters are to trigger operation within a ROM-emulated memory (REM) profile mode; and program a REM-profiled page of the set of reserved pages with REM data received from a host system.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan Wen Jian Oh, Aaron James Olson, Fulvio Rori, Qisong Lin, Preston A. Thomson
  • Patent number: 11200159
    Abstract: The system receives a request to write data and associated metadata. The system determines a key associated with the data, wherein the key corresponds to an entry in a data structure maintained by a first storage system. The system writes the metadata to a first non-volatile memory of a first set of storage drives of the first storage system by updating the entry with a logical block address for the data and a physical location in a second set of storage drives of a second storage system. The system writes the key and the data to a second non-volatile memory of the second set of storage drives based on the physical location, wherein the first non-volatile memory is of a lower density than the second non-volatile memory.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 14, 2021
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 11164650
    Abstract: A method and system for collecting diagnostic data from a storage class memory chip is disclosed. The method includes performing a scrub process on at least a portion of the storage class memory by: removing the portion of the storage class memory from use, wherein the portion comprises a plurality of memory locations, executing a first write operation to write a first pattern on each of the plurality of memory locations, executing a first read operation to obtain a first set of data written on each of the plurality of memory locations, analyzing the first set of data written on each of the plurality of memory locations to determine the number of stuck-at faults in the portion, and updating one or more counters in an error rate table (ERT) to indicate the number of stuck-at faults.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Robert Edward Galbraith, Damir Anthony Jamsek, Andrew Kenneth Martin, Daniel Frank Moertl, Charles Camp
  • Patent number: 11164641
    Abstract: One or more write operations are performed on a memory component. A determination is made as to whether a number of the plurality of write operations performed on the memory component since performance of a refresh operation on the memory component exceeds a threshold value. In response to determining that the number of write operations performed on the memory component exceeds the threshold value, a memory cell of the memory component is identified based on the plurality of write operations. Data stored at memory cells of the memory component that are proximate to the identified memory cell is refreshed.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: November 2, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Fangfang Zhu, Jiangli Zhu, Ying Yu Tai
  • Patent number: 11157640
    Abstract: Sensitive data is protected in a software product. A source file of the software product is compiled to generate an object file, in which the source file includes at least one piece of sensitive data marked with a specific identifier. The object file has a secure data section for saving storage information of the at least one piece of sensitive data at compile-time and run-time. The object file is linked to generate an executable file. The executable file updates the secure data section at run-time. Sensitive data is also protected when a core dump is generated.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Rui Feng, Shuang Shuang Jia, Da Fei Shi, Lijun Wei
  • Patent number: 11139035
    Abstract: A memory device may include memory cells configured to establish multiple levels of charge distributions; and a memory controller configured to perform operations on the memory cells. The operations may include recording a bit count number for a highest level of charge distributions within a set of memory cells, recording a bit count number for a lowest level of charge distributions within the set of memory cells, counting bits for the highest level of charge distributions within the set of memory cells, counting bits in the lowest level of charge distributions within the set of memory cells, comparing the counted bits for the highest level to the recorded bit count number for the highest level, and comparing the counted bits for the lowest level to the recorded bit count number for the lowest level.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Giuseppe Cariello
  • Patent number: 11126463
    Abstract: A system for providing a function as a service (FaaS) is provided. The system includes a communicator which receives a request for setting resources to execute the function, a memory which stores one or more instructions, and a processor. The processor executes the stored instructions. When the processor executes the instructions, it analyzes characteristics of the function and provides recommendation information related to the setting of the resources to execute the function based on a result of the analyzing.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keun-seob Kim, Jin-woo Song, Hong-uk Woo
  • Patent number: 11113002
    Abstract: A data storage device includes a controller configured to recognize commands received from a host as single logical address (LA) commands or multi-LA commands. The data storage drive also includes a command overlap detection table having a plurality of records with each record configured to store multiple unrelated LAs associated with different single LA commands and configured to store multiple related LAs associated with a single multi-LA command.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 7, 2021
    Assignee: Seagate Technology LLC
    Inventor: Thomas V. Spencer
  • Patent number: 11112997
    Abstract: An operating method of a storage device which includes a first nonvolatile memory device and a second nonvolatile memory device includes detecting sudden power-off, suspending an operation being performed in the first nonvolatile memory device, in response to the detected sudden power-off, writing suspension information about the suspended operation into the second nonvolatile memory device, and performing a block management operation on the first nonvolatile memory device based on the suspension information written into the second nonvolatile memory device, in power-up after the sudden power-off.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taehyun Kim, Chankyung Kim, Sang-won Shim, Suk-Soo Pyo
  • Patent number: 11106539
    Abstract: Systems and methods for determining retention periods or policies for backups are disclosed. A rule book stores relationships between rules and recommended retention periods. Data related to a backup is collected and organized. A query is generated from the organized data and used to identify a rule from the rule book. The retention period corresponding to the identified rule in the rule book is then applied to the corresponding backup.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 31, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mahesh Reddy Av, Gururaj Kulkarni, Swaroop Shankar D H, Lakshminarayanan Muniswamy
  • Patent number: 11093141
    Abstract: Embodiments of the present disclosure relate to methods and apparatuses for caching data. A method comprises writing data into a first cache module on a first processor in response to receiving a first request for caching the data from a client module running on the first processor. The method further comprises transmitting, to the client module, a first indication that the data has been written into the first cache module. The method further comprises, in response to receiving from the client module a second request for synchronizing the data to a second processor, transmitting to the second processor a first command for causing the data to be written into a second cache module on the second processor. In addition, the method further comprises transmitting to the client module a second indication that the data has been synchronized.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: August 17, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Yousheng Liu, Jian Gao, Xinlei Xu, Ruiyong Jia, Changyu Feng
  • Patent number: 11029868
    Abstract: A initialization code/data memory mapping system includes a processing system, memory device(s) storing initialization code and initialization data, and a main memory system. The processing system performs first MMIO read operations to access the initialization code stored in the memory device(s) that is mapped to an initialization memory space in order to provide an initialization engine, and uses it to copy the initialization code from the memory device(s) to the main memory system. The processing system then accesses the initialization code stored in the main memory system in order to provide the initialization engine, and uses it to map the initialization data stored in the memory device(s) to the initialization memory space. The processing system then performs second MMIO read operations to access the initialization data stored in the memory device(s) that is mapped to the initialization memory space for use by the initialization engine.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: June 8, 2021
    Assignee: Dell Products L.P.
    Inventors: Wei Liu, Po-Yu Cheng
  • Patent number: 11029881
    Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: June 8, 2021
    Assignee: SONY CORPORATION
    Inventors: Ken Ishii, Hiroyuki Iwaki, Kenichi Nakanishi, Yasushi Fujinami, Tatsuo Shinbashi
  • Patent number: 11030091
    Abstract: A semiconductor storage device exhibiting improved programming reliability is provided. In the disclosure, flash memory includes a storage controller and a NAND type storage device. The storage controller includes a voltage detecting part, SRAM, RRAM, and a writer/selector. The voltage detecting part detects whether a power supply voltage drops to a fixed voltage. The SRAM stores a conversion table for converting a logical address into a physical address. The RRAM stores the logical address of a block and a page currently being programmed and conversion information for converting the logical address into another physical address when the fixed voltage is detected by the voltage detecting part during a programming process. The writer/selector converts the inputted logical address into the physical address according to the conversion table or the conversion information of the RRAM and programs data on the page of the block selected according to the converted physical address.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: June 8, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Norio Hattori
  • Patent number: 11029892
    Abstract: A memory control apparatus includes a first memory, a second memory, a third memory, and a processor configured to add, to management information, first identification information and information indicating a position where first data is stored when the first data is stored in the first memory, add, to the management information, the first identification information and information indicating a position where second data is stored when the second data is stored in the second memory, add, to the management information, second identification information and information indicating a position where third data is stored when the third data is stored in the third memory, determine which one of the first identification information and the second identification information is associated with fourth data, and perform retrieval of the fourth data from the first memory or the second memory in accordance with information indicating a position where the fourth data is stored.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: June 8, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Satoshi Kazama, Shinya Kuwamura
  • Patent number: 11003483
    Abstract: A request to initiate a launch procedure of a compute instance at a virtualization host configured to access a remote storage device over a network is received. A memory buffer of the host is allocated as a write-back cache for use during a portion of the launch procedure. In response to a write request directed to remote storage during the portion of the launch procedure, the write payload is stored in the buffer and an indication of fulfillment of the write is provided independently of obtaining an acknowledgement that the payload has been propagated to the remote storage. Subsequent to the portion of the launch procedure, payloads of other write requests are transmitted to the remote storage device.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 11, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Marcin Kowalski, Karel Scott
  • Patent number: 10996881
    Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device may include a memory device including buffer blocks and main blocks, and a memory controller configured to control the memory device. The memory controller may include: a buffer block controller configured to control the memory device to store, in at least one of the main blocks, data stored in at least one of the buffer blocks; a mapping table manager configured to generate a P2P mapping table including mapping information between a buffer address that is a physical address of the at least one buffer block and a main address that is a physical address of the at least one main block; and a read operation controller configured to control, when a read request is received, the memory device to read the data based on the main address or the buffer address.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Seung Wan Jung, So Hee Kim, Seung Ok Han
  • Patent number: 10990311
    Abstract: A non-volatile storage apparatus (e.g., an SSD, embedded memory, memory card, etc.) comprises non-volatile memory (e.g., one or more memory dies) connected to a control circuit (e.g., controller, state machine, microcontroller, etc.). The non-volatile memory is configured to have multiple regions for storing different types of data using separate streams. The control circuit is configured to receive a request to write data to a logical address, automatically choose a stream (and corresponding destination region) by determining which of the multiple regions/streams has a sequence of logical addresses associated with previous writes that best fits the logical address for the received data, and store the received data in the chosen destination region of the non-volatile memory using the chosen stream.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: April 27, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Vishwas Saxena, Abhijit Rao, Ravi Kumar, Saifullah Nalatwad
  • Patent number: 10990378
    Abstract: A storage device includes a semiconductor memory device including a plurality of memory blocks; and a controller configured to control the semiconductor memory device, wherein the semiconductor memory device stores original firmware as default firmware and one or more copies of the original firmware as pieces of backup firmware in a first memory block among the plurality of memory blocks, and wherein the controller includes a firmware load circuit configured to load the default firmware when the default firmware is valid and load one of the pieces of backup firmware when the default firmware is not valid; and a firmware update circuit configured to update the default firmware from a previously updated version of the original firmware to a currently updated version of the original firmware.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: April 27, 2021
    Assignee: SK hynix Inc.
    Inventor: Sung-Jin Park
  • Patent number: 10991410
    Abstract: A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank and writing a second plurality of data words and associated memory addresses into an error buffer. The method also comprises monitoring a first counter value which tracks a number of write 1 errors and a second counter value which tracks a number of write 0 errors in the memory bank. Further, the method comprises determining if the first counter value and the second counter value have exceeded a predetermined threshold. Responsive to a determination that the first counter value has exceeded the predetermined threshold increasing a write 1 voltage of the memory bank, and, further, responsive to a determination that the second counter value has exceeded the predetermined threshold increasing a write 0 voltage of the memory bank.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: April 27, 2021
    Assignee: Spin Memory, Inc.
    Inventors: Neal Berger, Benjamin Louie, Kadriye Deniz Bozdag
  • Patent number: 10963185
    Abstract: A system comprising a memory component including blocks, and a processing device, operatively coupled with the memory component. The processing device determines endurance values for the memory component. For each selected block of the plurality of blocks, the processing device determines an endurance estimation of the selected block based on at least one of a time to erase the selected block or an error statistic for the selected block, and updates an endurance value associated with the selected block based on the endurance estimation for the selected block. The processing device receives a write instruction to the memory component and distributes the write instruction to one or more of the blocks based on the endurance values. Other embodiments are described.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Zoltan Szubbocsev
  • Patent number: 10956388
    Abstract: One example method includes receiving a write request that includes a data structure version to be written, wherein the data structure version is associated with a unique identifier, storing the data structure version in association with the unique identifier, receiving a read request for a most recent version of the data structure and, when the stored data structure version is not the most recent version of the data structure, examining respective unique identifiers of each of a group of other stored data structure versions to determine which stored data structure version is the most recent. Finally, the example method includes returning the most recent data structure version, notwithstanding that one or more other data structure versions existed at the time that the read request was received.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: March 23, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Philip Shilane, Venkata Ravi Chandra Bandlamudi, Atul A. Karmarkar
  • Patent number: 10956813
    Abstract: An apparatus is described. The apparatus includes a compute in memory circuit. The compute in memory circuit includes a memory circuit and an encoder. The memory circuit is to provide 2m voltage levels on a read data line where m is greater than 1. The memory circuit includes storage cells sufficient to store a number of bits n where n is greater than m. The encoder is to receive an m bit input and convert the m bit input into an n bit word that is to be stored in the memory circuit, where, the m bit to n bit encoding performed by the encoder creates greater separation between those of the voltage levels that demonstrate wider voltage distributions on the read data line than others of the voltage levels.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Ian A. Young, Ram Krishnamurthy, Sasikanth Manipatruni, Gregory K. Chen, Amrita Mathuriya, Abhishek Sharma, Raghavan Kumar, Phil Knag, Huseyin Ekin Sumbul
  • Patent number: 10942845
    Abstract: An in-line (or foreground) approach to obtaining contiguous ranges of free space in a file system of a data storage system that can select windows having blocks suitable for relocation at a time when one or more blocks within the respective windows are freed or de-allocated. By providing the in-line or foreground approach to obtaining contiguous ranges of free space in a file system, a more efficient determination of windows having blocks suitable for relocation can be achieved, thereby conserving processing resources of the data storage system.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: March 9, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Rohit Chawla, Ahsan Rashid, Kumari Bijayalaxmi Nanda, Alexander S. Mathews
  • Patent number: 10936497
    Abstract: In general, embodiments of the technology relate to a method and system for storing and reading data from persistent storage. More specifically, embodiments of the technology relate to a method and system for storing data in persistent storage, where the data written to the persistent storage is not immediately accessible in the persistent storage (i.e., during the inaccessibility period). In such instances, embodiments of the technology provide a method and system to enable the storage system to service read requests for the data using a primary cache entry table (PCET) and an overflow table.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: March 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Todd Wilde, Samir Rajadnya, Karthik Ramachandran, Michael Nishimoto
  • Patent number: 10929030
    Abstract: A computer comprises a controller and a storage apparatus which is configured to provide a storage area for storing data. The controller and the storage apparatus have a function of achieving encryption and decryption of data through use of an encryption key. The computer is configured to: execute encryption key setting processing for setting the encryption key in the controller and the storage apparatus so that the controller holds the same encryption key as the encryption key of the storage apparatus; and determine whether to enable the function of any one of the controller and the storage apparatus, based on load states of the controller and the storage apparatus when an I/O request is received.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: February 23, 2021
    Assignee: HITACHI, LTD.
    Inventor: Koji Washiya
  • Patent number: 10906482
    Abstract: The present invention is a system and method of making setpoint adjustments to a vehicle control computer in a real time manner in order to enable the one performing the programming to observe the changes in vehicle characteristics in real time. The system and method is an improvement over known methods in that it does not require the programmer to repeatedly stop and start the operation of the vehicle in order to verify that any changes have the desired result.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: February 2, 2021
    Assignee: Powerteq LLC
    Inventor: Timothy G. Milliken
  • Patent number: 10875298
    Abstract: In some examples, a fluidic die includes a plurality of fluid actuators, and a controller to determine, based on input control information relating to controlling actuation of the plurality of fluid actuators, whether a first fluid actuator of the plurality of fluid actuators is to be actuated, and in response to determining that the first fluid actuator is to be actuated, activate a delay element associated with the first fluid actuator, the delay element to delay an activation signal propagated to selected fluid actuators of the plurality of fluid actuators in response to an actuation event.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: December 29, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Eric Martin, Daryl E Anderson
  • Patent number: 10860429
    Abstract: Systems and methods for deleting backup pieces associated with an application such as a database application. Backup pieces are identified and deleted from the database records and from the backup application.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: December 8, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Navneet Upadhyay, Amith Ramachandran
  • Patent number: 10783090
    Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: September 22, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegyu Lee, Jisoo Kim, Young-Jin Park, Bo-Ram Shin
  • Patent number: 10783252
    Abstract: System and methods for booting a system-on-chip (SOC) in an enhanced memory mode are described herein. In one aspect, an enhanced memory mode indicator may be read to create a trusted channel to a non-volatile random-access memory (NVRAM). The NVRAM may be logically connected to the SOC. In an aspect, the NVRAM may be secured prior to the creation of the trusted channel. Once the secure channel to NVRAM has been created, the SOC may operate in an enhanced memory mode. Prior to the SOC powering down, the system may store an indicator operable to enable a subsequent boot of the SOC in the power saving mode. The SOC may be operable to switch between the power saving mode and a normal mode depending on the operational requirements of the portable computing device in which the SOC is implemented.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 22, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Yanru Li, Azzedine Touzni, Dexter Chun
  • Patent number: 10776047
    Abstract: Apparatuses and methods related to generating memory characteristic based access commands generating the access commands can include providing a first access command to a memory system of a plurality of memory systems, receiving, at a host coupled to the memory system, data corresponding to characteristics of a memory device of the memory system from a controller of the memory system, where the characteristics are based at least in part on processing of the first access command. Generating access commands can also include generating, at the host, a second access command based on the data and transmitting the second access command to at least the memory system.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Honglin Sun
  • Patent number: 10768828
    Abstract: The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Eugene Feng, Mathew Arcoleo
  • Patent number: 10747687
    Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: August 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegyu Lee, Jisoo Kim, Young-Jin Park, Bo-Ram Shin
  • Patent number: 10734081
    Abstract: A method for implementing pulse-amplitude modulation on a memory device includes configuring a first resistor of a first memory die to a first resistance value. The method also includes configuring a second resistor of a second memory die to a second resistance value. The method also includes receiving, during performance of a read operation, in parallel: two voltage values from the first memory die; and two voltage values from the second memory die. The method also includes determining a first data bit value using the two voltage values from the first memory die. The method also includes determining a second data bit value using the two voltage values from the second memory die.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: August 4, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Nimrod Blatt, Gennady Burdo, Tal Hamias
  • Patent number: 10725849
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if an access request (e.g., a read or write request) to a memory location would result in an integrity failure and, if so determined, read previous data from the memory location, set an indicator to indicate the integrity failure, and store the previous data together with the indicator and previous authentication information. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: David Durham, Siddhartha Chhabra, Kai Cong, Ron Gabor
  • Patent number: 10725790
    Abstract: A method for identifying a boot stage of a BIOS of a computer device is provided. A control terminal receives screen information data indicative of a current BIOS screen image of the computer device, acquires current screen information based on the screen information data, acquires feature vector based on the current screen information, uses an image classification model to classify the current information into a screen category, and generates boot stage information indicative of a boot stage corresponding to the screen category.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: July 28, 2020
    Assignee: MITAC COMPUTING TECHNOLOGY CORPORATION
    Inventors: Jyun-Hong Li, Chi-Hao Kuan
  • Patent number: 10708041
    Abstract: Apparatus and method for hashing a message, comprises using an array of individually selectable memristor cells. The memristor cells are subject to write disturb that affects cells neighboring a selected cell so that a write operation into one cell has a knock-on effect on the neighbors. The array is initiated into a known stable state so that these changes to neighboring cells are predictable according to proximity to the currently selected cell. An inserter sequentially mixes bits with the hash so far to insert bits into successively selected cells of the memristor array and forms a succession of memristor array states including the knock on effects on the neighboring cells. A final resulting memristor array state following input of the bits forms the hash of the message.
    Type: Grant
    Filed: April 29, 2018
    Date of Patent: July 7, 2020
    Assignee: Technion Research & Development Foundation Limited
    Inventors: Shahar Kvatinsky, Leonid Azriel
  • Patent number: 10691376
    Abstract: A computer-implemented method according to one embodiment includes identifying code word interleaved (CWI)-4 entries to be re-written to a data storage cartridge, selecting a subset of the CWI-4 entries to be included within a first CWI-4 set, where a plurality of the CWI-4 entries within the subset are associated with a single sub data set (SDS), and re-writing the first CWI-4 set to the data storage cartridge.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kevin D. Butt, Roy D. Cideciyan, Simeon Furrer, Mark A. Lantz
  • Patent number: 10691459
    Abstract: Converting program instructions for two-stage processors including receiving, by a preprocessing unit, a group of program instructions; determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction; converting, by the preprocessing unit, the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction; and sending, by the preprocessing unit, the single combined instruction to the execution unit.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Giles R. Frazier, Hung Q. Le, Jose E. Moreira, Brian W. Thompto
  • Patent number: 10685720
    Abstract: According to one embodiment, a non-volatile first memory includes a plurality of first storage areas. A second memory stores a plurality of first addresses each is address information of a second storage area. The second storage area is a first storage area in a first state. A third memory stores a counted value for the second storage area. A determiner circuit reads, at a time of a read access to the first memory, at least one of the first addresses and compares the read second address with a third address to determine whether a third storage area is in the first state. The third address indicates a location of the third storage area. The third storage area is a first storage area to be read. An update circuit increments, for the third storage area, the counted value, when the third storage area is in the first state.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 16, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoto Oshiyama
  • Patent number: 10684856
    Abstract: Converting program instructions for two-stage processors including receiving, by a preprocessing unit, a group of program instructions; determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction; converting, by the preprocessing unit, the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction; and sending, by the preprocessing unit, the single combined instruction to the execution unit.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: Giles R. Frazier, Hung Q. Le, Jose E. Moreira, Brian W. Thompto
  • Patent number: 10672486
    Abstract: One or more write operations are performed on a memory component. A determination is made as to whether a number of the plurality of write operations performed on the memory component since performance of a refresh operation on the memory component exceeds a threshold value. In response to determining that the number of write operations performed on the memory component exceeds the threshold value, a memory cell of the memory component is identified based on the plurality of write operations. Data stored at memory cells of the memory component that are proximate to the identified memory cell is refreshed.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 2, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Fangfang Zhu, Jiangli Zhu, Ying Yu Tai
  • Patent number: 10650875
    Abstract: A system for a nonvolatile memory for broad temperature range applications. The system includes a memory organized into an addressable memory range and comprising a plurality of memory arrays comprising memory cells wherein each memory array is configured for operation over a different temperature range, and a buffer for receiving a data word and an associated address for writing into the memory. A temperature sensor is used for sensing a current temperature of operation of the memory. A write controller is coupled to the buffer, the temperature sensor and the memory. The write controller is operable to perform a write operation that includes accessing a temperature value from the temperature sensor, selecting a selected memory array of the plurality of memory arrays that is configured for operation at the temperature value, and writing the data word, at the associated address, to the selected memory array.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 12, 2020
    Assignee: Spin Memory, Inc.
    Inventor: Charles H. Sobey
  • Patent number: 10649895
    Abstract: Common microcontroller unit (MCU) self-identification information is disclosed. In one embodiment, an MCU is contained in a package. The MCU includes a central processing unit (CPU) and a non-volatile memory. This non-volatile memory stores information specific to the MCU and/or the package. The non-volatile memory also stores a common main program that, when executed by the CPU, accesses the information. The information enables the common main program to adapt itself to resources of the MCU and/or package that are identified in the information.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: May 12, 2020
    Assignee: Renesas Electronics America Inc.
    Inventors: Jon Matthew Brabender, Bernd Willi Westhoff
  • Patent number: 10621059
    Abstract: A computer implemented method comprises detecting a failure of a primary volume at a first location, the primary volume having data stored on a first plurality of media according to a first heat map; in response to detecting the failure of the primary volume, overwriting a second heat map of a secondary volume at a second location with a copy of the first heat map, the secondary volume having data stored on a second plurality of media according to the second heat map; migrating extents of data on the second plurality of media at the second location according to the copy of the first heat map prior to a next heat map cycle update after detection of the failure; and processing data access requests from the secondary location using the extents of data on the secondary plurality of media migrated according to the copy of the first heat map.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kushal Patel, Sarvesh Patel, Wendy Lyn Henson, Joseph Thie
  • Patent number: 10607955
    Abstract: A device may include a fan-out structure that has a plurality of integrated circuits. The integrated circuits may be of different types, such as by being configured differently or configured to perform different functions. The fan-out structure may be coupled to another integrated circuit structure, such as a die stack. For example, the fan-out structure may be coupled to a top surface or a bottom surface of the integrated circuit structure, or may otherwise be disposed within a vertical profile defined by the integrated circuit structure. Horizontally-extending and vertically-extending paths may be disposed in between and around the combined fan-out structure and integrated circuit structure to enable the integrated circuits of the two structures to communicate.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 31, 2020
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Chin-Tien Chiu, Chih-Chin Liao, Weiting Jiang, Hem Takiar
  • Patent number: 10608615
    Abstract: A semiconductor device may include a master latch that stores an input data signal, using a local power supply voltage and a clock signal, and outputs the input data signal to a first output signal; a slave latch that stores the first output signal, using a global power supply voltage, the clock signal and a retention signal, and outputs a second output signal; a first logic gate that receives input of one signal and another signal of the retention signal, the clock signal and the reset signal, and outputs a first control signal generated by performing a first logical operation; and a second logic gate that receives input of the rest of the retention signal, the clock signal and the reset signal, and the first control signal, and performs a second logical operation to at least one of the master latch and the slave latch.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: March 31, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Woo Kim, Ju Hyun Kang, Min Su Kim, Ka Ram Lee
  • Patent number: 10599485
    Abstract: A computer implemented method includes receiving multiple requests to update a data structure stored in non-volatile memory (NVM) and applying an atomic multiword update to the data structure to arbitrate access to the NVM. In a further embodiment, a computer implemented method includes allocating a descriptor for a persistent multi-word compare-and-swap operation (PMwCAS), specifying targeted addresses of words to be modified, returning an error if one of the targeted addresses contains a value not equal to a corresponding compare value, executing the operation atomically if the targeted addresses contain values that match the corresponding compare values, and aborting the operation responsive to the returned error.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 24, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Justin J Levandoski, Umar Farooq Minhas, Per-Ake Larson, Tianzheng Wang, Joy James Prabhu Arulraj