Solid-state Read Only Memory (rom) Patents (Class 711/102)
  • Patent number: 10734081
    Abstract: A method for implementing pulse-amplitude modulation on a memory device includes configuring a first resistor of a first memory die to a first resistance value. The method also includes configuring a second resistor of a second memory die to a second resistance value. The method also includes receiving, during performance of a read operation, in parallel: two voltage values from the first memory die; and two voltage values from the second memory die. The method also includes determining a first data bit value using the two voltage values from the first memory die. The method also includes determining a second data bit value using the two voltage values from the second memory die.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: August 4, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Nimrod Blatt, Gennady Burdo, Tal Hamias
  • Patent number: 10725790
    Abstract: A method for identifying a boot stage of a BIOS of a computer device is provided. A control terminal receives screen information data indicative of a current BIOS screen image of the computer device, acquires current screen information based on the screen information data, acquires feature vector based on the current screen information, uses an image classification model to classify the current information into a screen category, and generates boot stage information indicative of a boot stage corresponding to the screen category.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: July 28, 2020
    Assignee: MITAC COMPUTING TECHNOLOGY CORPORATION
    Inventors: Jyun-Hong Li, Chi-Hao Kuan
  • Patent number: 10725849
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if an access request (e.g., a read or write request) to a memory location would result in an integrity failure and, if so determined, read previous data from the memory location, set an indicator to indicate the integrity failure, and store the previous data together with the indicator and previous authentication information. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: David Durham, Siddhartha Chhabra, Kai Cong, Ron Gabor
  • Patent number: 10708041
    Abstract: Apparatus and method for hashing a message, comprises using an array of individually selectable memristor cells. The memristor cells are subject to write disturb that affects cells neighboring a selected cell so that a write operation into one cell has a knock-on effect on the neighbors. The array is initiated into a known stable state so that these changes to neighboring cells are predictable according to proximity to the currently selected cell. An inserter sequentially mixes bits with the hash so far to insert bits into successively selected cells of the memristor array and forms a succession of memristor array states including the knock on effects on the neighboring cells. A final resulting memristor array state following input of the bits forms the hash of the message.
    Type: Grant
    Filed: April 29, 2018
    Date of Patent: July 7, 2020
    Assignee: Technion Research & Development Foundation Limited
    Inventors: Shahar Kvatinsky, Leonid Azriel
  • Patent number: 10691376
    Abstract: A computer-implemented method according to one embodiment includes identifying code word interleaved (CWI)-4 entries to be re-written to a data storage cartridge, selecting a subset of the CWI-4 entries to be included within a first CWI-4 set, where a plurality of the CWI-4 entries within the subset are associated with a single sub data set (SDS), and re-writing the first CWI-4 set to the data storage cartridge.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kevin D. Butt, Roy D. Cideciyan, Simeon Furrer, Mark A. Lantz
  • Patent number: 10691459
    Abstract: Converting program instructions for two-stage processors including receiving, by a preprocessing unit, a group of program instructions; determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction; converting, by the preprocessing unit, the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction; and sending, by the preprocessing unit, the single combined instruction to the execution unit.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Giles R. Frazier, Hung Q. Le, Jose E. Moreira, Brian W. Thompto
  • Patent number: 10684856
    Abstract: Converting program instructions for two-stage processors including receiving, by a preprocessing unit, a group of program instructions; determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction; converting, by the preprocessing unit, the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction; and sending, by the preprocessing unit, the single combined instruction to the execution unit.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: Giles R. Frazier, Hung Q. Le, Jose E. Moreira, Brian W. Thompto
  • Patent number: 10685720
    Abstract: According to one embodiment, a non-volatile first memory includes a plurality of first storage areas. A second memory stores a plurality of first addresses each is address information of a second storage area. The second storage area is a first storage area in a first state. A third memory stores a counted value for the second storage area. A determiner circuit reads, at a time of a read access to the first memory, at least one of the first addresses and compares the read second address with a third address to determine whether a third storage area is in the first state. The third address indicates a location of the third storage area. The third storage area is a first storage area to be read. An update circuit increments, for the third storage area, the counted value, when the third storage area is in the first state.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 16, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoto Oshiyama
  • Patent number: 10672486
    Abstract: One or more write operations are performed on a memory component. A determination is made as to whether a number of the plurality of write operations performed on the memory component since performance of a refresh operation on the memory component exceeds a threshold value. In response to determining that the number of write operations performed on the memory component exceeds the threshold value, a memory cell of the memory component is identified based on the plurality of write operations. Data stored at memory cells of the memory component that are proximate to the identified memory cell is refreshed.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 2, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Fangfang Zhu, Jiangli Zhu, Ying Yu Tai
  • Patent number: 10649895
    Abstract: Common microcontroller unit (MCU) self-identification information is disclosed. In one embodiment, an MCU is contained in a package. The MCU includes a central processing unit (CPU) and a non-volatile memory. This non-volatile memory stores information specific to the MCU and/or the package. The non-volatile memory also stores a common main program that, when executed by the CPU, accesses the information. The information enables the common main program to adapt itself to resources of the MCU and/or package that are identified in the information.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: May 12, 2020
    Assignee: Renesas Electronics America Inc.
    Inventors: Jon Matthew Brabender, Bernd Willi Westhoff
  • Patent number: 10650875
    Abstract: A system for a nonvolatile memory for broad temperature range applications. The system includes a memory organized into an addressable memory range and comprising a plurality of memory arrays comprising memory cells wherein each memory array is configured for operation over a different temperature range, and a buffer for receiving a data word and an associated address for writing into the memory. A temperature sensor is used for sensing a current temperature of operation of the memory. A write controller is coupled to the buffer, the temperature sensor and the memory. The write controller is operable to perform a write operation that includes accessing a temperature value from the temperature sensor, selecting a selected memory array of the plurality of memory arrays that is configured for operation at the temperature value, and writing the data word, at the associated address, to the selected memory array.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 12, 2020
    Assignee: Spin Memory, Inc.
    Inventor: Charles H. Sobey
  • Patent number: 10621059
    Abstract: A computer implemented method comprises detecting a failure of a primary volume at a first location, the primary volume having data stored on a first plurality of media according to a first heat map; in response to detecting the failure of the primary volume, overwriting a second heat map of a secondary volume at a second location with a copy of the first heat map, the secondary volume having data stored on a second plurality of media according to the second heat map; migrating extents of data on the second plurality of media at the second location according to the copy of the first heat map prior to a next heat map cycle update after detection of the failure; and processing data access requests from the secondary location using the extents of data on the secondary plurality of media migrated according to the copy of the first heat map.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kushal Patel, Sarvesh Patel, Wendy Lyn Henson, Joseph Thie
  • Patent number: 10607955
    Abstract: A device may include a fan-out structure that has a plurality of integrated circuits. The integrated circuits may be of different types, such as by being configured differently or configured to perform different functions. The fan-out structure may be coupled to another integrated circuit structure, such as a die stack. For example, the fan-out structure may be coupled to a top surface or a bottom surface of the integrated circuit structure, or may otherwise be disposed within a vertical profile defined by the integrated circuit structure. Horizontally-extending and vertically-extending paths may be disposed in between and around the combined fan-out structure and integrated circuit structure to enable the integrated circuits of the two structures to communicate.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 31, 2020
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Chin-Tien Chiu, Chih-Chin Liao, Weiting Jiang, Hem Takiar
  • Patent number: 10608615
    Abstract: A semiconductor device may include a master latch that stores an input data signal, using a local power supply voltage and a clock signal, and outputs the input data signal to a first output signal; a slave latch that stores the first output signal, using a global power supply voltage, the clock signal and a retention signal, and outputs a second output signal; a first logic gate that receives input of one signal and another signal of the retention signal, the clock signal and the reset signal, and outputs a first control signal generated by performing a first logical operation; and a second logic gate that receives input of the rest of the retention signal, the clock signal and the reset signal, and the first control signal, and performs a second logical operation to at least one of the master latch and the slave latch.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: March 31, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Woo Kim, Ju Hyun Kang, Min Su Kim, Ka Ram Lee
  • Patent number: 10599485
    Abstract: A computer implemented method includes receiving multiple requests to update a data structure stored in non-volatile memory (NVM) and applying an atomic multiword update to the data structure to arbitrate access to the NVM. In a further embodiment, a computer implemented method includes allocating a descriptor for a persistent multi-word compare-and-swap operation (PMwCAS), specifying targeted addresses of words to be modified, returning an error if one of the targeted addresses contains a value not equal to a corresponding compare value, executing the operation atomically if the targeted addresses contain values that match the corresponding compare values, and aborting the operation responsive to the returned error.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 24, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Justin J Levandoski, Umar Farooq Minhas, Per-Ake Larson, Tianzheng Wang, Joy James Prabhu Arulraj
  • Patent number: 10558615
    Abstract: Augmenting data files in a repository of an append-only file system includes maintaining a companion metadata file for each corresponding data file in a map-reduce system using the append-only file system. Each companion metadata file tracks a logical end-of-file (EOF) for each data file. Global versioning of each companion metadata is maintained. A map-reduce append job is performed for a set of data files using a current global version number for the companion metadata file. The map-reduce job including multiple append tasks. For each successful append job, a logical EOF for each appended file is incremented to a new physical EOF. For each failed append task of the append job, a logical EOF is maintained for each failed append task by not incrementing the logical EOF for each failed append task.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventor: Sandeep Tata
  • Patent number: 10552314
    Abstract: According to one embodiment, a memory system includes a non-volatile first memory, and a controller. The controller associates a first number of consecutive logical addresses with the first number of physical addresses which are included in a second number of consecutive physical addresses of the first memory. The controller executes a first updating and a second updating. The first updating includes associating a first physical address among the second number of physical addresses with a first logical address. The second updating includes obtaining a second logical address which is away from the first logical address by a value corresponding to distance information on the basis of origin information and the distance information and associating, with the second logical address, a second physical address which had been associated with the first logical address before the first updating is executed.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: February 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Naomi Takeda, Kenta Yasufuku, Hiroshi Yao
  • Patent number: 10509724
    Abstract: Implementations of this disclosure are directed to systems, methods and media for assessing the status of data being stored in distributed, cached databases that includes retrieving, from a data cache, variables which include a cache loss indicator and a non-null value. The variables are analyzed to determine a state of the cache loss indicator. If the cache loss indicator indicates an intentional cache loss state, the cache loss indicator is removed and the non-null value is provided to an application. Otherwise, a cache restore process is initiated.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 17, 2019
    Assignee: MZ IP HOLDINGS, LLC
    Inventors: Ajk Palikuqi, Garth Gillespie, Arya Bondarian, Jai Kim
  • Patent number: 10496303
    Abstract: A method for reducing power consumption of a memory of a computer device is presented. The memory includes at least two channels, each channel includes at least two storage units, a dirty data storage area is set in the memory, and the dirty data storage area includes at least one storage unit in each channel. After the computer device encounters a power failure, a backup power supply is turned on to supply power to the memory, then the storage unit included in the dirty data storage area is kept in a normal operating state, and a storage unit outside the dirty data storage area in the memory is caused to enter a self-refreshing state. Data in the dirty data storage area is then written to a non-volatile storage area of the computer device.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: December 3, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zhibing Li, Yongjiang Yi
  • Patent number: 10452546
    Abstract: Examples may include techniques to monitor processing of I/O requests of an application being executed by a computing platform by collecting a trace of the I/O requests, the trace including an I/O class of each I/O request; replay the trace and automatically analyze possible cache configuration policies for using a cache during execution of the application by the computing platform; and determine an optimal cache configuration policy for the cache from the possible cache configuration policies. The optimal cache configuration policy may then be applied to use of the cache during subsequent execution of the application by the computing platform.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Michael Mesnier, Arun Raghunath, Mariusz Barczak, John Keys
  • Patent number: 10452122
    Abstract: A data storage device coupled to a host device via a predetermined interface includes a memory device, an SRAM, and a controller. The controller is coupled to the memory device and the SRAM. The controller receives a first power mode change request packet requesting to change the data transfer speed of the predetermined interface from a first speed to a second speed via the predetermined interface from the host device, and in response to the first power mode change request packet, the controller determines whether the operation status of the data storage device is busy. When the operation status of the data storage device is busy, the controller determines to reject the request to change the data transfer speed and keeps the data transfer speed at the first speed and does not change the data transfer speed to the second speed.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: October 22, 2019
    Assignee: SILICON MOTION, INC.
    Inventors: Fu-Jen Shih, Yen-Hung Chen
  • Patent number: 10423529
    Abstract: Implementations of this disclosure are directed to systems, methods and media for assessing the status of data being stored in distributed, cached databases that includes retrieving, from a data cache, variables which include a cache loss indicator and a non-null value. The variables are analyzed to determine a state of the cache loss indicator. If the cache loss indicator indicates an intentional cache loss state, the cache loss indicator is removed and the non-null value is provided to an application. Otherwise, a cache restore process is initiated.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: September 24, 2019
    Assignee: MZ IP HOLDINGS, LLC
    Inventors: Ajk Palikuqi, Garth Gillespie, Arya Bondarian, Jai Kim
  • Patent number: 10409502
    Abstract: An example method and an example apparatus for writing data into a cache are described herein. The example method includes receiving an IO request write command, where the IO request write command includes metadata of to-be-written data. A first buddy group is obtained from a global buddy queue, and a determination as to whether all metadata of the to-be-written data can be written into the first buddy group is made. If the determination is yes, all the metadata of the to-be-written data is written into the first buddy group, and all the metadata of the to-be-written data is written into a metadata block corresponding to a metadata group to which the first buddy group belongs.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 10, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Futang Huang
  • Patent number: 10404410
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device maintain memory ranking information for a set of storage units (SUs) and receives a read data request. The computing device selects a decode threshold number and/or a read threshold number of SUs to service the read data request based on the memory ranking information. The computing device recovers the data segment and transmits a read data response that is based on the processing the read data request.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: September 3, 2019
    Assignee: PURE STORAGE, INC.
    Inventors: Jason K. Resch, Ethan S. Wozniak
  • Patent number: 10387306
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor, a prognostic agent embodied in a program of executable instructions and configured to, when executed, maintain a prognostic data structure setting forth a plurality of parameters regarding a non-volatile memory of the information handling system, and a memory controller configured. The memory controller may be configured to calculate a severity index based on the parameters set forth in the prognostic data structure, the severity index indicative of a likelihood of successfully completing a save operation to the non-volatile memory from a volatile memory in response to a power event of the information handling system and based on the severity index, determine whether or not to perform a save operating in response to a power event of the information handling system.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 20, 2019
    Assignee: Dell Products L.P.
    Inventors: Parmeshwr Prasad, Yogesh P. Kulkarni
  • Patent number: 10372658
    Abstract: A method and a memory device therefor for reconfiguring a DQ pad organization of the memory device on-the-fly. A DQ organization reconfiguration control unit generates a control signal for reconfiguring the DQ pad organization into a desired mode based on a user command. A DQ organization reconfiguration unit is provided between P DQ pads and memory cell arrays and reconfigures organization P DQ pads on-the-fly in any one among Xi DQ pad modes, where i=1, 2, 4, 8, 16, 32, 64, and 128, based on the control signal. For the reconfiguration of the organization of the DQ pads, a plurality of bus lines for data transfer, being switchable by a control signal, are provided. The bus lines are implemented utilizing at least one of the M3 and M4 metal layers of the memory device.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 6, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chan-Kyung Kim
  • Patent number: 10338848
    Abstract: Various examples of the present invention relate to an electronic device data recording method and an electronic device thereof, and an electronic device operating method can comprise the steps of: determining a data recording possibility of a specific area of a nonvolatile memory in which data is to be recorded; and determining whether to record data based on the data recording possibility. In addition, the various examples of the present invention also include the aforementioned example and other examples.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Tae-Young Kim
  • Patent number: 10331370
    Abstract: Performance tuning in a storage system that includes one or more storage devices, including: storing, by a primary controller of the storage system, data corresponding to one or more computer processes into one or more of the one or more storage devices, determining, by a secondary controller that is configured similarly to the primary controller, one or more utilization patterns of the data, and initiating, in dependence upon the one or more utilization patterns of the data, a modification to a manner in which the one or more computer processes access the data stored in the one or more storage devices.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: June 25, 2019
    Assignee: Pure Storage, Inc.
    Inventors: Argenis Fernandez, Ronald Karr, David Whitlock, Sergey Zhuravlev
  • Patent number: 10324864
    Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegyu Lee, Jisoo Kim, Young-Jin Park, Bo-Ram Shin
  • Patent number: 10318521
    Abstract: A computer-implemented method executed on one or more processors is provided for processing a query for a NoSQL (non-structured query language) database. The computer-implemented method includes periodically monitoring active transactions that started and are committing dirty versions before a specific time, sending a query to fetch a state of the active transactions, and receiving a query result. The computer-implemented method further includes, if the query result includes active transactions, performing a normal query that scans dirty and committed versions. The computer-implemented method further includes, if the query result includes no active transactions, due to a time window indicating a specified staleness, sending a simplified query that scans only committed versions.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventor: Hiroshi H. Horii
  • Patent number: 10289423
    Abstract: A system management controller with a consolidated memory is disclosed. The example computing device includes a processor to host an operating system and a system memory to be used by the processor to execute instructions. The computing device also includes a management controller to enable out-of-band management of the computing device. The management controller includes a consolidated memory device. A first memory block of the consolidated memory device is used by the management controller as a working memory and a second memory block of the consolidated memory device is used for long-term storage of programming instructions.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: May 14, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Vincent Nguyen, Chanh V. Hua, Ning Ge, Naveen Muralimanohar
  • Patent number: 10268387
    Abstract: Technology is described herein for performing memory array operations in multiple memory dies in parallel. The memory dies, or groups of non-volatile memory cells on the memory dies, may exhibit different performance times for memory array operations. For example, non-volatile memory cells on one memory die may program more slowly than those on another memory die. The performance times of the memory dies (or groups of the memory cells on different memory dies) may be characterized relative to one another. Memory dies having similar performance times may be placed into the same meta-groups. Meta-groups may be formed at the die, zone, or block level. The meta-groups can be re-formed over the lifetime of the memory system, which can account for changes in performance times over the lifetime of the memory system.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: April 23, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Narendhiran Cr, Satya Kesav Gundabathula, Muralitharan Jayaraman, Chittoor Devarajan Sunilkumar, Satrajit Chakraborty
  • Patent number: 10261571
    Abstract: Example implementations relate to backup power supply support. For example, a backup power supply support system can include a shared backup power supply controlled by a backup power control module and a support switch coupled to the shared backup power supply. The support switch enables a transition from a primary power supply to the shared backup power supply and the support switch includes system firmware. The system firmware detects a primary power supply compromise, isolates a hardware switch from the shared backup power supply, enables the hardware switch, and transitions to the shared backup power supply.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: April 16, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Edgar Hance, David W. Engler, Han Wang
  • Patent number: 10241927
    Abstract: A linked-list-based method for application caching management is disclosed, the method including: when receiving application cached data, creating a node in a linked list for the cached data and obtaining a memory size of the cached data; obtaining a maximum memory size and a currently occupied memory size of the linked list; adding the memory size of the received cached data to the currently occupied memory size of the linked list to obtain a first memory size; and adding the node to the linked list if the first memory size is smaller than or equal to the maximum memory size. A linked-list-based device for application caching management is also provided.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: March 26, 2019
    Assignee: SHENZHEN SKYWORTH-RGB ELECTRONIC CO., LTD.
    Inventor: Rui He
  • Patent number: 10236034
    Abstract: Examples disclosed herein relate to dual in-line memory module (DIMM) battery backup. Some examples disclosed herein describe systems that include a backup power source pluggable into a DIMM slot. The backup power source may include a plurality of battery cells electrically connected to a DIMM to provide backup power to the DIMM. Each of the plurality of battery cells supporting the DIMM may be electrically connected to a DC-to-DC converter in series and to each other in parallel.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: March 19, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Hai Nguyen, Daniel Hsieh, Abhishek Banerjee
  • Patent number: 10235049
    Abstract: A management device according to an embodiment manages reading and writing of data, by a processing circuit, from and into a first memory unit and a non-volatile memory unit containing a plurality of pages, and includes a setting storage unit, an access processing circuit, and a management circuit. The setting storage unit stores an access method indicating whether first access processing of writing and reading data into and from data transferred to the first memory unit from the non-volatile memory unit or second access processing of directly writing and reading data into and from data stored in the non-volatile memory unit is executed for each of the pages. The management circuit changes the access method for a third page on which the second access processing is set to be performed to the first access processing when quality of the third page is equal to or lower than a reference value.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: March 19, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Shirota, Tatsunori Kanai, Satoshi Shirai, Shiyo Yoshimura
  • Patent number: 10216437
    Abstract: Aspects of the subject matter described herein relate to storage systems and aliased memory. In aspects, a file system driver or other component may send a request to a memory controller to create an alias between two blocks of memory. One of the blocks of memory may be used for main memory while the other of the blocks of memory may be used for a storage system. In response, the memory controller may create an alias between the blocks of memory. Until the alias is severed, when the memory controller receives a request for data from the block in main memory, the memory controller may respond with data from the memory block used for the storage system. The memory controller may also implement other actions as described herein.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: February 26, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: William R. Tipton, Surendra Verma, Landy Wang, Malcolm James Smith
  • Patent number: 10210088
    Abstract: The present application relates to a cache invalidation unit for a computing system having a processor unit, CPU, with a cache memory, a main memory and at least one an alternate bus master unit. The CPU, the main memory and the at least one an alternate bus master unit are coupled via an interconnect for data communications between them. The cache invalidation unit generates one or more invalidation requests to the cache memory in response to the alternate bus master unit writing data to the main memory. The cache invalidation unit comprises a page address generator unit to generate page addresses relating to at least one address range and an invalidation request generator unit to generate an invalidation request for each page address. The one or more generated invalidation requests are transmitted by the cache invalidation unit via to the cache memory of the CPU.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Ray Charles Marshall, Nancy Hing-Che Amedeo, Joachim Fader
  • Patent number: 10205726
    Abstract: A method includes detecting a storage device at a protected node and determining whether the storage device has been checked-in for use with at least the protected node. The method also includes granting access to the storage device in response to determining that the storage device has been checked-in for use with at least the protected node. The method further includes blocking access to the storage device in response to determining that the storage device has not been checked-in for use with at least the protected node. The method may also include determining whether a file on the storage device has been checked-in for use with at least the protected node. Meaningful access to the file is granted or blocked in response to determining that the file has or has not been checked-in for use with at least the protected node.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: February 12, 2019
    Assignee: Honeywell International Inc.
    Inventors: Eric D. Knapp, Eric T. Boice
  • Patent number: 10185511
    Abstract: Technologies for managing an operational characteristic of a solid state drive include monitoring the operational characteristic to determine whether the operational characteristic satisfies a low threshold and a high threshold. If the operational characteristic does satisfy the low threshold, the solid state drive throttles high power memory accesses requests while not throttle low power memory access requests. If the operational characteristic satisfies a high threshold, the solid state drive is configured to throttle all memory accesses. The operational characteristic may be embodied as, for example, a temperature of the solid state drive.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Neeraj Sharma, Ning Wu, Steven E. Wells
  • Patent number: 10180811
    Abstract: A semiconductor storage device includes m (m?2) memory chips, a buffer, and a controller. The controller arranges, in the buffer, a first plurality of data units to be transferred to N (1?N?m) of the m memory chips, in an order in which each of the first plurality of data units has been received from a host, for each one of the N memory chips, and arranges a second plurality of data units, if any, in an order in which each of the second plurality of data units has been received from the host, for each one of the next N memory chips. Upon the arranged data units, the controller collectively transfers the certain number of arranged data units to the memory. The value of N is changed based on an amount of data accumulated in the buffer.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: January 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akinori Harasawa, Yoshihisa Kojima
  • Patent number: 10176094
    Abstract: Common microcontroller unit (MCU) self-identification information is disclosed. In one embodiment, an MCU is contained in a package. The MCU includes a central processing unit (CPU) and a non-volatile memory. This non-volatile memory stores information specific to the MCU and/or the package. The non-volatile memory also stores a common main program that, when executed by the CPU, accesses the information. The information enables the common main program to adapt itself to resources of the MCU and/or package that are identified in the information.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 8, 2019
    Assignee: RENESAS ELECTRONICS AMERICA INC.
    Inventors: Jon Matthew Brabender, Bernd Willi Westhoff
  • Patent number: 10089484
    Abstract: Systems and methods for destroying sensitive enterprise data on portable devices are provided. Such systems and methods may include providing a portable device that includes a security agent for deleting sensitive enterprise data. The security agent on the portable device can be required to regularly be authenticated by a user through an authentication server. The authentication server provides a pre-determined timeframe for which the user would need to re-authenticate. Failure by the user to re-authenticate within the pre-determined timeframe can result in the security agent proceeding with deleting the sensitive enterprise data on the portable device.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: October 2, 2018
    Assignee: QUEST SOFTWARE INC.
    Inventors: Tomas Willis, Peter Travis terSteeg
  • Patent number: 10078455
    Abstract: Aspects extend to methods, systems, and computer program products for predicting solid state drive reliability. Aspects of the invention can be used to predict and/or to configure a data center to minimize one or more of: SSD capacity degradation (how much storage an SSD has left), SSD performance degradation (reduced read/write latency/throughput), and SSD failure. Models and data center considerations can be based on device level SSD related operations, such as, for example, read, write, erase. Operations decisions can be made for a data center based on SSD specific features, such as, for example, remaining capacity, write amplification factor, etc. Dependence and/or causality of various different data center factors can be leveraged. The impact of the various data center factors on different SSD failure modes and capacity/performance degradation can be quantified to drive SSD design, SSD provisioning, and SSD operations.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: September 18, 2018
    Inventors: Iyswarya Narayanan, Di Wang, Myeongjae Jeon, Bikash Sharma, Laura Marie Caulfield, Sriram Govindan, Benjamin Franklin Cutler, Christopher W. Hoder, Jaya Naga Satish Bobba, Jie Liu, Badriddine Khessib
  • Patent number: 10048892
    Abstract: Fast reuse memory block detection methods and memory block management methods using the same are provided. A fast reuse memory block detection method may include selecting a memory block from memory blocks included in a nonvolatile memory device as a reference block at an initially set period, managing one of an erase time and a program time of the reference block, and determining whether other memory blocks are fast reuse memory blocks, based on a use period that is determined according to the managed one of the erase time and the program time of the reference block.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: August 14, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-kwon Moon, Jong-youl Lee, Seong-jun Ahn, Hee-won Lee
  • Patent number: 10025576
    Abstract: A BIOS delivery installation package includes a basic input/output system (BIOS) update payload including a BIOS image. The BIOS delivery installation package also includes a first hash corresponding to a portion of the BIOS image.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: July 17, 2018
    Assignee: DELL PRODUCTS, LP
    Inventors: Ricardo L. Martinez, Balasingh P. Samuel, Richard M. Tonry
  • Patent number: 10019320
    Abstract: An aggregation module combines a plurality of logical address spaces to form a conglomerated address space. The logical address spaces comprising the conglomerated address space may correspond to different respective storage modules and/or storage devices. An atomic aggregation module coordinates atomic storage operations within the conglomerated address space, and which span multiple storage modules. The aggregation module may identify the storage modules used to implement the atomic storage request, assign a sequence indicator to the atomic storage request, and issue atomic storage requests (sub-requests) to the storage modules. The storage modules may be configured to store a completion tag comprising the sequence indicator upon completing the sub-requests issued thereto. The aggregation module may identify incomplete atomic storage requests based on the completion information stored on the storage modules.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: July 10, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Nisha Talagala, Dhananjoy Das, Swaminathan Sundararaman, Ashish Batwara, Nick Piggin
  • Patent number: 10007459
    Abstract: Performance tuning in a storage system that includes one or more storage devices, including: storing, by a primary controller of the storage system, data corresponding to one or more computer processes into one or more of the one or more storage devices, determining, by a secondary controller that is configured similarly to the primary controller, one or more utilization patterns of the data, and initiating, in dependence upon the one or more utilization patterns of the data, a modification to a manner in which the one or more computer processes access the data stored in the one or more storage devices.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: June 26, 2018
    Assignee: Pure Storage, Inc.
    Inventors: Argenis Fernandez, Ronald Karr, David Whitlock, Sergey Zhuravlev
  • Patent number: 10001953
    Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 19, 2018
    Assignee: Intel Corporation
    Inventors: Leena K. Puthiyedath, Blaise Fanning, Toby Opferman, James B. Crossland
  • Patent number: 9997219
    Abstract: A memory macro includes a first set of memory cells, a second set of memory cells, a third set of memory cells, a set of retention circuits and a set of conductive lines. The second set of memory cells arranged in a first row arranged in a second direction. The third set of memory cells arranged in a first column arranged in a first direction. The set of retention circuits is configured to supply a second voltage value of a second supply voltage to the first set of memory cells during a sleep operational mode. The set of retention circuits is responsive to a set of control signals, and arranged in a second column arranged in the first direction. The set of conductive lines extend in the second direction, and coupled to the set of retention circuits and the voltage supply node of the first set of memory cells.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Pankaj Aggarwal, Jhon Jhy Liaw