Abstract: A device for detecting zone parallelity includes a detection control circuit configured to generate respective first and second requests for first and second zones among a plurality of zones included in a solid state drive (SSD). An SSD controller is configured to control the SSD by generating a first command and a second command corresponding to the first request and the second request, respectively, and to schedule the first command and the second command. The detection control circuit determines zone parallelity of the first and second zones using response characteristics of the responses of the SSD to the first request and the second request. The response characteristics may include a latency of a response.

Abstract: A method to secure boot an electronic device is disclosed according to some embodiments. The method includes receiving a request to initiate a boot sequence using memory content stored in a non-volatile memory circuit. A secure boot circuit receives verification data from the non-volatile memory circuit indicating the memory content. The verification data includes an error correction code for the memory content without including all of the memory content. A cryptographic hashing operation is performed to the error correction code in the secure boot circuit to obtain a digest of the error correction code. The digest is compared with a pre-stored reference digest to generate a verification signal. The verification signal is provided to the electronic device indicating whether the boot sequence passes the verification.

Abstract: A memory control device 100 of the present invention includes a data storage processing unit 101 that stores, in an additional data area that is an area for storing additional data in memory-stored data including compressed data and the additional data to be stored in a memory, an error correcting code of the compressed data and compression information representing the degree of compression of the compressed data, and a read processing unit 102 that controls readout of the memory-stored data on the basis of the degree of compression represented by the compression information in the additional data area of the memory-stored data, when reading out the memory-stored data from the memory.

Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.

Abstract: A hard disk device simulator, a testing system using the hard disk device simulator and a testing method thereof are disclosed. The hard disk device simulator having a detection circuit is serially connected to a test port of a device under test, and a test program is executed on the device under test to read a signal link status of an insertion slot of the device under test and transmit a detection command through the test port, to drive a detection circuit of the hard disk device simulator to detect signals on a power pin, a clock pin and a system management bus, to generate a detection result, thereby verifying correctness of the device under test based on the signal link status and the detection result. As a result, the technical effect of reducing the cost of testing the device under test can be achieved.

Abstract: According to one embodiment, a memory system includes a controller which controls garbage collection for preparing one or more free blocks by writing valid data read from N blocks to one or more blocks of less than the N. The controller calculates a performance ratio between writing of data in response to a request from a host device and writing of data for the garbage collection in accordance with a data writable capacity remaining in a nonvolatile memory, calculates an average performance ratio from calculated performance ratios of M generations including a calculated latest performance ratio, and adjusts a performance cycle of the garbage collection by applying one of the calculated latest performance ratio and the calculated average performance ratio.

Abstract: Various implementations described herein relate to systems and methods for managing metadata for an atomic write operation, including determining metadata for data, queuing the metadata in an atomic list, in response to determining that atomic commit has occurred, moving the metadata from the atomic list to write lookup lists based on logical information of the data, and determining one of metadata pages of a non-volatile memory for each of the write lookup lists based on the logical information.

Abstract: The present disclosure includes apparatuses and methods related to transaction identification. An example apparatus can determine a transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record with a memory device transaction identification (TID) record.

Abstract: Various embodiments include methods and devices for portion interleaving for asymmetric size memory portions. Embodiments may include determining an asymmetric memory portion assignment for an interleave unit, determining a consumed address space offset for consumed address space of a memory, modifying an address of the interleave unit using the consumed address space offset, and assigning the interleave unit to an interleave granule in the asymmetric memory portion using the modified address in a compact manner before assigning another interleave unit to another interleave granule. Embodiments may include receiving an address of memory access request in a memory, mapping the address to an interleave granule in an asymmetric memory portion, assigning consecutive interleave units to the interleave granule while the interleave granule has unused space before assigning another interleave unit to another interleave granule, and implementing the memory access request at the mapped address.

Abstract: An apparatus comprises a processing device configured to monitor a storage cache storing a plurality of cache pages to determine whether the storage cache reaches one or more designated conditions and to determine cache replacement scores for at least a subset of the cache pages, the cache replacement scores being determined based at least in part on input-output access types for data stored in the cache pages. The processing device is also configured to select, responsive to determining that the storage cache has reached at least one of the one or more designated conditions, at least one of the cache pages to move from the storage cache to a storage device based at least in part on the determined cache replacement scores. The processing device is further configured to move the selected at least one of the plurality of cache pages from the storage cache to the storage device.

Abstract: A field-programmable gate array includes a memory, a firmware state machine, a register, and an interconnect structure. The memory is configured to store a plurality of configurations. Each of the plurality of configurations has at least one parameter associated therewith. The firmware state machine is configured to read the parameters stored in the memory. The register is configured to have the parameters associated with the plurality of configurations written thereto. The interconnect structure is configured to transmit the parameters between the firmware state machine and the register. The interconnect structure is configured to receive the parameters associated with the plurality of the configurations simultaneously and the interconnect structure is configured to transmit the received parameters associated with the plurality of configurations to the register simultaneously.

Abstract: In one embodiment, the method includes receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.

Abstract: A memory system may include a memory device including at least one sequential area in which a data corresponding to consecutive logical addresses of the at least one sequential area is stored, a sequential buffer configured to temporarily store the data to be stored in the at least one sequential area, a meta buffer configured to store a meta data including a write pointer information indicating a logical address in which data is to be stored from among logical addresses corresponding to the at least one sequential area, and an area state information indicating whether the sequential buffer is allocated to the at least one sequential area, and a memory controller configured to perform a write operation of storing the data in the at least one sequential area in response to a first command received from the host using the meta data.

Abstract: One or more write operations are performed on a memory component. First data stored at the memory component is read. A determination is made as to whether an error rate associated with the first data stored at the memory component exceeds an error rate threshold. If the error rate exceeds the error rate threshold, a threshold value is adjusted. A determination is made as to whether a number of the plurality of write operations performed on the memory component since performance of a refresh operation on the memory component exceeds the threshold value. In response to determining that the number of write operations performed on the memory component exceeds the threshold value, a memory cell of the memory component is identified based on the plurality of write operations. Second data stored at memory cells of the memory component that are proximate to the identified memory cell is refreshed.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to read data from the nonvolatile memory by applying a read voltage to the nonvolatile memory. The controller is configured to correct the read voltage based on a difference between a measured value of a bit number obtained when the data is read from the nonvolatile memory by applying the read voltage to the nonvolatile memory and an expected value of the bit number.

Abstract: According to one embodiment, a memory system includes a controller which controls garbage collection for preparing one or more free blocks by writing valid data read from N blocks to one or more blocks of less than the N. The controller calculates a performance ratio between writing of data in response to a request from a host device and writing of data for the garbage collection in accordance with a data writable capacity remaining in a nonvolatile memory, calculates an average performance ratio from calculated performance ratios of M generations including a calculated latest performance ratio, and adjusts a performance cycle of the garbage collection by applying one of the calculated latest performance ratio and the calculated average performance ratio.

Abstract: A multi-stream memory system includes an in-device data processor including a first data processing engine and a second data processing engine, a controller processor, and a processor memory coupled to the controller processor, wherein the processor memory has stored thereon instructions that, when executed by the controller processor, cause the controller processor to perform: identifying a stream ID of an input stream, identifying the first data processing engine as being associated with the stream ID based on a stream assignment table, and applying the first data processing engine to the input stream to generate processed data.

Abstract: A system comprising a memory component including blocks, and a processing device, operatively coupled with the memory component. The processing device determines endurance values for the memory component. For each selected block of the plurality of blocks, the processing device determines an endurance estimation of the selected block based on at least one of a time to erase the selected block or an error statistic for the selected block, and updates an endurance value associated with the selected block based on the endurance estimation for the selected block. The processing device receives a write instruction to the memory component and distributes the write instruction to one or more of the blocks based on the endurance values. Other embodiments are described.

Abstract: The disclosed embodiments are directed to improving the lifespan of a memory device. In one embodiment, a system is disclosed comprising: a host processor and a memory device, wherein the host processor is configured to receive a write command from a virtual machine, identify a region identifier associated with the virtual machine, augment the write command with the region identifier, and issue the write command to the memory device, and the memory device is configured to receive the write command, identify a region comprising a subset of addresses writable by the memory device using a region configuration table, and write the data to an address in the subset of addresses.

Abstract: A method of managing data in a storage device is provided. The storage device includes a plurality of nonvolatile memory chips each including a plurality of pages. A first data object is received from an external host device. The first data object has an unfixed size and corresponds to a first logical address which is a single address. Based on determining that it is impossible to store the first data in a single page among the plurality of pages, a buffering policy for the first data object is set based on at least one selection parameter. While mapping the first logical address of the first data object and a first physical address of pages in which the first data object is stored, a first buffering direction representing the buffering policy for the first data object is stored with a mapping result.

Abstract: The present disclosure relates to an electronic device, such as a system on chip, that may perform firmware updates based on user consent. The system on chip includes a nonvolatile memory (NVM), a main processor, a security NVM, and a security processor. The nonvolatile memory (NVM) stores first firmware and a user permission indicator. The main processor Loads the first firmware to boot a security processor. The security NVM contains first version information. The security processor compares version information of the first firmware to the first version information based on the user permission indicator and executes the first firmware in response to the matching of the comparison result. In some examples, the security processor is implemented on the same chip as the main processor.

Abstract: Embodiments include side channel defender circuitry to protect shared code pages in executable only memory (XOM) from side-channel exploits. The side channel defender circuitry receives system calls and determines whether code pages include executable code, whether the code pages include writeable code, and whether the code pages include instructions capable of altering or modifying one or more protection keys associated with code pages stored in XOM. If the code pages contain executable code that is writeable or executable code that includes instructions capable of altering or modifying one or more protection keys associated with code pages stored in XOM the side channel defender circuitry, the side channel defender circuitry aborts the system call.

Abstract: There is provided a recording apparatus. A recording control unit performs control to record a still image or a moving image into a first recording medium. A control unit controls whether to permit execution of automatic background processing during a power saving period on the first recording medium. The control unit performs control to permit the execution of the automatic background processing during the power saving period when the still image is recorded into the first recording medium, and not to permit the execution of the automatic background processing during the power saving period when the moving image is recorded into the first recording medium.

Abstract: A data storage device may include a storage including a plurality of dies each including a plurality of memory blocks including a plurality of pages, and a controller configured to select at least one memory block from each of the dies to configure a block group, configure a page group with pages having an equal offset in each memory block in each block group, and access the storage in a die interleaving manner. The controller may be configured to detect an open block group as power is supplied after sudden power off, set search sections for each die including a plurality of blocks in the detected open block group, and search for a last access page by simultaneously accessing the search sections for each die.

Abstract: An information processing apparatus which is capable of preventing a malfunction of a storage using flash memory caused by a decrease in the number of free blocks. The information processing apparatus controls a storage that includes a nonvolatile memory and a memory controller that controls the nonvolatile memory. The number of free blocks in the nonvolatile memory is detected, and in accordance with the detected number of free blocks, the memory controller is instructed to switch to one of the following writing modes: a first writing mode in which the memory controller writes data to the nonvolatile memory without performing garbage collection, and a second writing mode in which the memory control unit writes data to the nonvolatile memory and then performs garbage collection.

Abstract: An electronic system such as an imaging system may include processing circuitry and memory circuitry. Data replacement circuitry may be interposed between the processing circuitry and the memory circuitry. In some implementations, the memory circuitry may be a read-only memory, and data replacement circuitry may be used to selectively replace executable firmware instructions stored on the read-only memory. The selective replacement operations may be based on an address that processing circuitry provides to access the memory circuitry. The data replacement circuitry may be implemented separately from the processing circuitry and the memory circuitry and may include a comparator block, registers, and switching circuitry.

Abstract: A memory controller configured to control a memory device may include: a metadata storage configured to store a plurality of metadata segments; a metadata updater configured to sequentially update the metadata segments; a backup data storage configured to store at least one original metadata segment (a metadata segment existing before being updated) among the metadata segments; a metadata backup circuit configured to store, before a selected metadata segment among the metadata segments is updated, an original metadata segment of the selected metadata segment in the backup data storage; and a metadata restorer configured to generate storage inhibit information indicating whether storing data in the memory device is inhibited based on a residual storage capacity of the memory device, and store, in the metadata storage, the original metadata segment stored in the backup data storage in response to the storage inhibit information while the metadata segments are updated.

Abstract: Non-volatile devices may be configured such that a clear operation on a single bit clears an entire block of bits. The representation of particular data structures may be optimized to reduce the number of clear operations required to store the representation in non-volatile memory. A data schema may indicate that a data structure of an application may be optimized for storage in non-volatile memory. A translation layer may convert an application level representation of a data value associated with the data structure to an optimized storage representation of the data value before storing the optimized storage representation of the data value in non-volatile memory.

Abstract: Systems and methods are disclosed comprising receiving first-level L2P table information from a storage system over a communication interface, maintaining a host L2P table on using the received first-level L2P table information, and providing a read command to the storage system for first data associated with a first LBA and a host L2P entry associated with the first data. The host L2P entry can include a physical address of the first LBA on the storage system according to the host L2P table and a physical address of a portion of the L2P table on the storage system associated with the first LBA. Control circuitry of the storage system can validate the physical address of the first LBA from the host L2P entry using the physical address of the portion of the host L2P table associated with the first LBA and the second-level L2P table.

Abstract: The present disclosure includes apparatuses and methods related to transaction identification. An example apparatus can determine a transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record with a memory device transaction identification (TID) record.

Abstract: A method is for operating a nonvolatile dual in-line memory module (NVDIMM). The NVDIMM includes a dynamic random access memory (DRAM) and a nonvolatile memory (NVM) device, the DRAM including a first input/output (I/O) port and a second I/O port, and the second I/O port connected to the NVM device. The method includes receiving an externally supplied command signal denoting a read/write command and a transfer mode, driving a multiplexer to select at least one of the first and second I/O ports according to the transfer mode of the command signal, and reading or writing data according to the read/write command of the command signal in at least one of the DRAM and NVM device using the at least one of the first and second I/O ports selected by driving the multiplexer.

Abstract: A programmable memory device includes a read only memory (ROM) block to store instructions associated with functionality of the programmable memory device. The device includes a memory array having a set of reserved pages to store updates to be performed on the ROM block. The device includes a controller coupled to the ROM block and the memory array. The controller is to execute the instructions to: execute a set features command; program, in execution of the set features command, a set of sub-feature parameters to a specified feature address of the set of reserved pages, wherein the set of sub-feature parameters are to trigger operation within a ROM-emulated memory (REM) profile mode; and program a REM-profiled page of the set of reserved pages with REM data received from a host system.

Abstract: The system receives a request to write data and associated metadata. The system determines a key associated with the data, wherein the key corresponds to an entry in a data structure maintained by a first storage system. The system writes the metadata to a first non-volatile memory of a first set of storage drives of the first storage system by updating the entry with a logical block address for the data and a physical location in a second set of storage drives of a second storage system. The system writes the key and the data to a second non-volatile memory of the second set of storage drives based on the physical location, wherein the first non-volatile memory is of a lower density than the second non-volatile memory.

Abstract: A method and system for collecting diagnostic data from a storage class memory chip is disclosed. The method includes performing a scrub process on at least a portion of the storage class memory by: removing the portion of the storage class memory from use, wherein the portion comprises a plurality of memory locations, executing a first write operation to write a first pattern on each of the plurality of memory locations, executing a first read operation to obtain a first set of data written on each of the plurality of memory locations, analyzing the first set of data written on each of the plurality of memory locations to determine the number of stuck-at faults in the portion, and updating one or more counters in an error rate table (ERT) to indicate the number of stuck-at faults.

Abstract: One or more write operations are performed on a memory component. A determination is made as to whether a number of the plurality of write operations performed on the memory component since performance of a refresh operation on the memory component exceeds a threshold value. In response to determining that the number of write operations performed on the memory component exceeds the threshold value, a memory cell of the memory component is identified based on the plurality of write operations. Data stored at memory cells of the memory component that are proximate to the identified memory cell is refreshed.

Abstract: Sensitive data is protected in a software product. A source file of the software product is compiled to generate an object file, in which the source file includes at least one piece of sensitive data marked with a specific identifier. The object file has a secure data section for saving storage information of the at least one piece of sensitive data at compile-time and run-time. The object file is linked to generate an executable file. The executable file updates the secure data section at run-time. Sensitive data is also protected when a core dump is generated.

Abstract: A memory device may include memory cells configured to establish multiple levels of charge distributions; and a memory controller configured to perform operations on the memory cells. The operations may include recording a bit count number for a highest level of charge distributions within a set of memory cells, recording a bit count number for a lowest level of charge distributions within the set of memory cells, counting bits for the highest level of charge distributions within the set of memory cells, counting bits in the lowest level of charge distributions within the set of memory cells, comparing the counted bits for the highest level to the recorded bit count number for the highest level, and comparing the counted bits for the lowest level to the recorded bit count number for the lowest level.

Abstract: A system for providing a function as a service (FaaS) is provided. The system includes a communicator which receives a request for setting resources to execute the function, a memory which stores one or more instructions, and a processor. The processor executes the stored instructions. When the processor executes the instructions, it analyzes characteristics of the function and provides recommendation information related to the setting of the resources to execute the function based on a result of the analyzing.

Abstract: An operating method of a storage device which includes a first nonvolatile memory device and a second nonvolatile memory device includes detecting sudden power-off, suspending an operation being performed in the first nonvolatile memory device, in response to the detected sudden power-off, writing suspension information about the suspended operation into the second nonvolatile memory device, and performing a block management operation on the first nonvolatile memory device based on the suspension information written into the second nonvolatile memory device, in power-up after the sudden power-off.

Abstract: A data storage device includes a controller configured to recognize commands received from a host as single logical address (LA) commands or multi-LA commands. The data storage drive also includes a command overlap detection table having a plurality of records with each record configured to store multiple unrelated LAs associated with different single LA commands and configured to store multiple related LAs associated with a single multi-LA command.

Abstract: Systems and methods for determining retention periods or policies for backups are disclosed. A rule book stores relationships between rules and recommended retention periods. Data related to a backup is collected and organized. A query is generated from the organized data and used to identify a rule from the rule book. The retention period corresponding to the identified rule in the rule book is then applied to the corresponding backup.

Abstract: Embodiments of the present disclosure relate to methods and apparatuses for caching data. A method comprises writing data into a first cache module on a first processor in response to receiving a first request for caching the data from a client module running on the first processor. The method further comprises transmitting, to the client module, a first indication that the data has been written into the first cache module. The method further comprises, in response to receiving from the client module a second request for synchronizing the data to a second processor, transmitting to the second processor a first command for causing the data to be written into a second cache module on the second processor. In addition, the method further comprises transmitting to the client module a second indication that the data has been synchronized.

Abstract: A semiconductor storage device exhibiting improved programming reliability is provided. In the disclosure, flash memory includes a storage controller and a NAND type storage device. The storage controller includes a voltage detecting part, SRAM, RRAM, and a writer/selector. The voltage detecting part detects whether a power supply voltage drops to a fixed voltage. The SRAM stores a conversion table for converting a logical address into a physical address. The RRAM stores the logical address of a block and a page currently being programmed and conversion information for converting the logical address into another physical address when the fixed voltage is detected by the voltage detecting part during a programming process. The writer/selector converts the inputted logical address into the physical address according to the conversion table or the conversion information of the RRAM and programs data on the page of the block selected according to the converted physical address.

Abstract: A initialization code/data memory mapping system includes a processing system, memory device(s) storing initialization code and initialization data, and a main memory system. The processing system performs first MMIO read operations to access the initialization code stored in the memory device(s) that is mapped to an initialization memory space in order to provide an initialization engine, and uses it to copy the initialization code from the memory device(s) to the main memory system. The processing system then accesses the initialization code stored in the main memory system in order to provide the initialization engine, and uses it to map the initialization data stored in the memory device(s) to the initialization memory space. The processing system then performs second MMIO read operations to access the initialization data stored in the memory device(s) that is mapped to the initialization memory space for use by the initialization engine.

Abstract: A memory control apparatus includes a first memory, a second memory, a third memory, and a processor configured to add, to management information, first identification information and information indicating a position where first data is stored when the first data is stored in the first memory, add, to the management information, the first identification information and information indicating a position where second data is stored when the second data is stored in the second memory, add, to the management information, second identification information and information indicating a position where third data is stored when the third data is stored in the third memory, determine which one of the first identification information and the second identification information is associated with fourth data, and perform retrieval of the fourth data from the first memory or the second memory in accordance with information indicating a position where the fourth data is stored.

Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.

Abstract: A request to initiate a launch procedure of a compute instance at a virtualization host configured to access a remote storage device over a network is received. A memory buffer of the host is allocated as a write-back cache for use during a portion of the launch procedure. In response to a write request directed to remote storage during the portion of the launch procedure, the write payload is stored in the buffer and an indication of fulfillment of the write is provided independently of obtaining an acknowledgement that the payload has been propagated to the remote storage. Subsequent to the portion of the launch procedure, payloads of other write requests are transmitted to the remote storage device.

Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device may include a memory device including buffer blocks and main blocks, and a memory controller configured to control the memory device. The memory controller may include: a buffer block controller configured to control the memory device to store, in at least one of the main blocks, data stored in at least one of the buffer blocks; a mapping table manager configured to generate a P2P mapping table including mapping information between a buffer address that is a physical address of the at least one buffer block and a main address that is a physical address of the at least one main block; and a read operation controller configured to control, when a read request is received, the memory device to read the data based on the main address or the buffer address.

Abstract: A storage device includes a semiconductor memory device including a plurality of memory blocks; and a controller configured to control the semiconductor memory device, wherein the semiconductor memory device stores original firmware as default firmware and one or more copies of the original firmware as pieces of backup firmware in a first memory block among the plurality of memory blocks, and wherein the controller includes a firmware load circuit configured to load the default firmware when the default firmware is valid and load one of the pieces of backup firmware when the default firmware is not valid; and a firmware update circuit configured to update the default firmware from a previously updated version of the original firmware to a currently updated version of the original firmware.

Abstract: A non-volatile storage apparatus (e.g., an SSD, embedded memory, memory card, etc.) comprises non-volatile memory (e.g., one or more memory dies) connected to a control circuit (e.g., controller, state machine, microcontroller, etc.). The non-volatile memory is configured to have multiple regions for storing different types of data using separate streams. The control circuit is configured to receive a request to write data to a logical address, automatically choose a stream (and corresponding destination region) by determining which of the multiple regions/streams has a sequence of logical addresses associated with previous writes that best fits the logical address for the received data, and store the received data in the chosen destination region of the non-volatile memory using the chosen stream.