Abstract: A method is described that involves loading X bits at a time into a shift register and shifting groups of older, loaded X bits up in the shift register with each new group of loaded X bits. Each group of X bits has been received from a serial data stream. The method further involves identifying an alignment key within the shift register and presenting aligned data from the serial data stream by rotating selection of a first group of Y contiguous bits from the shift register and a second group of Y contiguous bits from the shift register after the identifying. Y is greater than X.

Abstract: An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components.

Abstract: An asynchronous FIFO is provided that determines whether its buffer is primed with at least one data element during a data transfer across clock domains in order to eliminate metastability issues that cause data stalls and interruptions in data flow.

Abstract: A data processing apparatus has a memory element array (330) having a plurality of entries each formed by a memory element of more than one bit having a data shift function and a data comparison function, and the memory element array is arranged so that data can be shifted between corresponding bit positions of adjacent entries. Further, the data processing apparatus has a priority-judging circuit (340) for identifying one of the entries according to predetermined priorities based on results of comparison between data input to the entries in common and contents held by the memory elements constituting the entries. Even when the data held by an entry located halfway is nullified, data shift between entries can avoid that the entry with nullified data remains halfway, and enables the entries to hold valid data in order with the data densely aligned. The time sequence when data are held can be made coincident with the alignment of entries readily.

Abstract: A system and method are described that manage incremental state updates in such a way that multiple threads within a processor can each operate, in effect, on their own set of state data. The system and method are applicable to any processor in which multiple threads require access to sets of state information which differ from one another by a relatively small number of state changes.

Abstract: A method of extending the life of a segmented memory device, consistent with certain embodiments involves providing a segmented memory device having a plurality of user defined segments with each segment having a starting and an ending address, and wherein the size and number of the segments is user defined; determining that a threshold number of write operations has been reached by reference to a write counter; copying data from a specified one of the segments to a temporary storage location; shifting the starting and ending address of each segment by a specified address increment; moving data stored in each segment except the specified segment by the specified address increment such that all data in the memory device has been shifted by the specified increment except for the data in the specified one of the segments, wherein data at a last segment is fragmented to wrap from an end of the memory device's addressable locations to a beginning of the memory device's addressable locations; copying the data from

Abstract: An improved programmable logic device provides increased efficiency and enhanced flexibility in configuration of block memories and includes one or more memory blocks and a vertical shift register that receives the data to be loaded in the memory blocks. The PLD further provides a selection device for selecting the memory cells in the memory blocks that are to store the received data, and a control block for controlling the loading of the data in the memory blocks. The selection device includes an address counter connected to the input of an address decoder so as to enable the selection of addresses in the memory blocks.

Abstract: Disclosed is a FIFO peek access device that utilizes a peek signal to access data stored in a FIFO without losing or erasing data. The peek signal is applied to read address logic and prevents the incrementing of the pointers in the peek address logic, so that after a read enable signal is asserted, the same data block can be accessed again on the next read enable signal.

Abstract: A system includes a queue that stores P data units, each data unit including multiple bytes. The system further includes a control unit that shifts, byte by byte, Q data units from the queue during a first system clock cycle, where Q<P, and sends, during the first system clock cycle, the Q data units to a processing device configured to process a maximum of Q data units per system clock cycle.

Abstract: A method of for accessing a first-in-first-out (FIFO) buffer is provided. The method comprises the following two steps. Firstly, issue a request to access a memory when the amount of the data buffered in the FIFO buffer is more than a threshold. Second, pop the data buffered in the FIFO buffer out to access the memory when the request is granted. If the FIFO buffer is a single-port FIFO buffer, the threshold is set based on the burst length of one burst of data. If the FIFO buffer is a dual-port FIFO buffer, the threshold is set based on the speed at which the data is pushed into the FIFO buffer and the speed at which the data is popped out of the FIFO buffer.

Abstract: A microprocessor architecture comprising a microprocessor operably coupled to a plurality of registers and arranged to execute at least one instruction. The microprocessor is arranged to determine a class of data operand. The at least one instruction comprises one or more codes in a register specifier that indicates whether relative addressing or absolute addressing is used in accessing a register. In this manner, absolute and relative register addressing is supported within a single instruction word.

Abstract: A method and system for the selective broadcasting of commands to a subset of a plurality of devices connected in series to a memory controller, where each of the plurality of devices has a unique identification number (ID). The memory controller designates the subset of devices to execute the command, excluding the non-selected devices from executing the command. The memory controller encodes the ID numbers of the designated devices into a single coded address, and sends the command along with the coded address in a packet to the series connected devices. Each device receives the packet in a serial bitstream and decodes the coded address using its ID number in order to determine whether it is selected or not. If the device is selected, the command is executed. Otherwise, the packet is forwarded without executing the command.

Abstract: A method of wear leveling for a non-volatile memory is disclosed. A non-volatile memory is divided into windows and gaps, with each gap between two adjacent windows. The windows comprise physical blocks mapped to logical addresses, and the gaps comprise physical blocks not mapped to logical addresses. The windows are shifted through the non-volatile memory in which the mapping to the physical blocks in the window to be shifted is changed to the physical blocks in the gap.

Abstract: A reset system for a buffer and a method thereof are disclosed. The reset system of the present invention includes a resettable flag in the buffer and a control unit. The reset method is to set the resettable flag and reset buffer so tat each exchanged processing unit can re-read data in the buffer for processing. Moreover, the buffer further includes an overwriteable flag so as to prevent the data in the buffer to be overwritten and get lost.

Abstract: A bit block transfer (Bitblt) circuit includes a read register, a write register, a bit shifting circuit and an overflowing register. The read register stores decomposition data including original data. The bit shifting circuit shifts the decomposition data in the read register to the write register and shifts bits of the decomposition data in the write register such that an initial bit of the original data of the decomposition data is situated apart from an initial address of the write register by a bit-shifting amount. The overflowing register coupled to the write register stores overflowing data of the original data overflowing from a memory length of the write register when the bits of the decomposition data in the write register are being shifted. The write register outputs and writes the decomposition data therein to a memory cell of a first memory.

Abstract: A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The macro-common register block has macro-common registers which are provided outside the plurality of memory macros and supply memory macro operation specifying signals to the plurality of memory macros. The memory macro operation setting circuits are respectively provided in the plurality of memory macros and are each configured to set an operating state of the memory macro in response to the memory macro operation specifying signal supplied from the macro-common register.

Abstract: A scheme for monitoring links in a point-to-point architecture computer system is discussed. The scheme monitors labels for transactions to determine if they have been reissued within a user selected time window. A corresponding position in a register is updated to reflect the value of the transaction identifier. Subsequently, after the expiration of a counter, the corresponding position in the registers is compared to other predetermined positions in other registers to determine if the transaction identifier has been used (reissued). Otherwise, a possible hang condition might have occurred.

Abstract: A memory system includes a memory cell array for storing data; and a register unit including one or more registers for storing system information. In the memory system, when a simultaneous access to the memory cell array and the register unit is requested, write data for the memory cell array is inputted after write data for the register unit is inputted, respectively through a common data input bus in a write operation, and read data from the memory cell array is outputted after read data from the register unit is outputted, respectively through a common data output bus in a read operation.

Abstract: A data output apparatus includes a disk drive for driving a magneto-optical disk. Compressed image data recorded on the magneto-optical disk is transferred from the magneto-optical disk to an SDRAM according to a transfer instruction set in an instruction list and then output through an expansion process by a JPEG codec. A size of the compressed image data for which the transfer instruction is set in the instruction list and which has not yet been transferred to the SDRAM, and a size of the compressed image data for which the transfer instruction is set in the instruction list and which has not yet been expanded are detected by a CPU. The CPU suspends an output of an expansion instruction to the JPEG codec when a difference between the detected sizes is below a threshold value.

Abstract: A method and circuit for updating a software register is disclosed, wherein the software register is updated using data received through a data I/O pad, and the updated data is read and transferred to the outside through the data I/O pad. The disclosed method of updating the software register includes the steps of receiving necessary data from a data I/O pad, writing the data received from the data I/O pad into the software register, thereby updating the software register, and reading the updated data from the software register, and transferring the data to the outside through the data I/O pad.

Abstract: A method and apparatus is provided to enable provision of requested data within two clock cycles when performing a swap operation between an accessible memory cell and a background memory in a computer. In a first clock cycle, memory addresses to be used in the swap operation are decoded. In a high phase of a second clock cycle, requested data is restored from the background memory to an accessible memory cell. Because the data previously stored in the accessible memory cell is duplicated in a shadow memory cell, the restoration of data to the accessible memory cell is performed without data loss. In a low phase of the second clock cycle, the requested data is available for reading. During a third cycle, data is saved from the shadow memory cell to the background memory, and the shadow memory cell is made consistent with the accessible memory cell.

Abstract: A semiconductor memory device is capable of controlling an address and data mask information through the use of a common part, thereby reducing chip size. The semiconductor memory device for receiving the addresses and data mask information via a common pin includes a buffer unit and a shift register unit. The buffer unit receives the addresses and data mask information. The shift register unit is comprised of a plurality of latch stages connected in series, for sequentially latching the addresses and data mask information being inputted in series, and an address output unit and a data mask information output unit for outputting information from different latch stages.

Abstract: A file system technique extends the life cycle of limited read/write media. Rewrite cycles of each file and/or each region of the media may be tracked. Different regions of the media are classified as static and dynamic based on their respective number of rewrite cycles. Static files are migrated to the more worn out or dynamic regions of the media, and dynamic files are integrated to the less worn out or static regions of the media. The file system is further sensitized by allocating a new file to an available region after a most recently used region. Where multiple versions of a data region exist, the file system marks a version of the data region as unstable after a certain number of rewrite cycles to the version and directs rewrite cycles to a subsequent version of the data region.

Abstract: Embodiments of the invention improve the cache hit ratio of read data. A hard disk drive (HDD) according to an embodiment of the present invention determines whether the read buffer should be used in its entirety or the partial continuous space should be used to read read-data from the magnetic disk. When the HDD determines use of the partial continuous space, the HDD specifies the sub-buffer which is a continuous space wherein the leading-end position and the trailing-end position are coupled to each other, and executes data writing to the sub-buffer in parallel with data reading from the sub-buffer and transmission thereof to the host. The sub-buffer capacity coincides with the data length of the back data.

Abstract: Circuitry for use in aligning bytes in a serial data signal (e.g., with deserializer circuitry that operates in part in response to a byte rate clock signal) includes a multistage shift register for shifting the serial data signal through a number of stages at least equal to (and in many cases, preferably more than) the number of bits in a byte. The output signal of any shift register stage can be selected as the output of the “bit slipping” circuitry so that any number of bits over a fairly wide range can be “slipped” to produce or help produce appropriately aligned bytes. The disclosed bit slipping circuitry is alternatively or additionally usable in helping to align (“deskew”) two or more serial data signals that are received via separate communication channels.

Abstract: A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design for register renaming allows processor hardware to use a larger set of registers than the architected registers visible to the compiler. This larger set of registers is called the physical register file. Thus, dynamically renaming every compiler-suggested architected register to a microarchitecture-specific physical register, allows the processor to overcome name dependencies and the hazards (pipeline slowdowns) induced by name dependencies.

Abstract: A synchronous multi-port memory including a plurality of ports coupled with a memory array, each of the plurality of ports including a delay stage to delay a memory access while a memory access arbitration is performed. The synchronous multi-port memory may also include selection logic coupled with the plurality of ports and the memory array to arbitrate among a plurality of contending memory access requests, to select a prevailing memory access request and to implement memory access controls.

Abstract: The executions of computer viruses are analyzed to develop register signatures for the viruses. The register signatures specify the sets of outputs the viruses produce when executed with a given set of inputs. A virus detection system (VDS) (400) holds a database (430) of the register signatures. The VDS (400) selects (710) a file that might contain a computer virus and identifies potential entry points in the file. The VDS (400) uses a virtual machine (422) having an initial state to emulate (714) a relatively small number of instructions at each entry point. While emulating each potential entry point, the VDS builds (716) a register table that tracks the state of a subset of the virtual registers (428). Once the VDS (400) reaches an emulation breakpoint, it analyzes the register table in view of the register signatures to determine whether the file contains a virus.

Abstract: A memory system has a plurality of memory modules and a global memory buffer. Each of the plurality of memory modules has at least two integrated circuit memory chips. The global memory buffer has a plurality of ports, each port coupled to a respective one of the plurality of memory modules. The global memory buffer stores information that is communicated with the plurality of memory modules. The global memory buffer has a communication port for coupling to a high-speed communication link.

Abstract: A device for transferring data signals between a first clock domain and a second clock domain comprises a serial memory element and a parallel memory element which are coupled. The serial memory element comprises at least one extra memory position more than the parallel memory element for the storage of the data signals.

Abstract: Double buffering of serial transfers is provided in order to allow for increased serial transfer rate without requiring increased internal processing speeds. A laser driver serial controller serially receives a word including address bits and data bits. During a write operation, the address bits are serially shifted into an address shift register of the laser driver, and the data bits are serially shifted into a data shift register of the laser driver. After the address bits and data bits are completely shifted into the respective address and data shift registers, the address bits and data bits are transferred in parallel to address and data holding registers of the laser driver. After the parallel transfers of the address bits and data bits from the address and data shift registers to the address and data holding registers, the address and data shift registers are available to serially receive additional address bits and data bits of an additional word.

Abstract: A data transfer apparatus has a controller configured to read out data in a predetermined sequential address area in units of a first byte count and to perform control for transferring the read-out data to a length register having a data area of a second byte count, the second byte count being the first byte count n times, where n is an integer equal to or more than “1”, a mask generator configured to generate mask information so that data already stored into the length register is not overwritten and to provide the controller with the mask information, when last data included in data in the predetermined address range read out from the memory is stored into the length register, and a bit circular configured to circulate each bit of data stored in the length register by the number of bytes in accordance with a lower side bit string of a start address of data in the predetermined address area read out from the memory.

Abstract: First-in-first-out (FIFO) memory system and method for providing the same is described. In one example, a dual-port memory circuit includes first storage locations for defining a plurality of FIFOs, second storage locations for storing status information for each of the FIFOs, a first port, and a second port. The first port includes a write data terminal for receiving write data and a write address terminal for receiving write addresses. Each of the write addresses includes a first portion for selecting a FIFO of the FIFOs and a second portion for selecting a storage location in the dual-port memory circuit. The second port includes a read data terminal for providing read data and a read address terminal for receiving read addresses. Each of the read addresses includes a first portion for selecting a FIFO of the FIFOs and a second portion for selecting a storage location in the dual-port memory circuit.

Abstract: A method for accessing digital data information is used for reducing accessing time when a processor accesses digital data from a register. The method comprises the steps of accessing data from a register with a processor, continuously accessing data from the register with the processor if the data in the register is valid, enabling an identifier register with the processor if the data in the register is invalid, transmitting an interrupt signal to the processor, disabling the identifier register with the processor, and accessing the data from the register with the processor.

Abstract: An electronic timer may include a clock reference signal generator and a real time clock (RTC) circuit for generating real time data based upon the clock reference signal. The RTC circuit may include a plurality of registers each for storing a respective bit of the real time data. Further, each register may include a master latch for initially storing the real time data bit, a slave latch for subsequently storing the real time data bit, and a user latch for storing the real time data bit from the slave latch. The RTC circuit may further include a controller for causing at least some of the registers to increment based upon the clock reference signal. Additionally, the electronic timer may also advantageously include a tamper circuit for receiving a tamper event signal and causing each of the user latches to hold a time stamp therein.

Abstract: A method, apparatus, and computer program product are provided for implementing an enhanced circular queue using loop counts for command processing. A circular queue includes a plurality of entries for storing commands. As command entries are added to the queue at the head of the queue, a head loop count is stored with each command entry. A head pointer is updated to the head of the queue. When the head pointer wraps from a last queue entry to a first queue entry, the head loop count is incremented. A tail pointer points to an oldest command entry, and is updated when the oldest command entry is executed. When the tail pointer advances and wraps from a last queue entry to a first queue entry, the tail pointer loop count is incremented.

Abstract: This disclosure generally relates to a processor configured to access an element in a data structure. The processor includes an element in a data structure having an array, an index, and a base address. A fractional shifter is also included and is configured to shift the index value up to three bit places, and output a byte offset. An adder is configured to add the byte offset with the base address and output a final address. Further included is a general purpose shifter that is configured to rotate left and right, and shift left and right. A selector is configured to select either the final address or an output signal from the general purpose shifter.

Abstract: A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first grou

Abstract: The present invention provides permutation instructions usable in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. PPERM and PPERM3R instructions are defined to perform permutations by a sequence of instructions with each sequence specifying the position in the source for each bit in the destination. In the PPERM instruction bits in the destination register that change are updated and bits in the destination register that do not change are set to zero. In the PPERM3R instruction bits in the destination register that change are updated and bits in the destination register that do not change are copied from intermediate result of previous PPERM3R instructions. Both PPERM and PPERM3R instructions can individually do permutation with bit repetition. Both PPERM and PPERM3R instructions can individually do permutation of bits stored in more than one register. In an alternate embodiment, a GRP instruction is defined to perform permutations.

Abstract: A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.

Abstract: Various embodiments of the invention relate to communicating data between a number of processing elements (PEs) of a signal processor, using a plurality of communication registers (CCRs). For instance, a plurality of the CCRs can be shared by and mapped to the address space of each PE, where each CCR couples a first of the PEs to every other one of the PEs. Moreover, each CCR can include a data payload field and a data valid field to indicate a target PE to read the data in the data payload field. Thus, data can be written to a selected CCR by a PE and stored in the selected CCR to be read by at least one target PE.

Abstract: A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs, and/or a block transfer engine (BTE) that optionally includes a serial cabinet-to-cabinet communications path (MLINK). In some embodiments, the processor TLBs are located within one or more common memory sections, each memory section being connected to a plurality of processors, wherein each processor TLB is associated with one of the processors. The BTE performs efficient memory-to-memory data transfers without further processor intervention. The MLINK extends the BTE functionality beyond a single cabinet.

Abstract: A Next Return Target Address stack to maintain return addresses for call and return operations. The invention accommodates both definite return addresses and speculative return address in a single stack. Return addresses are written into the stack and read out of the stack at an entry/exit register interior to the stack. The stack has a lower portion below the entry/exit register for maintaining both actual and speculative return addresses, and an upper portion above the entry/exit register for maintaining return addresses that have been speculatively popped out. A branch history register keeps an ongoing record of the most recent calls and returns. In the event of a pipeline flush, such as would be caused by a branch mispredict, the contents of the branch history register are examined to determine how to adjust the contents of the stack. One or more depth counters keep track of which contents in the branch history register are to be examined.

Abstract: A data input circuit converts input serial data to n-bit parallel data, and outputs the n-bit parallel data by following an address signal. The data input circuit includes a data shifting unit including a plurality of columns, and sequentially shifting the input serial data through the plurality of columns; and a selection unit selecting a column among the plurality of columns as an input column by following the address signal, wherein the input serial data is inputted to the data shifting unit through the input column. Thus, the data input device can speed up its processing speed with a simplified circuit structure whose circuit size is reduced.

Abstract: A method employs a bit sequence having a plurality of successive bits is stored in a write mode in a memory unit for a data value of a datum. The bit positions are each allocated to a data set which contains a data field for storing the datum. This measure enables logic operations to be carried out very rapidly.

Abstract: A graphics memory system of a graphics display system which utilizes a batching architecture in conjunction with detached Z buffering to minimize paging overhead is disclosed. The graphics memory system comprises a memory controller, which receives a batch of pixels from the graphics display system when a 3D rendering mode is in effect. Each pixel has a color and a corresponding Z coordinate. The memory controller performs a Z comparison test wherein Z coordinates of the batch are compared with existing Z coordinates read from a frame buffer to determine whether each new color of the batch associated with the compared Z coordinate should be written into the frame buffer. If the results of a Z comparison test pass, the new pixel color and Z coordinate are queued for writing into the frame buffer. A preferred embodiment of the graphics memory system uses two memory controllers, with each memory controller accessing its own frame buffer. Each frame buffer may be a RAM storage device.

Abstract: A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.

Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The memory hub includes a row cache memory that stores data as they are read from the memory devices. When the memory module is not being accessed by the controller, a sequencer in the memory module generates requests to read data from a row of memory cells. The data read responsive to the generated read requests are also stored in the row cache memory. As a result, read data in the row being accessed may be stored in the row cache memory even though the data was not previously read from the memory device responsive to a memory request from the controller.

Abstract: An asynchronous FIFO buffer communicates data between an input clock domain and a relatively slow output clock domain. The input clock frequency is not an even multiple of the output clock frequency, so the data transfer is asynchronous. The FIFO buffer includes a collection of input registers, a shift register, and some clock-comparison and write logic that controls the flow of data into, out of, and between these registers. The input data is loaded into the input registers in synchronization with the input clock. The clock-comparison and write logic compares the input and output clock signals and moves the data from the input registers to the shift register at an address value that may vary based on the result of the comparison of the input and output clock signals, skipping write cycles as necessary to avoid shifting data into the shift register faster than the data is shifted out.

Abstract: A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.