Abstract: A packet receiving circuit splits the packet received from a transmission channel into a fixed length of cells and outputs the cells, a search key extracting circuit extracts a predetermined search key from the above-mentioned cells, a CAM performs retrieval based on the above-mentioned search key and outputs a memory address corresponding to the search key, a matching entry address receiving and associative data address transmitting circuit calculates the memory address of an associative data memory based on the above-mentioned memory address and outputs the information stored in the associative data memory as associative data, a search result (associative data) receiving circuit receives the above-mentioned associative data and performs header updating and destination address of the above-mentioned cells, and a packet transmitting circuit outputs the above-mentioned cells in the form of a packet to a transmission channel.

Abstract: A random access memory array is used as a shift register. Data is written into different locations in a first column of the memory and then gradually transferred successively to any other number of columns in the memory. Such column-to-column data transfer is the result of reading data from each column and presenting it for writing in the next column. To compensate for latency (delay) in the column-to-column data transfer, the circuitry that controls reading is kept ahead of the circuitry that controls writing by a number of read/write cycles that takes approximately the same amount of time as the column-to-column data transfer delay.

Abstract: The present invention provides a controller that can write an operation program for a control circuit to a memory and a method for writing data, while suppressing an increase in circuit area and an increase in manufacturing cost. An ATA register is connected to a host computer. A flash ROM access register is connected to the ATA register. When a special command code 80h is sent to the ATA register from the host computer, data (a command and microcomputer control software) sent from the host computer is sent via the ATA register. A decoder decodes the data sent to the flash ROM access register and generates a format, an address, and data for writing the microcomputer control software to the flash ROM.

Abstract: A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first grou

Abstract: A method and apparatus for assembling non-aligned packet fragments over multiple cycles is described. In one embodiment, the invention is a method. The method includes rotating a non-aligned data fragment within a rotate register based on a tail pointer of a prior data fragment to form a rotated data fragment. The method also includes outputting the rotated data fragment to a double width bus as a double width image of the rotated data fragment. The method further includes selectively copying the double width image of the rotated data fragment from the bus to a location logically following the prior data fragment in a destination register.

Abstract: A memory array configured to operate as a shift register includes a first column of memory cells with an input and an output and at least a second column of memory cells with an input and an output. The memory array also includes a multiplexer that is connected between the output of the first column of memory cells and the input of the second column of memory cells. The memory array can be operated as a shift register by shifting data from the first column of memory cells to the second column of memory cells through the multiplexer rather than using general routing lines.

Abstract: A method and apparatus for resetting and modifying special registers in a security token is described. In one embodiment, a register may be reset when a reset flag is true when a special transmission on a bus demonstrates the mutual locality of the associated processor and chipset. A modify flag may also be used to indicate whether the register contents may be modified. Modifications may also be dependent upon demonstration of mutual locality.

Abstract: A hazard queue for a pipeline, such as a multiple-stage pipeline for transaction conversion, is disclosed. A transaction in the pipeline is determined to represent a hazard relative to another transaction, such as by evaluating the transaction against a hazard content-addressable memory (CAM). The hazard CAM can enforce various hazard rules, such as considering a transaction as active if it is referencing a memory line and is currently being processed within the pipeline, and ensuring that only one active transaction with a given coherent memory line is in the pipeline at a single time. In response to determining that a transaction is a hazard, the transaction is routed to a hazard queue, such as at the end of the pipeline. Once the hazard is released, the transaction re-enters the pipeline.

Abstract: A control register assembly controls components to be controlled in an electric circuit. The control register assembly includes a control register. The control register is formed by at least one shift register, whose elements are distributed over the electric circuit at mutual intervals, individually or in groups. Such a control register makes it possible to keep short the length of the connecting lines between the control register and the device writing the latter and between the control register and the elements to be controlled thereby.

Abstract: In a scannable D master-slave flip-flop circuit with synchronous preset or clear capability, the output of the slave latch is gated with the scan-enable signal to form the scan-data-output signal. This output gating of the scan-output data that allows for considerable simplification of the input logic. This simplification also provides for the reduction in both the size and the number of transistors in the input logic. This in turn is multiplied many tens of thousands of times in a complex processor chip, resulting in a substantial reduction in chip power and silicon area usage.

Abstract: A shift register is provided to monitor the difference between the read and write pulses to an elasticity buffer. The shift register essentially eliminates the need for any math functions in the elasticity buffer management logic. The shift register is as wide as the elasticity buffer is deep. In other words, for every word in the elasticity buffer, the shift register has a corresponding bit. Each time a word is written into the elasticity buffer without a simultaneous corresponding read, a value of “1” is shifted from a first end into the shift register, indicating that a space has been taken in the elasticity buffer. For every word read out of the elasticity buffer without a simultaneous corresponding write, a value of “0” (zero) is shifted from a second end of the shift register, indicating that one more space is available.

Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a FIFO array having a first plurality of memory elements, each memory element having a predetermined number of bits, the FIFO array having a read pointer. The apparatus also includes a FIFO control register array having a second plurality of memory elements, each memory element of the second plurality corresponding to a memory element of the first plurality of memory elements, the read pointer suitable for accessing the FIFO control register array. The apparatus further includes a control logic block coupled to the FIFO control register array and the FIFO array. The control logic block is to receive a data value of the memory element of the FIFO control register array pointed to by the read pointer. The control logic block is also to signal the read pointer to stall responsive to the data value having a first value.

Abstract: The present invention provides a speculatively loaded memory for use in a data processing system. The present invention may include a memory block including rows each identified by an address. A first register may store a first address of the memory block and a second register may store a second address of the memory block. A control circuit may be coupled to the first and second registers, and may receive control signals. The control circuit causes contents of the first register to be stored into the second register in response to a first state of the control signals, and the control circuit causes contents of the second register to be stored into the first register in response to a second state of the control signals.

Abstract: A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.

Abstract: Memory interleaving includes providing a non-power of two number of channels in a computing system and interleaving memory access among the channels.

Abstract: A circuit according to an embodiment of the present invention can load data in parallel to a barrel shifter, and output data to a pipelined multiplexer stage. The multiplexer is used to direct data from predetermined barrel slots to a predetermined number of output data slots. A control logic circuit will determine which of the barrel shifter entries are the oldest, and will drive the selects of the multiplexer to direct them to the output. The second stage of the multiplexer will drive the four 16-bit outputs to generate the 64-bit user data path. Methods for implementing the embodiments of the invention are also disclosed.

Abstract: The present invention comprises a dual bank FIFO memory buffer operable to buffer read data from memory and thereby compensate for specific timing problems in certain computerized systems. One embodiment of the invention includes a dual bank FIFO that comprises a first bank of memory elements operable to buffer memory data and a second bank of memory elements operable to buffer memory data. Write control address logic is operable to store selected memory data in memory elements with selected addresses within a bank of memory elements, and write control timing logic is operable to selectively grant write access to the banks of memory elements at predetermined time. Also, read control logic operable to read data stored in the first and second banks.

Abstract: A flip-flop circuit with embedded scan capabilities uses a skewed latch to pull one end of the flip-flop either up or down while another end of the flip-flop is active. Further, the flip-flop is designed such that a data node and a scan node are coupled to a master stage, which contains the skewed latch. The data node and scan node values are initially generated from different ends of the flip-flop. Based upon clock dependencies and whether the flip-flop is in a normal mode or a scan mode, the master stage passes a value to a slave stage dependent upon the data node and scan node values. Thereafter, the slave stage outputs a result based on the value passed from the master stage.

Abstract: The present invention may provide a digital memory circuit comprising a plurality of multi-bit registers, a memory circuit interface, and a logic circuit. The memory circuit interface may be configured to access a selected one of the registers. The logic circuit may be coupled to the plurality of multi-bit registers and responsive to data received through the interface for selectively writing a predetermined logic state to at least one first bit of the selected register while leaving at least one second bit in the selected register with an unmodified state.

Abstract: A mechanism for executing requests in a system. More specifically, a technique for processing requests to a memory system is provided. A shift register may be used to store an index associated with requests, such as read and write requests, to a memory system. Each request is stored in a respective queue depending on the source of the request and the request type (e.g. read or write). Each request includes flags which may be set to determine the processing order of the requests, such that out-of-order processing is feasible. An index corresponding to each of the requests is stored in an index shifter to facilitate the out-of-order processing of the requests. Alternatively, a shift register may be used to store each of the requests. Rather than shifting the indices to facilitate the out-of-order processing of requests, depending on the state of the corresponding request flags, the entire entry may be shifted.

Abstract: A speculative transmit function, utilizing a configurable logical buffer, is implemented in a network. When a transmission is started the logical buffer is configured as a FIFO to reduce transmit latency. If a data under-run lasts for more than a fixed time interval the transmission is abandoned and the logical buffer is reconfigured as a STORE-AND-FORWARD buffer. The transmission is restarted after all transmit data is buffered.

Abstract: First-in/first-out (“FIFO”) memory circuitry includes first and second Gray-code-based counters for respectively counting write and read clock signals. A Gray code subtractor subtracts from one another the counts output by the counters. Shift register circuitry shifts in successive data words in synchronism with the write clock signal. The shift register circuitry includes selection circuitry configured to select one of the data words based on a Gray code decoding of information from the subtractor. Circuitry may also be included to monitor the information from the subtractor to detect full or empty conditions of the shift register circuitry.

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.

Abstract: Circuits and methods for operating a latch structure are disclosed. The circuits include a plurality of stages, and each stage includes a first logic circuit, a latch coupled to a second logic circuit of an adjacent stage and a switch which connects the first logic circuit to the latch in a first state and disconnects the logic circuit from the latch in a second state. A local clock circuit controls the first and second states by providing a locally generated clock signal to activate the switch. The locally generated clock signals are generated by interlocking handshake signals from a local clock circuit of an adjacent stage.

Abstract: A buffer control device for controlling a buffer memory includes a comparing unit which compares input data with one or more data patterns, a control unit which stores a code which indicates a data pattern among data patterns into said buffer memory if the input data matches with the data pattern, and a recovering unit which recovers the input data from the code.

Abstract: A dynamic data queuing mechanism for network packets is disclosed. A three-dimensional coil may be expanded or contracted in length. In addition, the size of each loop of the three-dimensional coil may be adjusted. Moreover, simple circular queue and dynamic buffer management techniques are combined to implement circular queues that may be adjusted in size. Size adjustment, in turn, causes an entire queue either to expand or contract. Circular queue size is changed dynamically, without any copying or moving of queue data. This advantage is attained with little overhead added to conventional circular queues, and is useful in reducing memory requirements for simple circular queues by adjusting queue size as needs change. This is particularly useful for multiple queues that share the same memory space.

Abstract: A command buffer for use in packetized DRAM includes a two stage shift register for shifting for sequentially storing two of four 10-bit command words in each packet. After the first two words of each packet have been stored, they are transferred to a first storage register and output from the first storage register. After the final two words of each packet have been shifted into the shift register, they are transferred to a second storage register and output from the second storage register. The first two command words are output from the first storage register before the last two command words are applied to the command buffer. As a result, the DRAM can start processing the first two command words of the command packet before the entire command packet has been received.

Abstract: A method for processing multiple memory requests in a pipeline. Each memory request is processed in part by a plurality of stages. In a first stage, the memory request is decoded. In a second stage, the address information for the memory request is processed. In a third stage, the data for the memory request is transferred. A request buffer is used to hold each of the memory requests during the processing of each of the memory requests.

Abstract: A circuit for generating one or more serial bit streams includes a memory coupled to a reformatter, which is in turn coupled to a serializer for converting parallel data to serial data. The memory includes a plurality of words having a known bit width (e.g., 32 bits) for storing one or more serial bit streams. The length of each serial bit stream is generally not an integer multiple of the memory's bit width, causing the last word storing each serial bit stream to contain a gap. The reformatter eliminates each such gap by combining bits from the last word of a bit stream with bits from the first word to provide a completely filled word to the serializer. As operation proceeds, the reformatter continues to combine bits from successive words to ensure that completely filled words are produced. Gaps that formerly appeared when producing serial bit streams are thereby eliminated.

Abstract: A speculative transmit function, utilizing a configurable logical buffer, is implemented in a network. When a transmission is started the logical buffer is configured as a FIFO to reduce transmit latency. If a data under-run lasts for more than a fixed time interval the transmission is abandoned and the logical buffer is reconfigured as a STORE-AND-FORWARD buffer. The transmission is restarted after all transmit data is buffered.

Abstract: A method and apparatus for expediting the searching of a CAM array to obtain a matching or near-matching word is disclosed. In those cases where no word matches any of the words contained within the CAM array, a word that “almost” matches can be quickly found.

Abstract: In a clock switching circuit, a write address is generated based on a pre-switched clock, and the write address is employed to store input data in memory. Then, a read address is generated based on a post-switched clock, and the read address is employed to read data from memory, so that a clock synchronized with the data is changed. There are multiple pre-switched frequencies, and the frequency of a post-switched clock is higher than the frequency of a pre-switched clock. When the pre-switched clock frequency is lower than the post-switched clock frequency, the read address is updated in accordance with a ratio of the frequency of the pre-switched clock to the frequency of the post-switched clock.

Abstract: A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section controller. In this system, a data request for the data may be received over a communications path by a section controller. The section controller determines the addresses in the memory devices storing the requested data, transfers these addresses to those memory devices storing the requested data, and transfers an identifier to the memory interface device. The memory device, in response, reads the data and transfers the data to its corresponding memory interface device. The memory interface device then adds to the data the identifier it received from the section controller and forwards the requested bits towards their destination, such that the data need not pass through the section controller.

Abstract: A memory redundancy scheme is provided for re-routing data signal paths to disconnect defective memory blocks in a memory array. Each memory block is provided with a corresponding routing unit. Each routing unit is coupled to its corresponding memory block and at least one additional adjacent memory block. The routing units are configured to route data between functional memory blocks and a data bus. The routing units are controlled by configuration values stored in a shifter circuit, which extends through the routing units. To replace a defective memory block, the address of the defective memory block is identified. Configuration values are serially loaded into the shifter circuit, wherein the configuration values are selected in response to the address of the defective memory block.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data storage registers on the data communication connections during a predetermined number of consecutive clock cycles by adjusting a burst length of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.

Abstract: A method of managing ring-buffer memory space in a digital signal processor when processing a filter, includes releasing ring-buffer memory space previously reserved for ring-buffer data upon completing a filter process and determining that the ring-buffer data stored in said ring-buffer memory space is no longer necessary after the filter-process is carried out.

Abstract: A memory control unit has been developed. The control unit includes a command “spin wheel” which schedules the order of read and write commands to the memory. It also includes a read “spin wheel” which ensures proper timing of the read commands and a write “spin wheel” which ensures proper timing of the write commands.

Abstract: The invention relates to memory processing in a microprocessor. The microprocessor comprises a memory indicated by means of alignment boundaries for storing data, at least one register for storing data used during calculation, memory addressing means for indicating the memory by means of the alignment boundaries and for transferring data between the memory and the register, and a hardware shift register, which can be shifted with the accuracy of one bit, and which comprises a data loading zone and a guard zone. The memory addressing means transfer data including a memory addressing which cannot be fitted into the alignment boundary between the memory and the register through the data loading zone in the hardware shift register, and the hardware shift register is arranged to process data using shifts and utilizing the guard zone.

Abstract: The present invention introduces a configurable register file architecture of a processing device (microprocessor, CPU, DSP) with multi-range shift register support. Said register file has two working modes which can be simultaneously active such that in addition to behaving as a conventional register file, said register file can also be configured such that the registers of said register file form one or more shift registers whose ranges are specified by dedicated ‘range control’ inputs of said register file. By incorporating the functionality of shift registers into the register file, register renaming is achieved at almost no hardware overhead, allowing furthermore a reduction in overall power consumption and machine code size.

Abstract: The central processing unit is provided with an instruction queue storage section. This central processing unit is made of a memory, such as FIFO memory, that adopts first-in first-out method. A counter counters each time an instruction datum is stored in the instruction queue storage section. When the value of the counter is 0 or 1 and instruction fetch is not suppressed, a fetch request is issued.

Abstract: In order to enable a pointer register device including registers called shadow registers to conduct updating operation rapidly by arithmetic operation of a pointer value between the registers, a front/back register set includes a first register and a second register. A switch control section allows a read select switch and a write select switch to select different registers. When the read select switch selects the first register and the write select switch selects the second register, the sum obtained by an adder can be stored in the second register while retaining the pointer value of the first register. In this case, the pointer value need not be transferred between the registers.

Abstract: Data is written to an unsegmented buffer located within shared memory. While data is being written to the unsegmented buffer, at least a portion of the data is being read from the buffer. A counter is used to indicate how much space is available in the buffer to receive data. Further, the counter is employed to ensure that the reader does not advance beyond the writer.

Abstract: A circuit that may comprise a data-cache memory and a data-path circuit. The data-cache memory may be configured to (i) store a cache input data item among a plurality of associative sets and (ii) present a plurality of cache output data items. The data-path circuit may be configured to (i) independently shift each of the plurality of cache output data items and (ii) multiplex the plurality of shifted cache output data items to present an output data item.

Abstract: A method and circuit for determining the health of a microcontroller is provided having a circuit that includes a bus, a CPU coupled to the bus and a register coupled to the bus. A memory is also coupled to the bus. The memory is utilized by the first CPU. A controller is coupled to the register for controlling reading of the memory. The register generates a signature in response to the memory. The controller compares the reference signature and the second signature. The controller generated a fault signal when the reference signature is unequal to the second signature.

Abstract: An apparatus comprising one or more memory blocks in a programmable logic device. The memory blocks may be configured as content-addressable memory having arbitrarily adjustable tag and data widths.

Abstract: A system and method for memory management in a high-speed network environment. Multiple packets are interleaved in data streams and sent to a Memory Manager System. Read and write requests are queued in FIFO buffers. Subsets of these requests are grouped and ordered to optimize processing. This method employs a special arbitration scheme between read and write accesses. Read and write requests are treated as atomic. Memory bank selection is optimized for the request being processed. Alternating between memory bank sets is done to minimize bank conflicts. Link list updates are pipelined. Multiple independent link lists may be supported with the inclusion of a link list identifier. Arbitration between read and write requests continues until the group is exhausted. Then, processing is repeated for the next requests in the BRAM (buffer memories).

Abstract: A memory controller includes a memory unit having an n-byte memory data width, a register unit consecutively reading out, in response to an enable signal supplied thereto, data from the memory unit having n-byte size, the register unit further recording therein the data read out from the memory unit in the form of continuous data of 2n−1 bytes including the last data read out from the memory unit, a shifter unit selecting consecutively a block of continuous n-byte data from the continuous data of 2n−1 bytes recorded in the register unit, the shifter unit supplying the continuous n-byte data block to an output terminal, and a control unit controlling the memory unit, the register unit and the shifter unit.

Abstract: A Next Return Target Address stack to maintain return addresses for call and return operations. The invention accommodates both definite return addresses and speculative return address in a single stack. Return addresses are written into the stack and read out of the stack at an entry/exit register interior to the stack. The stack has a lower portion below the entry/exit register for maintaining both actual and speculative return addresses, and an upper portion above the entry/exit register for maintaining return. addresses that have been speculatively popped out. A branch history register keeps an ongoing record of the most recent calls and returns. In the event of a pipeline flush, such as would be caused by a branch mispredict, the contents of the branch history register are examined to determine how to adjust the contents of the stack. One or more depth counters keep track of which contents in the branch history register are to be examined.

Abstract: A modulus address generator calculates the next address to access from a current address of a circular buffer having a length L and an address shift from the current address to the next address to access. Within the circuit of the modulus address generator, a plurality of registers stores the length L of the circular buffer, the current address, and the address shift. A separator circuit generates an offset address and a base address from a mask value and the current address. A modulus calculation via a plurality of adders, and selectors is performed to calculate the next address of the circular buffer to access. A sign selector associated with an inverter and the separator circuit sets a wrap around flag depending on whether a wrap around the circular buffer has occurred during the modulus calculation of the next address to access.

Abstract: A first plurality of registers are daisy chained together with each register associated with a particular cache line. Similarly, a second plurality of registers are daisy chained together with each register associated with a cache line. The first daisy chain defines a fill order of cache lines and the second daisy chain defines a lock order for the cache lines.