Detachable Memory Patents (Class 711/115)
  • Patent number: 10558588
    Abstract: A processor includes a decode unit to decode an instruction that is to indicate a page of a protected container memory, and a storage location outside of the protected container memory. An execution unit, in response to the instruction, is to ensure that there are no writable references to the page of the protected container memory while it has a write protected state. The execution unit is to encrypt a copy of the page of the protected container memory. The execution unit is to store the encrypted copy of the page to the storage location outside of the protected container memory, after it has been ensured that there are no writable references. The execution unit is to leave the page of the protected container memory in the write protected state, which is also valid and readable, after the encrypted copy has been stored to the storage location.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Carlos V. Rozas, Mona Vij, Rebekah M. Leslie-Hurd, Krystof C. Zmudzinski, Somnath Chakrabarti, Francis X. Mckeen, Vincent R. Scarlata, Simon P. Johnson, Ilya Alexandrovich, Gilbert Neiger, Vedvyas Shanbhogue, Ittai Anati
  • Patent number: 10553259
    Abstract: A memory device configured to support multiple memory densities is provided. The memory device includes a first plurality of electrical contacts corresponding to a first command/address channel, a second plurality of electrical contacts corresponding to a second command/address channel, a third plurality of electrical contacts corresponding to a first data bus, a fourth plurality of electrical contacts corresponding to a second data bus, and mode selection circuitry configured to place the memory device in the first mode or the second mode. In the first mode, the first plurality of memory cells is operatively coupled to the first and third pluralities of electrical contacts and the second plurality of memory cells is operatively coupled to the second and fourth plurality of electrical contacts. In the second mode, the first and second pluralities of memory cells are both operatively coupled to the first and third pluralities of electrical contacts.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Martin Brox
  • Patent number: 10552360
    Abstract: According to one embodiment, when an external device is connected, the electronic device detects devices in the external device, and setup of detected devices. When the electronic device is powered, when a power state is restored from a hibernation or a sleep state to a normal state, or when the external device is connected, it is determined whether a first device is included in the detected devices. When the first device is included and when setup of a second device is failed, detection of devices and setup of detected devices are repeated.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 4, 2020
    Assignee: Toshiba Client Solutions CO., LTD.
    Inventor: Rinzo Iwamoto
  • Patent number: 10521986
    Abstract: A secure transport device includes a hardware storage, a physical lock coupled to the hardware storage, a data storage residing within the hardware storage, the data storage comprising a destination location comprising a first geophysical location, processor(s), and a computer readable medium comprising programming instructions. The data storage includes a destination location that includes a first geophysical location. Execution of the programming instructions causes the processor(s) to: receive an access request to access the hardware storage; obtain a current location of the secure transport device, the current location including a second geophysical location; and compare the first geophysical location to the second geophysical location. Upon determining that the second geophysical location matches the first geophysical location, a command is sent to unlock the physical lock to allow access to the hardware storage, and the access request and the current location are stored in the data storage.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: December 31, 2019
    Assignee: TP Lab, Inc.
    Inventor: Chi Fai Ho
  • Patent number: 10506709
    Abstract: An electronic circuit includes: a motherboard; an input/output connector including at least one group containing N input/output contacts; a set containing expansion slots having expansion contacts electrically connected to input/output contacts; each input/output contact being identified by an identifier T, each expansion slot being identified by an identifier S, each connected expansion contact being identified by an identifier R, for: each expansion slot of identifier S; and each connected expansion contact of identifier R. Each input/output contact of identifier T is electrically connected to a single expansion contact of identifier R of the expansion slot of identifier S, and the identifier T is calculated according to the following relation: T?[(R+D×S) modulo (N)], where D is fixed in each group and is an integer sub-multiple of the natural number N.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: December 10, 2019
    Assignee: ZODIAC AEROTECHNICS
    Inventor: Zoran Racic
  • Patent number: 10489325
    Abstract: A USB Type-C module has a plurality of ground pins including a first ground pin, a first configuration pin, a second configuration pin and a detector. The detector is electrically connected to the first ground pin and configured to detect a voltage value at the first ground pin so as to selectively enable a controller to determine a configuration of a corresponding connector via at least one of the first configuration pin and the second configuration pin.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: November 26, 2019
    Assignee: eEver Technology, Inc.
    Inventors: Yu-Chih Hsieh, Yuan-Bo Chang, Sian-Jia Chen
  • Patent number: 10489056
    Abstract: A queue manager apparatus converts inbound commands of a first width into scalar format commands to be queued in a command queue. Furthermore, the queue manager converts the scalar format commands residing in the command queue into outbound commands of a second width for transmission. Converting inbound commands to scalar format commands and then converting the scalar format commands to a target width for transmission allows the queue manager to advantageously provide efficient and programmable command transmission between arbitrary processing units, regardless of potentially mismatched native command widths.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: November 26, 2019
    Assignee: NVIDIA Corporation
    Inventor: John Erik Lindholm
  • Patent number: 10490524
    Abstract: An antenna apparatus includes a radio-frequency chip arranged on a substrate, wherein the radio-frequency chip includes at least one antenna output terminal and the antenna output terminal functions as a first fixing region for an electric conductor. The antenna apparatus further includes a first bond wire connecting in an electrically conducting manner the first fixing region to a second fixing region arranged on the substrate. Furthermore, the antenna apparatus includes a second bond wire connecting in an electrically conducting manner the second fixing region and a third fixing region arranged on the substrate. According to the invention, the first and the second bond wire electrically connected in series form an antenna. In this case, the first and second bond wires are at least regionally spaced apart from the substrate.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: November 26, 2019
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventor: Ivan Ndip
  • Patent number: 10467018
    Abstract: A method of booting a host device includes enabling or disabling a ready boot option within a basic input-output system (BIOS) of a host device. A normal boot is performed to load a first operating system (OS), that is stored in an internal storage of the host device, to a main memory of the host device when the ready boot option is disabled. A boot operation to load a second OS, that is stored in an internal storage of a mobile device, to the main memory of the host device is performed when the ready boot option is enabled. An individualized user environment for the host device, is provided by booting the host device from the mobile device. The individualized user environment is easily realized as the user need only connect the mobile device to a designated USB port of the host device prior to restarting the host device.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Young-Jin Park
  • Patent number: 10468127
    Abstract: A portable data-management system may be easily employed with multiple processing devices by eliminating the need to pre-install additional programs, agents, device drivers, or other software components on the hosts. A portable storage device contains software for a data-management application, which receives and processes test data from a meter that measures an analyte. The portable device may employ an interface protocol that makes the portable device immediately compatible with different operating systems and hardware configurations. Once the portable device is connected to the host, the data-management application can be automatically launched. The convenience and portability of a data-management system may be enhanced by integrating advanced data processing and display features with the portable device. The users may access some advanced presentations of health data without having to launch the data-management application on a separate host.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 5, 2019
    Assignee: ASCENSIA DIABETES CARE HOLDINGS AG
    Inventors: Darren Brown, Jun Chen, Igor Gofman, Steven B. Harris, Paul L. Inman, Richard Kates, Qiong Li, Harris Lieber, Paul M. Ripley, Gregory Stefkovic, Hoi-Cheong Steve Sun, Mu Wu, Raymond Yao, Simin Yao
  • Patent number: 10466911
    Abstract: A method for control of latency information through logical block addressing is described comprising receiving a computer command, performing a read flow operation on a computer buffer memory based on the computer command; populating at least one metadata frame with data based on logical block address latency information; initiating a serial attached data path transfer for one of transmitting and receiving data to the computer drive and transmitting data to a host based on the second latency.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 5, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Darin Edward Gerhart, Nicholas Edward Ortmeier, Mark David Erickson
  • Patent number: 10459660
    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: October 29, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Scott C. Best
  • Patent number: 10445024
    Abstract: A semiconductor integrated card includes an external package, a subscriber identification module (SIM) circuit, a plurality of SIM pins, a storage device and a plurality of memory pins. The SIM circuit is formed inside of the external package and is configured to store subscriber information. The SIM pins are formed on a surface of the external package and are electrically connected to the SIM circuit. The storage device is formed inside of the external package and is separated from the SIM circuit. The storage device includes a nonvolatile memory device. The memory pins are formed on the surface of the external package and are electrically connected to the storage device.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hui-Kwon Seo
  • Patent number: 10430333
    Abstract: An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 1, 2019
    Inventors: Peng Li, Jawad B. Khan, Sanjeev N. Trika
  • Patent number: 10402140
    Abstract: A portable memory device, for example a universal serial bus (“USB”) flash drive that can inform the user, via a display, device information, for example, its capacity may be full or nearly full without the need to connect to a computer or separate processing device. The portable memory device supports various interconnectors for connecting to USB interfaces of different specifications, including any and all revised USB specifications as determined by the industry standard.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: September 3, 2019
    Inventor: Steven Mazurek
  • Patent number: 10402352
    Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: September 3, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil
  • Patent number: 10367698
    Abstract: Access and regulations systems to facilitate safe and secure access of web content by residents of an institutional facility such as a correctional facility includes an administrator workstation to define authorized and prohibited web content, a resident workstation displaying on a predetermined list of web content, and a server receiving and processing the authorized and prohibited web content and requests made by institutional residents.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: July 30, 2019
    Assignee: KEEFE GROUP, LLC
    Inventor: Atul Gupta
  • Patent number: 10332568
    Abstract: A memory module includes a module substrate. The module substrate includes a plurality of regions, on which a plurality of memory apparatuses are mounted. A plurality of inductors are formed in the plurality of regions of the memory module substrate, respectively.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 25, 2019
    Assignee: SK hynix Inc.
    Inventor: Kyung Hoon Kim
  • Patent number: 10331699
    Abstract: A method and an apparatus for data backup are disclosed. The method includes querying a slave for check information, where the check information is data inserted into a master when data written to the master is copied into the slave in a form of a log; obtaining a time at which the check information is inserted into the master and setting the time as a backup completion time point; and deleting data record(s) that is/are earlier than the backup completion time point from mirrored data, the mirrored data being data that is synchronously written to a defined storage space when the data is written to the master. The method for data backup is easy to implement at a low cost, and provides highly secure data backup.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 25, 2019
    Assignee: Alibaba Group Holding Limited
    Inventors: Yunliang Shi, Huabing Du
  • Patent number: 10318179
    Abstract: A host device includes a first serial peripheral interface (SPI) and a second SPI to communicate with an embedded multimedia card (eMMC) device. The host device has a mode controller that controls the first SPI to toggle between first transmission and first reception modes for command transmission and response reception, respectively. The mode controller controls the second SPI to toggle between second transmission and second reception modes for data transmission and data reception, respectively.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: June 11, 2019
    Assignee: NXP B.V.
    Inventors: Bin Er, Wenwei Jiang, Xiaodong Niu, Yan Song
  • Patent number: 10318201
    Abstract: Systems and methods for managing content in a flash memory. Content or data in a flash memory is overwritten when the write operation only requires bits to be set. This improves performance of the flash and extends the life of the flash memory.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 11, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Grant R. Wallace, Philip N. Shilane
  • Patent number: 10291681
    Abstract: A system and method for facilitating directory limit based storage scheme for uploading media segments in multiple directories at one or more media servers. Directory limit parametric information may be signaled in an MPD document for enabling a DASH client device to construct URLs based on the received directory parametric information via a modified/extended SegmentTemplate element of the MPD document.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: May 14, 2019
    Assignee: ERICSSON AB
    Inventors: Raj Nair, Prabhudev Navali
  • Patent number: 10289603
    Abstract: A system can monitor data usage, including an amount of searchable data used and/or a rate at which the searchable data is manipulated, on a storage allocation in a networked environment. The storage allocation can have a quantity/number of partitions, including at least one partition, configured to store the searchable data. The system can detect that the data usage is beyond a specified threshold and then based at least in part on factors such as network traffic, CPU usage, and/or data usage, the system can modify the storage allocation to increase or decrease a size of the partition and/or the quantity of partitions. Network traffic for the storage allocation can be directed away from the portion of the storage allocation being modified. When modifying the storage allocation is complete, the network traffic can be directed to the modified portion of the storage allocation.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: May 14, 2019
    Assignee: Amazon TEchnologies, Inc.
    Inventors: Jonathan Michael Goldberg, Asif Mansoor Ali Makhani, Ekechi Karl Edozle Nwokah
  • Patent number: 10261852
    Abstract: A technique includes accessing error information generated in response to memory errors of a memory device. The error information generated in response to the memory errors of the memory device may then be determined as indicative of a row hammer error for the memory device.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: April 16, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Andrew C. Walton
  • Patent number: 10261693
    Abstract: A storage system in one embodiment comprises a plurality of storage devices configured to store user data pages and metadata pages. Each of the user data pages has a logical address and a content-based signature derived from content of that data page, and each of the metadata pages characterizes a plurality of the user data pages and associates the content-based signatures of those user data pages with respective physical blocks in the storage devices. In conjunction with release of logical address space in the storage system, the released logical address space is made available to users in a first order based at least in part on released logical address, and multiple dereferencing operations are accumulated for respective ones of the physical blocks corresponding to the released logical address space. The accumulated dereferencing operations for the physical blocks are executed in a second order that differs from the first order.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 16, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Zvi Schneider, Anton Kucherov, Uri Shabi
  • Patent number: 10236617
    Abstract: An electrical connector includes a pair of housing units side by side arranged with each other and equipped with the corresponding contacts, respectively. A pair of protection caps are assembled to the corresponding housing units horizontally in opposite directions, respectively. A linking part is mounted upon the pair of caps with a rigid suction region thereof in a symmetrical manner. The linking part is downwardly mounted upon the pair of caps with corresponding standoffs to space the main part of the linking part from the caps in the vertical direction so as not to block the related heat dissipation.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: March 19, 2019
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Shuo-Hsiu Hsu, Chang-Long Zheng, Qi-Jin Yi, Fu-Jin Peng
  • Patent number: 10223061
    Abstract: An aspect includes a computer implemented method for display redistribution between a personal display and an external display. The method includes initiating, by a primary device, a wireless connection between a primary device and a secondary device. The primary device includes a primary display and the secondary device includes a secondary display. A confirmation is received at the primary device from the secondary device in response to the initiating. Based on receiving the confirmation, the wireless connection between the primary device and the secondary device is executed. The executing includes utilizing, by the primary device, the secondary display in place of the primary display.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eli M. Dow, Thomas D. Fitzsimmons, Tynan J. Garrett, Emily M. Metruck, Charles J. Stocker, IV
  • Patent number: 10203924
    Abstract: A display apparatus, a controlling method thereof and a controlling method of a display system are provided. The controlling method of a first display apparatus includes receiving setting information from an external storage medium in response to the first display apparatus being connected to the storage medium; and in response to the first display apparatus being set as a master device according to the setting information, transmitting reproduction time information of image contents to a second display apparatus, synchronizing the second display apparatus with the first display apparatus with respect to the image contents, and reproducing the synchronized image contents.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-hyuck Hong, Jae-hwang Lee, Pureunsol Ku
  • Patent number: 10162766
    Abstract: The multi-level storage system and method of deleting first level storage structure pages or records without record locks. The method includes determining whether a record to be deleted from the first level storage structure has any uncommitted write operation, and if the record has an uncommitted write operation, the record is kept in the first level storage structure. Record-moved version information is added to the record to designate the record being moved from the first level storage structure to the second level storage structure. Data change operations are executed for the record based on the record-moved version information without waiting until the record's movement from the first level storage structure to the second level storage structure finishes.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 25, 2018
    Assignee: SAP SE
    Inventors: Franz Faerber, Juchang Lee, Ivan Schreter
  • Patent number: 10152237
    Abstract: The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Robert M. Walker, James A. Hall, Jr., Frank F. Ross
  • Patent number: 10127039
    Abstract: A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a micro-architectural state and an architectural state of a processor in a common buffer of a memory upon a context switch that suspends the execution of a process. The micro-architectural state contains performance data resulting from the execution of the process. A restore instruction is executed to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process. Power management hardware then uses the micro-architectural state as an intermediate starting point for the resumed execution.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Eliezer Weissmann, Michael Mishaeli, Boris Ginzburg, Alon Naveh
  • Patent number: 10114122
    Abstract: The present disclosure describes methods and systems for measuring crosswind speed by optical measurement of laser scintillation. One method includes projecting radiation into a medium, receiving, over time, with a photodetector receiver, a plurality of scintillation patterns of scattered radiation, comparing cumulative a radiation intensity for each received scintillation pattern of the received plurality of scintillation patterns, and measuring a cumulative weighted average cross-movement within the medium using the compared cumulative radiation intensities.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: October 30, 2018
    Assignee: Torrey Pines Logic, Inc.
    Inventor: Leo Volfson
  • Patent number: 10095411
    Abstract: Solid state drives may include a controller, a mapping table and a buffer memory. The controller provides a logical address of associated data through a first input-output unit at a first speed and provides the associated data through a second input-output unit at a second speed. The controller may be connected to the first input-output unit and the second input-output unit. The mapping table may be connected to the controller through the first input-output unit. The buffer memory may be connected to the controller through the second input-output unit. The first input-output unit may be physically separated from the second input-output unit. The first speed may be different from the second speed.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Woon Park, Byung-Ho Kim
  • Patent number: 10079211
    Abstract: An integrated circuit device or devices is presented that include internal connection ports to transmit data to or receive data from a first portion of the integrated circuit device. The integrated circuit device(s) also include external connection ports to transmit data to or receive data from outside the integrated circuit device, such as between integrated circuit devices. The integrated circuit device also includes remapping circuitry that remaps from a first connection between a first internal connection port of the internal connection ports and a first external connection port of the external connection ports to a second connection between a second internal connection port of the internal connection ports and a second external connection port of the external connection ports.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 18, 2018
    Assignee: INTEL CORPORATION
    Inventor: Chee Hak Teh
  • Patent number: 10074426
    Abstract: A memory device having a resistance change material and an operating method of the memory device are provided. A memory device includes a memory cell array including first and second resistive memory cells, which store different data according to the change of their resistance; a buffer including first and second storage regions corresponding to the first and second resistive memory cells, respectively; and a control circuit receiving program data to be programmed to the memory cell array, comparing first data stored in the first storage region and second data stored in the first resistive memory cell, and as a result of the comparison determining one of the first and second storage regions as a storage region to which to write the program data.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: September 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chea Ouk Lim, Hyun Kook Park, Jung Sunwoo, Young Hoon Oh, Yong Jun Lee
  • Patent number: 10073804
    Abstract: A computer includes: first and second connectors; and a data transmission path. The first connector includes: a first connector body to which at least a first module is capable of being attached; and a first electrode portion which is connected with the data transmission path. The first electrode portion is electrically connected with the first module when the first module is attached to the first connector body. The second connector includes: a second connector body to which at least the first module and a second module are alternatively capable of being attached; and a second electrode portion which is connected with the data transmission path. The second electrode portion is electrically connected with the second module when the second module is attached to the second connector body. The second electrode portion is electrically disconnected from the first module when the first module is attached to the second connector body.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: September 11, 2018
    Assignee: NEC Corporation
    Inventor: Kazuya Uchida
  • Patent number: 10051764
    Abstract: An electronic equipment chassis in one embodiment comprises a housing having a front portion and a rear portion, at least one row of dual in-line memory modules disposed at one of an upper level and a lower level of the front portion, and a plurality of storage devices arranged in the front portion adjacent the at least one row of dual in-line memory modules. At least a subset of the dual in-line memory modules and the storage devices are configured so as to be removable from the chassis through a vertical plane of the front portion of the housing.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: August 14, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Ralph C. Frangioso, Jr., Robert Wierzbicki
  • Patent number: 10038727
    Abstract: Methods and systems for providing a communication system in a controlled environment are disclosed herein. A communication server establishes a communication session between client devices located within a controlled environment, and routes communication data between the client devices via the communication session. In some embodiments, the communication server stores the communication data as confidential communications based on profile information corresponding to the clients associated with the client devices. Further, the communication server manages access to the confidential communications based on profile information associated with the clients, and the subject matter of the confidential communications.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 31, 2018
    Assignee: GLOBAL TEL*LINK CORPORATION
    Inventor: Stephen Lee Hodge
  • Patent number: 10037164
    Abstract: Systems and methods for managing content in a flash memory. Content or data in a flash memory is overwritten when the write operation only requires bits to be set. This improves performance of the flash and extends the life of the flash memory.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: July 31, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Grant R. Wallace, Philip N. Shilane
  • Patent number: 9990143
    Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application, and accessing data storage memory through the first and second memory devices.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: June 5, 2018
    Assignee: SK Hynix Inc.
    Inventors: Do-Yun Lee, Min-Chang Kim, Chang-Hyun Kim, Yong-Woo Lee, Jae-Jin Lee, Hoe-Kwon Jung
  • Patent number: 9927975
    Abstract: A multi-mode hybrid memory drive comprises a bulk memory device and a removable cache memory device. A controller of the bulk memory device may be configured to operate the bulk memory device in either a stand-alone mode or a hybrid mode responsive to detecting the removable cache memory device being coupled with a cache port of the bulk memory device. A method of operating a multi-mode hybrid drive may also comprise monitoring a cache port of a bulk memory device to determine a presence of a removable cache memory device, operating the bulk memory device as a stand-alone drive responsive to determining the removable cache memory device is not present, and operating the bulk memory device as a hybrid drive using the removable cache memory device as a data cache responsive to determining the removable cache memory device is present. Additional hybrid memory drives and computer systems are also described.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: March 27, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Thomas L. Pratt
  • Patent number: 9921772
    Abstract: A semiconductor memory device includes a NAND memory including a plurality of blocks, each of which is a unit of data erasing, and a controller. The controller is configured to select an initial value from a group of initial values, based on an address of the NAND memory in which data are to be written, set a value corresponding to the selected initial value to a linear feedback shift register circuit, randomize the data using an output value of the linear feedback shift register circuit, and write the randomized data to the address of the NAND memory. A size of each of the blocks S is smaller than 2n?1 bytes, n being a number of registers included in the linear feedback shift register circuit.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: March 20, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Tsuyoshi Atsumi, Yasuhiko Kurosawa
  • Patent number: 9910610
    Abstract: A multiple application smart card uses hardware firewalls and an internal communications scheme to isolate applications from different service providers. A first application from a first service provider is stored within a first supplemental security domain of a memory device on the multiple application smart card. A second application from a second service provider is stored within a second SSD of the memory device. A hardware firewall is located between the first and second applications of the first and second SSDs. The hardware firewall prevents direct data access between the first and second applications of the first and second SSDs.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: March 6, 2018
    Assignee: NXP B.V.
    Inventors: Ralf Malzahn, Francesco Gallo
  • Patent number: 9880772
    Abstract: A memory device includes a memory component and controller circuitry. The memory component stores data and the controller circuitry receives, from a host electronic device, one or more commands of a memory system protocol. The one or more commands include at least one write command, the write command comprising one or more blocks of data to be stored in the memory component. Further, the one or more commands include metadata, attributes, or both related to the one or more blocks of data. The controller circuitry interprets and executes the one or more commands. Accordingly, the blocks are stored in the memory component. Further, the controller circuitry of the memory device has access to the metadata, attributes or both.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: January 30, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Danilo Caraccio, Graziano Mirichigni, Gianfranco Santopietro, Gianfranco Ferrante, Emanuele Confalonieri
  • Patent number: 9880787
    Abstract: A patching system and a patching circuit provide a type of patching entry which can replace several sequential memory positions with hardcoded and dynamically configured assembly instructions, thus injecting a small piece of code. The operation of the injected code can be for any purpose, but as an example may be used to seamlessly redirect the execution flow of a processing unit.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: January 30, 2018
    Assignee: Dialog Semiconductor B.V.
    Inventor: Konstantinos Ninos
  • Patent number: 9865143
    Abstract: The present invention discloses a status displaying device and method thereof for a Solid-State Drive (SSD). The status displaying device may include a non-volatile memory, an emitting unit, a firmware, and a first control unit. A first instruction is generated and transmitted by the firmware. The first instruction is received by the first control unit. The first control unit performs a first operation on the non-volatile memory and controls the emitting unit to have a first emitting behavior according to the first instruction.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: January 9, 2018
    Assignee: APACER TECHNOLOGY INC.
    Inventor: Meng-Hung Tsai
  • Patent number: 9843589
    Abstract: Access and regulations systems to facilitate safe and secure access of web content by residents of an institutional facility such as a correctional facility includes an administrator workstation to define authorized and prohibited web content and associated secondary restrictions, a resident workstation displaying on a predetermined list of web content, and a server receiving and processing the authorized and prohibited web content and requests made by institutional residents.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: December 12, 2017
    Assignee: KEEFE GROUP, LLC
    Inventor: Atul Gupta
  • Patent number: 9829951
    Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to enhance support to sleep states. The computer system includes a processor, a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable, and power management (PM) module. A dynamic random access memory (DRAM) provides a portion of system address space. The PM module intercepts a request initiated by an operating system for entry into a sleep state, copies data from the DRAM to the NVRAM, maps the portion of the system address space from the DRAM to the NVRAM, and turns off the DRAM when transitioning into the sleep state. Upon occurrence of a wake event, the PM module returns control to the operating system such that the computer system resumes working state operations without the operating system knowing that the portion of the system address space has been mapped to the NVRAM.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Mohan J. Kumar, Murugasamy K. Nachimuthu
  • Patent number: 9760524
    Abstract: In certain information handling system environments, universal serial bus (USB) attached small computer interface (SCSI) protocol (UASP) devices may be connected to a client and redirected to a server or other information handling system. Some operating systems (OS) of a server may not support UASP. Rather than installing non-certified or expensive third party software, a virtual disk enumerator may retrieve the relevant information of the redirected UASP device and determine that all requests to the virtual UASP device must be redirected to the disk stack of the client for processing.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: September 12, 2017
    Assignee: Dell Products L.P.
    Inventor: Gokul T. Vajravel
  • Patent number: 9734112
    Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: August 15, 2017
    Assignee: Rambus Inc.
    Inventors: Liji Gopalakrishnan, Ian Shaeffer, Yi Lu