Detachable Memory Patents (Class 711/115)
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Patent number: 12124345Abstract: A command to transfer data in a portion of a memory component to a recovery portion of a different memory component is received from a host system, wherein the portion of the memory component is associated with a portion of the memory component that has failed, and the data in the portion of the memory component is recovered and transferred to the recovery portion of the different memory component without moving or processing the data through the host system responsive to receipt of the command.Type: GrantFiled: July 15, 2021Date of Patent: October 22, 2024Assignee: Micron Technology, Inc.Inventor: David G. Springberg
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Patent number: 12086227Abstract: A device includes memory and a processor. The device receives biometric information. The device receives location information. The device analyzes the received biometric information with stored biometric information. The device analyzes the received location information with stored location information. The device determines whether the received biometric information matches the stored biometric information. The device determines whether the received location information matches the stored location information. The device sends an electronic communication that indicates whether the received biometric information matches the stored biometric information and whether the received local information matches the stored location information.Type: GrantFiled: April 3, 2023Date of Patent: September 10, 2024Assignee: Visitlock LLCInventor: Kevin Robert Phillips
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Patent number: 12066936Abstract: An example cache memory includes a schedule module, control modules, a datapath, and an output module. The cache memory receives requests to read and/or write cache lines. The schedule module maintains a queue of the requests. The schedule module may assign the requests to the control modules based on the queue. A control module, which receives a request, controls the datapath to execute the request, i.e., to read or write the cache line. The control module can control the execution by the datapath from start to end. Multiple control modules may control parallel executions by the datapath. The output module outputs, e.g., to a processor, responses of the cache memory to the requests after the executions. A response may include a cache line. The cache memory may include a buffer that temporarily stores cache lines before the output to avoid deadlock in the datapath during the parallel executions of requests.Type: GrantFiled: March 21, 2022Date of Patent: August 20, 2024Assignee: Habana Labs Ltd.Inventors: Ehud Eliaz, Eitan Joshua, Yori Teichman, Ofer Eizenberg
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Patent number: 12051470Abstract: A memory controller capable of sequentially increasing or decreasing a total current consumed by a plurality of memory devices, controls a plurality of memory devices coupled through a plurality of channels. The memory controller includes a request checker for identifying memory devices corresponding to requests received from a host among the plurality of memory devices, and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager for outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator for sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse.Type: GrantFiled: February 25, 2022Date of Patent: July 30, 2024Assignee: SK hynix Inc.Inventor: Sung Yeob Cho
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Patent number: 12050822Abstract: The present disclosure provides an access request response method, a consumable chip and a storage medium. The method includes receiving an access request sent by a printing device, the access request including address information; determining at least one second-type address in memory correspondingly according to the address information, a second-type address corresponding to at least two addresses in the address information; and responding to the access request through the at least one second-type address.Type: GrantFiled: December 28, 2022Date of Patent: July 30, 2024Assignee: GEEHY MICROELECTRONICS INC.Inventors: Weichen Liu, Liang Chen
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Patent number: 12026117Abstract: A data transfer system, which comprises a system host and an adaptor including a local host, is provided. The adaptor is connectable to a local device inserted into the adaptor and includes a switch unit configured to perform address translation and Requestor (Req) ID translation for data transfers between the local device and the system host. The system host checks, when the local device is inserted or removed while the system host is in operation, a type of a protocol applied to the local device and reloads a device driver based on a result of the check. The device driver includes a pre-sleep state storage configured to store an insertion and removal state of the local device immediately before the system host and the adaptor enter a sleep state.Type: GrantFiled: August 25, 2020Date of Patent: July 2, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hideaki Yamashita, Takeshi Ootsuka
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Patent number: 11971838Abstract: A data transmission apparatus includes: a first port and a second port which are selected by a first control signal; a first signal path and a second signal path which are selected by a second control signal. When a memory card satisfies a first condition, the first control signal selects the first port and the second control signal selects the first signal path, the data transmission apparatus connects the host device and the memory card via the first port and the first signal path and works in a first transmission mode. When the memory card satisfies a second condition, the first control signal selects the second port and the second control signal selects the second signal path, the data transmission apparatus connects the host device and the memory card via the second port and the second signal path and works in a second transmission mode.Type: GrantFiled: March 2, 2022Date of Patent: April 30, 2024Assignee: SUZHOU BAYHUB ELECTRONICS TECHNOIInventors: Yishao-Max Huang, Xiaoguang Yu, Katsutoshi Akagi, Hongzhang Wang, Zhenlun Allen Li
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Patent number: 11942172Abstract: A chip having a debug function includes functional circuitries, a selector circuitry, a data reconstruction circuitry, and a switching circuitry. Each functional circuitry includes a decoder circuit that stores a corresponding set of debug signals and outputs a corresponding debug signal in the corresponding set of debug signals to be a corresponding signal in first signals according to a corresponding address signal in address signals. The selector circuitry selects second signals from the first signals according to the address signals. The data reconstruction circuitry selects first data from the second signals according to split signals and outputs the same to be debug data. Each first data is partial data of a corresponding signal in the second signals. The switching circuitry determines whether to output the debug data or at least one output signal associated with the functional circuitries via output ports according to switching signals.Type: GrantFiled: August 30, 2022Date of Patent: March 26, 2024Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Pan-Ting Jiang, Zan Li
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Patent number: 11940938Abstract: A hypervisor is configured to bridge I/O operations between the NVMeoPCIe version of the NVMe I/O protocol and the NVMeoF version of the NVMe I/O protocol. By providing a bridging hypervisor, guests can use the NVMePCIe version of the NVMe I/O protocol for storage access operations, while the hypervisor can use the NVMeoF version of the NVMe I/O protocol to implement the storage access operations on attached storage resources of the storage system. The hypervisor handles administrative actions associated with creating, managing, and destroying submission queues and completion queues. Once the desired queue configuration has been created, NVMeoPCIe I/O operations are able to be transparently bridged by the hypervisor, which greatly reduces the amount of processing that would be required if the hypervisor were required to terminate each NVMeoPCIe I/O operation, generate corresponding NVMeoF I/O operations, and keep track of each such pair of I/O operations.Type: GrantFiled: July 1, 2022Date of Patent: March 26, 2024Assignee: Dell Products, L.P.Inventor: Matthew H. Fredette
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Patent number: 11911148Abstract: Presented are concepts for monitoring walker usage by a subject. One such concept obtains movement data comprising values of detected movement of an arm of the subject for a first time period during which the subject is determined to have transferred between first and second locations the first time period. It is determined if the subject used a walker during the first time period based on a measure of variance in the values of detected movement of the subject's arm during the first time period.Type: GrantFiled: October 16, 2019Date of Patent: February 27, 2024Assignee: Koninklijke Philips N.V.Inventors: Warner Rudolph Theophile Ten Kate, Doortje Van De Wouw
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Patent number: 11914900Abstract: A storage system receives an instruction to cancel an in-progress read/write command. The storage system allows data associated with the command to continue to be processed by a data path in the storage system even though the command was cancelled. However, before the data is actually transferred out of the data path, a controller determines that the command was cancelled and prevents the data from being transferred out, while internally indicating that the transfer was complete. This provides a faster cancellation process than methods that attempt to stop the data from being processed by the data path.Type: GrantFiled: May 31, 2022Date of Patent: February 27, 2024Assignee: Western Digital Technologies, Inc.Inventors: Amir Segev, Shay Benisty
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Patent number: 11908029Abstract: A machine and process for managing restrictions of a wireless device associated with an inmate service account. The machine and process include a kiosk operable to exchange data with the wireless device, including limited-use restrictions related to: an inmate associated with the inmate service account, a correctional facility, and/or a parole requirement. The kiosk may also unlock the wireless device when the inmate is released from the correctional facility by removing the limited-use restrictions from the wireless device.Type: GrantFiled: July 12, 2021Date of Patent: February 20, 2024Assignee: TouchPay Holdings, LLCInventors: Charles Craig Bullard, David DuWayne Wise, Stephen Lee Hodge
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Patent number: 11893439Abstract: A transaction card is provided. The transaction card can include one or more layers having sensitive information related to a user's identity and account information. The transaction card can also include one or more privacy features to selectively obfuscate and reveal the sensitive information.Type: GrantFiled: May 9, 2022Date of Patent: February 6, 2024Assignee: Capital One Services, LLCInventors: Bryant Yee, Kevin Osborn, Tyler Maiman
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Patent number: 11887116Abstract: Authentication systems and methods using orientation sensor-enabled payment cards are disclosed herein where a server receives an authorization request from a web server or an electronic terminal. The server then transmits an instruction to the orientation sensor to determine whether the payment card has an orientation that is consistent with a predetermined orientation. When the payment card has an orientation consistent with the predetermined orientation, the server executes a first authentication protocol. However, if the payment card has an orientation that is not consistent with the predetermined orientation, the server executes a second authentication protocol that is more restrictive than the first authentication protocol.Type: GrantFiled: November 24, 2020Date of Patent: January 30, 2024Assignee: United Services Automobile Association (USAA)Inventors: Kelly Q. Baker, David M. Jones, Jr., Robert Andrew Massie, Bryan J. Osterkamp, Ryan Thomas Russell
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Patent number: 11856465Abstract: A method of an access network node of a carrier aggregation enabled cellular wireless communication system, and a method of a wireless terminal device of a carrier aggregation enabled cellular wireless communication system are disclosed. The method for the network node comprises identifying a need for an inter-band handover where a same physical frequency on which the access network node interacts with a wireless terminal device has more than one logical reference, wherein the wireless terminal device currently operates using a first logical reference, assigning a target frequency for the inter-band handover as a second logical reference for the physical frequency, and performing handover signalling with the wireless terminal device including the assigned target frequency.Type: GrantFiled: July 25, 2022Date of Patent: December 26, 2023Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)Inventors: Peter Alriksson, Maria Ulander
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Patent number: 11837058Abstract: A card with an embedded location tracker that can assist with locating a misplaced, lost, or stolen card is described. The location tracking device is embedded into the material forming the card. Other devices can form a crowdsourced network covering a wide geographic area that may be used to detect signals from the location tracking device of the card using a short-range wireless communication technology. When the card becomes misplaced, lost, or stolen, the card holder or the card issuer may use the embedded location tracking device to determine the current location of the card. In one embodiment, a tamper mechanism may also be provided to disable a chip of the card in response to an attempt to deactivate, destroy, or remove the embedded location tracking device from the card.Type: GrantFiled: December 20, 2022Date of Patent: December 5, 2023Assignee: United Services Automobile Association (USAA)Inventor: Nicole Williamson
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Patent number: 11789623Abstract: Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.Type: GrantFiled: May 12, 2021Date of Patent: October 17, 2023Assignee: Imagination Technologies LimitedInventor: Ian King
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Patent number: 11787194Abstract: Examples of a print liquid supply unit are described herein. In some examples, the print liquid supply unit includes an electrical interconnect. In some examples, the electrical interconnect is sealed in a supply joint from an outside of the supply unit to an inside of the supply unit. In some examples, the supply joint is welded to join housing components of the supply unit.Type: GrantFiled: July 18, 2019Date of Patent: October 17, 2023Assignee: Hewlett-Packard Development Company, L.P.Inventors: Anthony Donald Studer, David Olsen, Quinton Buford Weaver, Brian Allen Nichols
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Patent number: 11775187Abstract: According to one embodiment, a memory system includes first and second memory chips. The first memory chip has a first plane with a first block and a second block and a second plane with a third block and a fourth block. The second memory chip has a third plane with a fifth block and a sixth block and a fourth plane with a seventh block and an eighth block. The memory controller sets the first and third blocks as a first block unit in a user data storage area and the fifth and seventh blocks as a second block unit in the user data storage area. The memory controller allocates the second block, the fourth block, the sixth block, and the eighth block to a management data storage area. The memory controller manages user data operations for accessing the user data storage area in block units.Type: GrantFiled: September 2, 2021Date of Patent: October 3, 2023Assignee: Kioxia CorporationInventors: Shinji Yonezawa, Tomoyuki Kantani
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Patent number: 11757026Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: GrantFiled: October 16, 2020Date of Patent: September 12, 2023Assignee: Google LLCInventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
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Patent number: 11687447Abstract: A method and apparatus for performing access control of a memory device with aid of additional physical address information are provided. The method includes: during a garbage collection procedure, reading valid data from a source block and writing the valid data into a destination block; updating at least one logical-to-physical address mapping table; receiving a first read request from a host device, wherein the first read request indicates reading at a first logical address; in response to the first read request, reading the valid data of the destination block according to the second physical address associated with the first logical address; receiving a second read request from the host device, wherein the second read request indicates reading at the first logical address; and in response to the second read request, reading the valid data of the source block according to the first physical address associated with the first logical address.Type: GrantFiled: January 4, 2022Date of Patent: June 27, 2023Assignee: Silicon Motion, Inc.Inventor: Tsung-Chieh Yang
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Patent number: 11662916Abstract: Techniques for managing a storage system involve cleaning up a persistent storage disk in a backup mode to increase a writing rate of the persistent storage disk. The techniques further involve creating a library partition in the cleaned persistent storage disk. The techniques further involve writing cache data in a volatile storage device into the library partition. Accordingly, in a storage device with only a single persistent storage disk, cache data in a volatile storage device can be written into the persistent storage disk at a relatively high writing rate, thereby achieving efficient memory persistence.Type: GrantFiled: November 3, 2021Date of Patent: May 30, 2023Assignee: EMC IP Holding Company LLCInventors: Yechen Huang, Honggang Li, Zhonghua Zhu, Zhenhua Dong
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Patent number: 11662922Abstract: In some examples, a system allocates a plurality of partitions of a shared storage to respective data services. Based on respective utilizations of the plurality of partitions, the system selects, for a given data service of the data services, between a global storage apportionment process to rebalance shares of the shared storage among the data services, and a local storage apportionment process, where the rebalancing includes releasing a partition of the given data service, and the local storage apportionment process comprising freeing segments within the partition of the given data service.Type: GrantFiled: October 18, 2021Date of Patent: May 30, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Hy Dinh Vu, Murali Krishna Vishnumolakala, Yihong Xu, Ying Hu
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Patent number: 11645214Abstract: The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.Type: GrantFiled: June 26, 2020Date of Patent: May 9, 2023Assignee: Rambus Inc.Inventors: Frederick A. Ware, Holden Jessup
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Patent number: 11625466Abstract: A device includes memory and a processor. The device receives biometric information. The device receives location information. The device analyzes the received biometric information with stored biometric information. The device analyzes the received location information with stored location information. The device determines whether the received biometric information matches the stored biometric information. The device determines whether the received location information matches the stored location information. The device sends an electronic communication that indicates whether the received biometric information matches the stored biometric information and whether the received local information matches the stored location information.Type: GrantFiled: March 13, 2021Date of Patent: April 11, 2023Assignee: Visitlock LLCInventor: Kevin Robert Phillips
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Patent number: 11609973Abstract: To resolve a conflict between CMIS secondary types and certain ECM features such as content server categories, and allow the underlying ECM system to be fully CMIS-compliant, an ECM-independent ETL tool comprising a CMIS-compliant, repository-specific connector is provided. Operating on an integration services server at an integration tier between an application tier and a storage tier where the repository resides, the connector is particular configured to support CMIS secondary types and specific to the repository. On startup, the connector can import any category definition from the repository. The category definition contains properties associated with a category in the repository. When the category is attached to a document, the properties are viewable via a special category object type and a category identifier for the category. Any application can be adapted to leverage the ECM-independent ETL tool disclosed herein.Type: GrantFiled: January 12, 2021Date of Patent: March 21, 2023Assignee: Open Text SA ULCInventors: Alexander Lilko, Martin Brousseau
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Patent number: 11593021Abstract: Example implementations relate to metadata operations in a storage system. An example method includes receiving, from a first stream process, a first write request for a first container index in memory. The method further includes, in response to a receipt of the first write request, sending a first token to the first stream process without writing the first container index to a persistent storage. The method further includes receiving, from a second stream process, a first completion request for the first container index. The method further includes, in response to a receipt of the first completion request, writing the first container index from the memory to the persistent storage.Type: GrantFiled: November 6, 2020Date of Patent: February 28, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: David Malcolm Falkinder, Richard Phillip Mayo
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Patent number: 11579565Abstract: Disclosed is a cartridge attachable to an image forming apparatus body, the cartridge including: a memory member storing information relating to the cartridge; and a supporting body having a memory mounting portion on which the memory member is mounted, the memory member having a first surface, a second surface, and a lateral surface, the first surface is provided with a contact portion connected to a body electrode portion of the body of the image forming apparatus when the cartridge is installed in the body of the image forming apparatus, the memory mounting portion has a first opposing portion opposing the second surface and a second opposing portion opposing the lateral surface when the memory member is mounted, the memory member is mounted by adhesive between the second surface and the first opposing portion and between the lateral surface and the second opposing portion.Type: GrantFiled: August 23, 2021Date of Patent: February 14, 2023Assignee: CANON KABUSHIKI KAISHAInventors: Yu Fukasawa, Yukio Kubo, Yosuke Kashiide
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Patent number: 11557363Abstract: An integrated circuit includes a test counting circuit, a test information storage circuit, a sequence control circuit and a driving circuit. The test counting circuit generates a counting address signal. The test information storage circuit stores a test control value and outputs the test control value based on the counting address signal. The sequence control circuit changes an output sequence of the test control value based on a sequence control signal and outputs a final test control value based on the test control value or a target control value. The driving circuit performs a pre-set test operation based on the final test control value.Type: GrantFiled: January 15, 2021Date of Patent: January 17, 2023Assignee: SK hynix Inc.Inventor: Seung Hyun Chung
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Patent number: 11550938Abstract: Systems, apparatuses, and methods are described for zeroization of a computing device based on biometric information and vitality information. A computing device may store information associated with a user. The computing device may request biometric information and vitality information from one or more sensing devices. The computing device may determine, based on the requested biometric information and the requested vitality information, whether to zeroize the computing device.Type: GrantFiled: September 3, 2019Date of Patent: January 10, 2023Assignee: Science Applications International CorporationInventor: George Fortney
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Patent number: 11537640Abstract: A map output device is provided for preventing a storage medium from being sharedly used. The map output device comprises a connection unit; an output unit that outputs map data; and a control unit. The control unit is configured, when a storage medium is connected to the connection unit or when a movable body is used beyond a predetermined usage amount, to write a file containing information on a unique value related to the movable body into the storage medium connected to the connection unit, and to output, to the output unit, the map data read from the storage medium.Type: GrantFiled: February 25, 2021Date of Patent: December 27, 2022Assignee: MICWARE CO., LTD.Inventors: Kenta Imaida, Takuma Segawa, Eishin Hirokawa
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Patent number: 11487652Abstract: Devices and techniques are disclosed herein for providing L2P information to a host device from a storage system, the L2P information comprising changed L2P region and associated subregion information, to-be-loaded L2P region and associated subregion information, and invalid L2P region and associated subregion information.Type: GrantFiled: April 22, 2019Date of Patent: November 1, 2022Assignee: Micron Technology, Inc.Inventor: Giuseppe Cariello
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Patent number: 11481130Abstract: Techniques involve determining a target identifier of an operation command if a type of the operation command is determined to be a target type, the target type indicating that the operation command is a command for acquiring data. The techniques further involve executing the operation command to acquire a target data block if it is determined that the target identifier does not exist in a historical mapping relationship between stored data blocks and identifiers of historical operation commands for the stored data blocks. The techniques further involve storing the target data block and a target mapping relationship between the target data block and the target identifier in a storage space for storing the stored data blocks and the historical mapping relationship. Accordingly, different types of commands can be quickly distinguished, thereby reducing the time for processing commands of a target type, reducing the bandwidth consumed, and improving processing efficiency.Type: GrantFiled: September 22, 2020Date of Patent: October 25, 2022Assignee: EMC IP Holding Company LLCInventors: Zhibin Zhang, Yalan Kuang
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Patent number: 11461251Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.Type: GrantFiled: May 21, 2021Date of Patent: October 4, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyungmin Jin, Jindo Byun, Younghoon Son, Youngdon Choi, Junghwan Choi
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Patent number: 11439903Abstract: An in-game event occurring based on a user's input is detected in a game of each time, where the game is performed a plurality of times. A first parameter is increased or decreased based on the in-game event occurring in the game of each time, the first parameter being reset for the game of each time, to calculate a score in the game of each time. A second parameter is increased or decreased based on a result of the game determined based on an assessment parameter different from a final score, the second parameter being used in the game of the plurality of times without being reset for the game of each time.Type: GrantFiled: December 20, 2019Date of Patent: September 13, 2022Assignee: NINTENDO CO., LTD.Inventors: Yugo Hayashi, Miyuki Kimura, Shinya Fujiwara, Kyosuke Shimokawa, Hiroaki Tamura
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Patent number: 11422705Abstract: The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.Type: GrantFiled: March 25, 2021Date of Patent: August 23, 2022Assignee: Micron Technology, Inc.Inventors: Robert M. Walker, James A. Hall, Jr., Frank F. Ross
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Patent number: 11409452Abstract: The present invention provides a method performed by a secure digital (SD) card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode for initializing the SD card. The method includes: (a) after receiving a first supply voltage through a first voltage supply pin from a host coupled to the SD card, entering the SD mode if the SD card is not in the PCIe mode and a CMD0 command for entering the SD mode is received through a command pin from the host coupled to the SD card; and (b) after receiving the first supply voltage through the first voltage supply pin from the host coupled to the SD card, performing a PCIe linkup process if the SD card is not in the SD mode and a second supply voltage is received through a second voltage supply pin from the host coupled to the SD card. The SD card enters the PCIe mode if the PCIe linkup process succeeds.Type: GrantFiled: September 30, 2020Date of Patent: August 9, 2022Assignee: SILICON MOTION INC.Inventor: Chao-Kuei Hsieh
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Patent number: 11347420Abstract: Aspects of a multi-protocol storage device including a memory and a controller are provided which allow for endurance and other storage requirements of a host to be maintained for different logical regions of memory without disruption due to protocol switching. The memory includes blocks that are each associated with a storage attribute such as high endurance, performance, or protection. While operating in a first mode such as NVMe, the controller receives a mapping of storage attributes to different logical regions and stores the mapping in memory. The controller also associates blocks to logical addresses based on the mapping. When the controller switches to a second mode such as SD in response to a host command, the controller reads the mapping from memory and similarly associates blocks to logical addresses based on the mapping in the second mode. Storage attributes thus remain applicable across modes when mapping and storing data.Type: GrantFiled: June 8, 2020Date of Patent: May 31, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Ramanathan Muthiah, Dinesh Kumar Agarwal, Hitesh Golechchha
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Patent number: 11314907Abstract: In some examples, one or more computing devices on a network may receive, from a client computing device, one or more inputs for configuring a simulation, the simulation including at least a first simulator and a second simulator. The one or more computing devices may allocate computing resources including at least a first virtual machine for executing at least one of the first simulator or the second simulator. The one or more computing devices may configure a first simulation controller executable on the first virtual machine for controlling execution of the at least one of the first simulator or the second simulator. The first simulation controller may initiate execution of at least one of the first simulator or the second simulator as part of execution of the co-simulation. In some examples, a result of the co-simulation may be sent to the client computing device.Type: GrantFiled: August 26, 2016Date of Patent: April 26, 2022Assignee: HITACHI, LTD.Inventors: Sujit S Phatak, Herning Chen, Yuan Xiao, Can Wang
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Patent number: 11295037Abstract: Techniques for data scanning and removal for a removable storage device are described herein. An aspect includes a removable storage device comprising an embedded processor configured to boot from an embedded read-only memory (ROM) of the removable storage device. Another aspect includes scanning an internal storage of the removable storage device to identify a first file in the internal storage that matches removal criteria defined in the embedded ROM. Another aspect includes removing the identified first file from the internal storage of the removable storage device.Type: GrantFiled: May 28, 2019Date of Patent: April 5, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Michael Cracraft
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Patent number: 11275826Abstract: An apparatus capable of hosting a secure module. The hosting apparatus is configured to provide connectivity to the secure module, and comprises a memory for storing secure module related applications. A processing module is configured to check whether an application chosen or activated by the user of the apparatus is a secure module related application. In case the chosen or activated application is a secure module related application, the processing module is 101 configured to restrict user rights concerning the application.Type: GrantFiled: January 31, 2007Date of Patent: March 15, 2022Assignee: Nokia Technologies OyInventor: Mikko Antero Saarisalo
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Patent number: 11237976Abstract: Embodiments of the disclosure relate to a memory system, a memory controller and a meta-information storage device. By providing a memory device configured to store mapping information between a logical address and a physical address, a memory controller configured to control the memory device and control a memory area in which mapping segments including some of the mapping information are stored and a meta-information storage device configured to store meta-information on the memory area, it is possible to provide a memory system, a memory controller and a meta-information storage device capable of processing a command received from a host as quickly as possible even when an SPO occurs.Type: GrantFiled: November 4, 2019Date of Patent: February 1, 2022Assignee: SK hynix Inc.Inventors: Hye-Mi Kang, Eu-Joon Byun
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Patent number: 11223739Abstract: A printing system includes a printer and an information processing device that includes a processor and a memory storing processor-executable instructions, the instructions being configured to, when executed by the processor, cause the processor to accept a print instruction, in response to accepting the print instruction, determine whether to instruct the printer to start a pre-printing operation based on preparation instruction information, in response to determining to instruct the printer to start the pre-printing operation, transmit the preparation instruction information to the printer, in response to determining to instruct the printer to start the pre-printing operation and transmitting the preparation instruction information to the printer, generate print data based on specified contents data, and transmit print instruction information to the printer.Type: GrantFiled: September 14, 2020Date of Patent: January 11, 2022Assignee: BROTHER KOGYO KABUSHIKI KAISHAInventor: Kazutaka Yamada
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Patent number: 11216209Abstract: A storage device comprises a storage medium, storage controller, a host interface, and a bridge slot. The storage controller is configured to control read and write operations to the storage medium and operates according to a firmware written by a storage device manufacturer. The bridge slot is configured to receive a removable bridge storing software written by a third-party different from the storage device manufacturer. The removable bridge is configured to intercept a first command sent from the host system to the storage controller, modify the first command according to the software stored on removable bridge, and transmit the first command to the storage controller.Type: GrantFiled: March 26, 2019Date of Patent: January 4, 2022Assignee: Western Digital Technologies, Inc.Inventor: William Bernard Boyle
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Patent number: 11209992Abstract: Detection of alteration of storage keys used to protect memory includes determining whether a storage key alteration event has occurred within a processor of a computing environment. The determining includes checking whether one or more selected fields of a storage key have been updated. The storage key is associated with a block of memory and controls access to the block of memory. Based on the checking indicating that the one or more selected fields of the storage key have been updated, a storage key alteration event has been detected. Based on determining the storage key alteration event has occurred, a notification is provided.Type: GrantFiled: September 25, 2020Date of Patent: December 28, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Slegel, Jonathan D. Bradbury, Bruce C. Giamei, James H. Mulder, Peter J. Relson
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Patent number: 11151135Abstract: A pre-computed result module computes a result prior to receiving a query. The pre-computed result module includes instructions executed by a processor to assess a pre-computation query to designate each identified database source that contributes to the answer to the pre-computation query and corresponding database source metadata. A metadata signature is computed for each identified database source to create a store of identified database sources and corresponding metadata signatures. The query is evaluated to identify accessed database sources responsive to the query. A current metadata signature for each accessed database source is compared to the metadata signatures to identify each updated database source. Re-computed results are formed for each updated database source. Pre-computed results are utilized for each database source that is not updated. A response is supplied to the query using the re-computed results and the pre-computed results.Type: GrantFiled: August 5, 2016Date of Patent: October 19, 2021Assignee: Cloudera, Inc.Inventor: Douglas J. Cameron
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Patent number: 11106829Abstract: A chip fingerprint management device includes: a one-time programmable (OTP) memory including a first storage region, the first storage region being readable by hardware and access restricted by software; and an OTP controller which generates a chip fingerprint based on a random number, and programs the generated chip fingerprint into the first storage region in the OTP memory.Type: GrantFiled: December 7, 2018Date of Patent: August 31, 2021Assignee: INNOGRIT TECHNOLOGIES CO., LTD.Inventor: Moyang Chen
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Patent number: 11074012Abstract: A storage device includes: a semiconductor memory; and a memory controller coupled to the semiconductor memory and configured to control the semiconductor memory, wherein the memory controller is configured to store information for translating a logical address into a physical address, and execute a dividing process that includes dividing, upon receiving a computational command, the computational command into a plurality of commands based on the information.Type: GrantFiled: March 29, 2019Date of Patent: July 27, 2021Assignee: FUJITSU LIMITEDInventor: Shinya Kuwamura
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Using a distributed prime data sieve for efficient lossless reduction, search, and retrieval of data
Patent number: 11068444Abstract: Systems and techniques for losslessly reducing input data using a distributed system comprising multiple computers that maintain portions of a data structure that organizes prime data elements based on names of the prime data elements. During operation, a first computer can determine a first name for the element, and send the element to a second computer based on the first name. The second computer can losslessly reduce the element by determining a second name for the element, and using the second name to navigate through a portion of the data structure maintained at the second computer.Type: GrantFiled: September 17, 2018Date of Patent: July 20, 2021Assignee: Ascava, Inc.Inventor: Harshvardhan Sharangpani -
Patent number: 11038307Abstract: In one embodiment, as apparatus includes a cable identifier for attachment to a plug and cable assembly operable to deliver Power over Ethernet (PoE) at a power greater than 90 watts, the plug and cable assembly receivable in a receptacle delivering the PoE. The cable identifier is configured for mating with the receptacle and includes an electrical identifier for use in identifying a power rating of the cable when the plug and cable assembly is inserted into the receptacle. A method and network device are also disclosed herein.Type: GrantFiled: September 4, 2018Date of Patent: June 15, 2021Assignee: CISCO TECHNOLOGY, INC.Inventors: Paolo Sironi, Simone Vigna, Joel Richard Goergen, Chad M. Jones