Based On Data Size Patents (Class 711/171)
  • Patent number: 10375111
    Abstract: Anonymous containers are discussed herein. An operating system running on a computing device, also referred to herein as a host operating system running on a host device, prevents an application from accessing personal information (e.g., user information or corporate information) by activating an anonymous container that is isolated from the host operating system. In order to create and activate the anonymous container, a container manager anonymizes the configuration and settings data of the host operating system, and injects the anonymous configuration and settings data into the anonymous container. Such anonymous configuration and settings data may include, by way of example and not limitation, application data, machine configuration data, and user settings data. The host operating system then allows the application to run in the anonymous container.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: August 6, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Benjamin M. Schultz, Frederick Justus Smith, Daniel Vasquez Lopez, Abhinav Mishra, Ian James McCarty, John A. Starks, Joshua David Ebersol, Ankit Srivastava, Hari R. Pulapaka, Mehmet Iyigun, Stephen E. Bensley, Giridhar Viswanathan
  • Patent number: 10365999
    Abstract: A method and an apparatus for performing memory space reservation and management are provided, wherein the method is applied to a server system. The method includes: providing a mount point at a file system of a server in the server system, and creating a file at the mount point to occupy partial memory space of a physical memory; mapping the file to a section of virtual memory addresses to prevent any swap operation from being applied to the partial memory space; and updating file information of the file into a memory space management list to dynamically manage the partial memory space.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 30, 2019
    Assignee: SYNOLOGY INCORPORATED
    Inventors: Chuan-Yu Tsai, Yi-Chun Lin
  • Patent number: 10346073
    Abstract: A storage control apparatus includes a memory and a processor. The memory stores selection condition information relating to a selection condition for storage devices to construct a RAID, group information relating to groups to which the storage devices belong, and connection information indicating a connection configuration of the storage devices. The processor is configured to perform a procedure including: selecting the storage devices that match the selection condition information; extracting groups to which the selected storage devices belong based on the group information; assigning group priorities, which indicate selection priorities in units of the groups of the storage devices, to the extracted groups based on the connection information; and selecting one storage device from each of the extracted groups in accordance with the group priorities until a predetermined number of storage devices have been selected.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 9, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Atsuhiro Otaka, Akiko Sakaguchi, Hidetoshi Satou, Takahiro Yumoto, Akira Yamazaki
  • Patent number: 10331375
    Abstract: A block-level data storage system receives a request to delete a data storage volume. As a result, the data storage volume is deleted and the areas comprising the volume are released and reaped. The areas may contain non-zero data within a plurality of data storage chunks that comprise the areas. An area cleaner is configured to zero out the areas for allocation to a newly created data storage volume.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: June 25, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Nandakumar Gopalakrishnan, Kerry Quintin Lee, Danny Wei
  • Patent number: 10318198
    Abstract: Provides a bin-type heap where bin sizes can be easily customized to the exact requirements of a specific system by means of a bin size array, thus resulting in greater efficiency and better performance. Also provides enhanced debugging support and self-healing. Intended primarily for embedded and similar systems, which require high performance, deterministic operation, efficient memory utilization, high reliability, and which are characterized by limited block size requirements and ample available idle time.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: June 11, 2019
    Inventor: Ralph Crittenden Moore
  • Patent number: 10303375
    Abstract: Methods and apparatus for buffer allocation and memory management are described. A plurality of buffers of a memory may be allocated, by a memory controller, with the buffers having variable sizes. The memory controller may maintain a mapping table that associates each of a plurality of access keys to a respective one of a plurality of page addresses of a plurality of pages of the memory. Each of the buffers may respectively include one or more contiguous pages of the plurality of pages of the memory. Each page of the plurality of pages may include one or more blocks of the memory.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 28, 2019
    Assignee: Fungible, Inc.
    Inventors: Deepak Goel, Pradeep Sindhu, Bertrand Serlet, Wael Noureddine, Paul Kim
  • Patent number: 10282287
    Abstract: Memory devices and systems having direct access mode (DAM) space allocation across interleaved non-volatile memory (NVM) modules, as well as methods of allocating direct access mode (DAM) space across interleaved non-volatile memory (NVM) modules are disclosed and described.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Wojciech Malikowski, Maciej Maciejewski
  • Patent number: 10284650
    Abstract: A computer-implemented method for supervising data stream storage including communicating with a probe that captures network data and outputs a plurality of data streams to a plurality of data repository units, receiving registration data associated with respective data streams that identifies the associated probes, selecting at least one of the data repository units to store the first data stream in real time based on a storage capacity of the data repository units to receive and store data, determining that storage capacity is not sufficient for the data stream in response to a change in the storage capacity of the data repository units to receive and store data, determining a corrective action in response to the determination that the storage capacity is not sufficient, and notifying the probe identified in association with the first data stream about the corrective action.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: May 7, 2019
    Assignee: NetScout Systems Texas, LLC
    Inventors: Eric C. McNair, Ryan L. Pipkin, Adrian C. Soncodi
  • Patent number: 10282111
    Abstract: A device that provides for adaptive wear levelling includes at least one processor. The at least one processor utilizes sets of blocks of flash memory circuits for data storage operations, each set of blocks including a block from each flash memory circuit and at least some of the blocks being marked active for the data storage operations. The at least one processor monitors a quality metric of each block while the blocks marked active are utilized for data storage operations. The at least one processor determines when the quality metric of a block falls below a minimum level and marks the block as temporarily inactive, where the block is not utilized for the data storage operations while marked temporarily inactive. The at least one processor, when a criterion is satisfied, marks the block as active so that the block can again be utilized for the data storage operations.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: May 7, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Richard David Barndt, Aldo G. Cometti, Scott Thomas Kayser
  • Patent number: 10261896
    Abstract: Disclosed herein are system, method, and computer program product embodiments for adaptively self-tuning a bucket memory manager. An embodiment operates by receiving requests for memory blocks of varying memory sizes from a client. Determining a workload for the client based on the requests. Analyzing buckets in the bucket memory manager based on the workload. Adjusting parameters associated with the bucket memory manager based on the analyzing to accommodate the requests.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: April 16, 2019
    Assignee: SAP SE
    Inventor: Tony Imbierski
  • Patent number: 10241550
    Abstract: A method for zeroing memory in computing systems where access to memory is non-uniform includes receiving, via a system call, a request for a pool of memory, determining a size of the requested pool of memory, and creating a dummy memory segment. The size of the dummy memory segment is larger than the size of the requested pool of memory. The dummy memory segment is filled with one or more pages, based on the determined size of the requested pool of memory, and the dummy memory segment is deleted.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Nikhil Hegde, Bruce Mealey, Mark D. Rogers
  • Patent number: 10235292
    Abstract: A method and a system for implementing a lock-free shared memory accessible by a plurality of readers and a single writer are provided herein. The method including: maintaining a memory accessible by the readers and the writer, wherein the memory is a hash table having at least one linked list of buckets, each bucket in the linked list having: a bucket ID, a pointer to an object, and a pointer to another bucket; calculating a pointer to one bucket of the linked list of buckets based on a hash function in response to a read request by any of the readers; and traversing the linked list of buckets, to read a series of objects corresponding with the traversed buckets, while checking that the writer has not: added, amended, or deleted objects pointed to by any of said traversed buckets, wherein said checking is carried out in a single atomic action.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: March 19, 2019
    Assignee: Dell Products L.P.
    Inventors: Michael Hakimi, Max Shifrin
  • Patent number: 10235079
    Abstract: A storage system includes a host including a processor and a storage device including a controller and a flash memory unit. The host is configured to read physically fragmented data of a file stored in one or more physical storage regions of the flash memory unit and write the data continuously into other one or more physical regions of the flash memory unit, such that the data are physically defragmented.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: March 19, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Daisuke Hashimoto
  • Patent number: 10228737
    Abstract: A method for zeroing memory in computing systems where access to memory is non-uniform includes receiving, via a system call, a request for a pool of memory, determining a size of the requested pool of memory, and creating a dummy memory segment. The size of the dummy memory segment is larger than the size of the requested pool of memory. The dummy memory segment is filled with one or more pages, based on the determined size of the requested pool of memory, and the dummy memory segment is deleted.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Nikhil Hedge, Bruce Mealey, Mark D. Rogers
  • Patent number: 10229046
    Abstract: Separating data of trusted and untrusted data types in a memory of a computer during execution of a software program. Assigning mutually separated memory regions in the memory, namely, for each of the data types, a memory region for storing any data of the respective data type, and an additional memory region for storing any data which cannot be uniquely assigned to one of the data types. For each allocation instruction, performing a memory allocation including linking the allocation instruction to at least one data source, generating instruction-specific context information, evaluating the data source to determine the data type, associating the data type with the context information, based on the context information, assigning the allocation instruction to the memory region assigned to the evaluated data type, and allocating memory for storing data from the data source in the assigned memory region.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anil Kurmus, Matthias Neugschwandtner, Alessandro Sorniotti
  • Patent number: 10223275
    Abstract: Zones of a magnetic recording medium are allocated as a respective plurality of distributed media caches arranged in in a predetermined order. For each of a plurality of caching events, cache data is written to one or more of the distributed media caches. A next of the media caches in the predetermined order is selected for the next caching event if the selected caches are not a last in the predetermined order. Otherwise a first media cache is selected in the predetermined order.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: March 5, 2019
    Assignee: Seagate Technology LLC
    Inventors: Jason M. Feist, Mark Allen Gaertner, Dipeshkumar J. Purani, Anil Kashyap, Wei Zhao
  • Patent number: 10223025
    Abstract: An apparatus in one embodiment comprises a reconfigurable multi-tier storage system having at least a front-end storage tier and a back-end storage tier. The multi-tier storage system is implemented at least in part utilizing a plurality of replicated storage units. One or more of the replicated storage units are each utilized in a first configuration of the reconfigurable multi-tier storage system to implement a portion of at least one of a burst buffer appliance and a software-defined storage pool of the front-end storage tier. At least one of the one or more replicated storage units is utilized in a second configuration of the reconfigurable multi-tier storage system to implement a portion of at least one of a scale-out network-attached storage cluster and an object store of the back-end storage tier. A given one of the replicated storage units may be reconfigured by rebooting it using different software modules.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: March 5, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Sorin Faibish, Percy Tzelnic, Dennis Ting, James M. Pedone, Jr.
  • Patent number: 10209900
    Abstract: Methods and apparatus for buffer allocation and memory management are described. A plurality of buffers of a memory may be allocated, by a memory controller, with the buffers having variable sizes. The memory controller may maintain a mapping table that associates each of a plurality of access keys to a respective one of a plurality of page addresses of a plurality of pages of the memory. Each of the buffers may respectively include one or more contiguous pages of the plurality of pages of the memory. Each page of the plurality of pages may include one or more blocks of the memory. The mapping table may include one or more entries organized in a tree structure.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: February 19, 2019
    Assignee: Fungible, Inc.
    Inventors: Deepak Goel, Wael Noureddine, Paul Kim
  • Patent number: 10191854
    Abstract: A system for providing both low-level, physical data access and high-level, logical data access to a single process is disclosed, having a data block table with a physical memory address portion and a logical memory address portion. Data blocks that are mapped to physical memory bypass multiple logical memory address layers, such as the operating system layer and a logical block address layer, while data blocks that are mapped to the logical memory will be routed through traditional API layers, providing both increased performance and flexibility.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: January 29, 2019
    Assignee: Levyx, Inc.
    Inventor: Ali Tootoonchian
  • Patent number: 10168907
    Abstract: a memory system may include: a memory device including a plurality of memory dies each having a plurality of memory blocks; and a controller suitable for performing one or more of data defragmentation and data remapping operations for a target transaction group in the memory device in response to a request message provided from a host, transmitting a completion message to the host as a response to the request message, and receiving an access to the transaction group, from the host.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: January 1, 2019
    Assignee: SK Hynix Inc.
    Inventors: Gi-Seob Chang, Soong-Sun Shin
  • Patent number: 10157142
    Abstract: In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: December 18, 2018
    Assignee: INTEL CORPORATION
    Inventors: Ashok Raj, Sivakumar Radhakrishnan, Dan J. Williams, Vishal Verma, Narayan Ranganathan, Chet R. Douglas
  • Patent number: 10152233
    Abstract: A file management method, a distributed storage system, and a management node are disclosed. In the distributed storage system, after receiving a file creation request sent by a host for requesting to create a file in a distributed storage system, a management node allocates, to the file, first virtual space from global virtual address space of the distributed storage system, where local virtual address space of each storage node in the distributed storage system is corresponding to a part of the global virtual address space. Then, the management node records metadata of the file, where the metadata of the file includes information about the first virtual space, and the information about the first virtual space is used to point to local virtual address space of a storage node that is used to store the file. Further, the management node sends, the information about the first virtual space to the host.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: December 11, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jun Xu, Junfeng Zhao, Yuangang Wang
  • Patent number: 10133509
    Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include identifying a set of storage services on multiple storage systems. A plurality of storage services are defined, each of the storage services comprising a subset of the storage resources, and a defined storage (SDS) system is configured comprising the defined storage services. Multiple sub consistency groups are configured, each of the sub consistency group comprising one or more logical volumes stored in a subset of the defined storage services on a given storage system, and a consistency group is configured comprising the multiple sub consistency groups. Upon detecting a snapshot condition, processing input/output operations to all the volumes in the sub consistency groups can be simultaneously suspended, a snapshot for each of the sub consistency groups is generated, and the processing of the input/output operations is resumed upon generating the respective snapshots.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ohad Atia, Amalia Avraham, Ran Harel
  • Patent number: 10095550
    Abstract: A multiprocessor computer system facility is provided for selectively reallocating a logical processing unit within the computer system. The logical processing unit is one logical processing unit of multiple logical processing units backed by a socket of a plurality of sockets of the multiprocessor computer system. The selectively reallocating includes: monitoring, during execution of program code of the multiple logical processing units, a performance metric of a hardware resource of the socket, the hardware resource being shared by the multiple logical processing units; and reassigning the logical processing unit, based on the monitoring, to a different socket of the plurality of sockets of the multiprocessor computer system to, in part, improve the performance metric of the hardware resource of the socket.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: October 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oliver Benke, Hartmut E. Penner, Klaus Theurich
  • Patent number: 10073630
    Abstract: A storage module may be configured to perform log storage operations on a storage log maintained on a non-volatile storage medium. An I/O client may utilize storage services of the storage module to maintain an upper-level log. The storage module may be configured to coordinate log storage and/or management operations between the storage log and the upper-level log. The coordination may include adapting a segment size of the logs to reduce write amplification. The coordination may further include coordinating validity information between log layers, adapting log grooming operations to reduce storage recovery overhead, defragmenting upper-level log data within the storage address space, preventing fragmentation of upper-level log data, and so on. The storage module may coordinate log operations by use of log coordination messages communicated between log layers.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: September 11, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Jingpei Yang, Nisha Talagala, Swaminathan Sundararaman, Ned Plasson, Gregory N. Gillis
  • Patent number: 10055299
    Abstract: In an approach to backup and restore one or more clone file trees, one or more processors generate a clone management table. One or more processors record a clone management information in the clone management table about each clone file. To backup a clone file, one or more processors update the clone management information, and store one or more data blocks that are in the clone file trees. To restore a clone file, one or more processors analyze a clone management information and restore one or more data blocks in the clone file. To restore a clone file parent, one or more processors analyze a clone management information and restore one or more data blocks in the clone file parent. To restore a clone file tree, one or more processors analyze a clone management information and restore one or more data blocks in the clone file tree.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Stefan Bender, Nils Haustein, Dominic Mueller-Wicke, Wayne A. Sawdon, James P. Smith
  • Patent number: 10049121
    Abstract: In an approach to backup and restore one or more clone file trees, one or more processors generate a clone management table. One or more processors record a clone management information in the clone management table about each clone file. To backup a clone file, one or more processors update the clone management information, and store one or more data blocks that are in the clone file trees. To restore a clone file, one or more processors analyze a clone management information and restore one or more data blocks in the clone file. To restore a clone file parent, one or more processors analyze a clone management information and restore one or more data blocks in the clone file parent. To restore a clone file tree, one or more processors analyze a clone management information and restore one or more data blocks in the clone file tree.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Stefan Bender, Nils Haustein, Dominic Mueller-Wicke, Wayne A. Sawdon, James P. Smith
  • Patent number: 10025519
    Abstract: In one aspect, a method includes performing a reconfiguration process to reconfigure storage usage. The reconfiguration process includes selecting a subset of solutions from a user-shaped solution space, determining a cost value of each solution in the subset using a cost function, executing a cost-based reconfiguration generation based on a customized genetic process where each reconfiguration solution is treated as a genome, selecting genomes using the cost function as a next generation and repeating the executing.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 17, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Jieming Di, Yu Cao, Hui Liu, Lihong Li, Devanjan Sarkar
  • Patent number: 9996466
    Abstract: Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems, methods, and computer readable media to support operations performed with data that is compressed prior to being written as a cache line in a cache memory. In some embodiments, a cache controller determines the size of compressed data to be stored as a cache line. The cache controller identifies a logical block address (LBA) range to cache the compressed data, where such identifying is based on the size of the compressed data and on reference information describing multiple LBA ranges of the cache memory. One or more such LBA ranges are of different respective sizes. In other embodiments, LBA ranges of the cache memory concurrently store respective compressed cache lines, wherein the LBA ranges and are of different respective sizes.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Rowel S. Garcia
  • Patent number: 9946660
    Abstract: Examples include a device for memory space management. Some examples include receiving, from a host, a space management request that identifies a virtual page address. The virtual page address may be associated with a compressed page that includes a compression metadata having a reference count that indicates a number of virtual pages of data in the compressed page. The virtual page table entry associated with the virtual page address in a virtual page table may be looked up. The virtual page table entry may identify the compressed page. In such examples, the virtual page table entry may be marked as invalid without updating the reference count in the compressed page. A determination may be made as to whether each virtual page table entry that identifies the compressed page is marked invalid. Based on the determination that each virtual page table entry that identifies the compressed page is invalid, a free space bitmap entry for the compressed page may be updated to indicate that the compressed page is free.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: April 17, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Shankar Iyer, Siamak Nazari, Srinivasa D Murthy, Jin Wang
  • Patent number: 9922439
    Abstract: A method for of playing an animation image, the method including: obtaining a plurality of images; displaying a first image of the plurality of images; detecting a first event as a trigger to play the animation image for a first object of the first image; and playing the animation image for the first object using the plurality of images.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: March 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pavan Sudheendra, Sarvesh, Yogesh Manav, Adappa M Gourannavar, Rahul Varna, Sumanta Baruah
  • Patent number: 9924339
    Abstract: A device may receive first information. The first information may be based on traffic associated with usage of a toll-free data service. The device may receive an identifier for a user device. The user device may be using the toll-free data service. The device may generate second information. The second information may correspond to usage, by the user device, of the toll-free data service. The second information may be generated based on the first information and the identifier. The device may send the second information to another device to support providing a notification of toll-free data service usage. The notification of toll-free data service usage may be based on the second information.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: March 20, 2018
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Fnu Bongu Huma Shankar Rao, Jian Huang, Susan Kelly, Gong Zhang, Sayan Dey, Mohammad Zohaib Akmal, Guanrao Chen
  • Patent number: 9870174
    Abstract: An apparatus includes a memory storing a group of pages of data. An interface of the apparatus is configured to send, to a data storage device (DSD) from a first command queue, a first instruction of instructions to store the group of pages to the DSD using a logical address corresponding to the group of pages. The interface is further configured to send, to the DSD from a second command queue, a second instruction of the instructions to write the group of pages to the DSD using the logical address. Sending a first copy of the group of pages in association with the first instruction and sending a second copy of the group of pages in association with the second instruction enables a multi-stage programming operation to be performed at the DSD without storing the group of pages at the DSD between stages of the multi-stage programming operation.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: January 16, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Amir Shaharabany, Hadas Oshinsky
  • Patent number: 9870400
    Abstract: Analyzing a managed runtime cache is provided. A heap associated with a managed runtime environment, where the heap includes an N-generation cache or a plurality of objects associated with a program operating within a managed runtime environment is identified. A snapshot of the heap is produced, wherein the snapshot identifies a memory location for each object of the plurality of objects at which the object is stored. A generation of each of the plurality of objects based, at least in part, on the memory location of the object is determined. One or more suggestions based, at least in part, on the memory location of the plurality of objects is provided.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Richard N. Chamberlain, Howard J. Hellyer, Matthew F. Peters, Adam J. Pilkington
  • Patent number: 9785562
    Abstract: Embodiments of the present invention provide methods, computer systems, and computer program products for adjusting allocation of a storage device. In one embodiment, a first part of the storage device is allocated to tiering storage, and a second part of the storage device is allocated to cache storage. Operating statuses of the first part and second part are collected. A performance measure of the first part is obtained based on the operating status of the first part, and a performance measure of the second part is obtained based on the operating status of the second part. Allocation of a capacity of the storage devices is adjusted between the first part and the second part based on the performance measures of the first part and the second part.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Yang Liu, Yi Yang, Jun Wei Zhang, Xin Zhang
  • Patent number: 9773570
    Abstract: Aspects of the invention provide for reducing BIST test time for a memory of an IC chip. In one embodiment, a BIST architecture for reducing BIST test time of a memory for an integrated circuit (IC) chip, the architecture comprising: a pair of latches for receiving bursts of data from a memory; a first compression stage for receiving a burst of data and compressing the burst of data into a plurality of latches; a second compression stage for comparing the compressed bursts of data with expected data; and a logic gate for determining whether there is a fail in the burst of data.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: September 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kevin W. Gorman, Deepak I. Hanagandi, Krishnendu Mondal, Michael R. Ouellette
  • Patent number: 9767018
    Abstract: An illustrative embodiment of a computer-implemented method for estimating heap fragmentation in real time, models a runtime view of free heap memory, models a runtime view of heap allocation patterns for the heap memory and takes a snapshot of the heap memory. A batch allocator simulator is executed at a predetermined event and a remaining amount of memory unused in the simulation is identified as fragmented memory.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: September 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles R. Gracie, Aleksandar Micic
  • Patent number: 9760858
    Abstract: A method that includes a first record that relates to a first subject entity is received and a second record that relates to a second subject entity is received, where it is unknown whether the first subject entity is the same as the second subject entity. A comparison of a first external/non-key attribute value for the first subject entity to a second external/non-key attribute value for the second subject entity is performed. A probability value is calculated, at least in part, on a first external/non-key attribute value for the first subject entity to a second external/non-key attribute value for the second subject entity.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Leonardo F. Demo, Mariana R. Franco, Denilson Nastacio, Fabio Negrello, Cassandro J. D. P. Pereira, Maristela Salvatore, Paulo H. O. Sousa Leal
  • Patent number: 9734204
    Abstract: Analyzing a managed runtime cache is provided. A heap associated with a managed runtime environment, where the heap includes an N-generation cache or a plurality of objects associated with a program operating within a managed runtime environment is identified. A snapshot of the heap is produced, wherein the snapshot identifies a memory location for each object of the plurality of objects at which the object is stored. A generation of each of the plurality of objects based, at least in part, on the memory location of the object is determined. One or more suggestions based, at least in part, on the memory location of the plurality of objects is provided.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Richard N. Chamberlain, Howard J. Hellyer, Matthew F. Peters, Adam J. Pilkington
  • Patent number: 9720613
    Abstract: A system and method for allocating storage devices within a multi-node data storage system. The system maintains a data structure including a generation number indicating an incarnation of the data structure, a highest cylinder ID index value observed to be in use within the data storage system, and a safe index value indicating a lowest cylinder ID index value for use when allocating a new cylinder index. Following receipt of an allocation request, the system assigns a cylinder ID index to the allocation request, the cylinder ID index being greater than the safe index value. The assigned cylinder ID index is compared to the highest cylinder ID index value observed to be in use within said data storage system, and when the cylinder ID index is greater than the highest cylinder ID index value, increments the generation number and highest cylinder ID index value maintained within the data structure.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 1, 2017
    Assignee: Teradata US, Inc.
    Inventor: Gary Lee Boggs
  • Patent number: 9601199
    Abstract: Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain. Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: David R. Cheriton, Amin Firoozshahian, Alexandre Y. Solomatnikov
  • Patent number: 9582431
    Abstract: Storage address space to NVM address, span, and length mapping/converting is performed by a controller for a solid-state storage system that includes a mapping function to convert a logical block address from a host to an address of a smallest read unit of the NVM. The mapping function provides span and length information corresponding to the logical block address. The span information specifies a number of contiguous smallest read units to read to provide data (corresponding to the logical block address) to the host. The length information specifies how much of the contiguous smallest read units relate to the data provided to the host. The converted address and the length information are usable to improve recycling of no longer needed (e.g. released) portions of the NVM, and usable to facilitate recovery from outages and/or unintended interruptions of service.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: February 28, 2017
    Assignee: Seagate Technology LLC
    Inventor: Earl T Cohen
  • Patent number: 9542112
    Abstract: Techniques for enabling secure cross-process memory sharing are provided. In one set of embodiments, a first user process executing on a computer system can create a memory handle representing a memory space of the first user process. The first user process can further define one or more access restrictions with respect to the memory handle. The first user process can then transmit the memory handle to a second user process executing on the computer system, the memory handle enabling the second user process to access at least a portion of the first process' memory space, subject to the one or more access restrictions.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: January 10, 2017
    Assignee: VMware, Inc.
    Inventors: Adrian Drzewiecki, Christoph Klee, Mounesh Badiger
  • Patent number: 9542227
    Abstract: One embodiment of the present invention sets forth a technique for dynamically allocating memory using one or more lock-free FIFOs. One or more lock-free FIFOs are populated with FIFO nodes, where each FIFO node represents a memory allocation of a predetermined size. Each particular lock-free FIFO includes memory allocations of a single size. Different lock-free FIFOs may include memory allocations for different sizes to service allocation requests for different size memory allocations. A lock-free mechanism is used to pop FIFO nodes from the FIFO. The use of the lock-free FIFO allows multiple consumers to simultaneously attempt to pop the head FIFO node without first obtaining a lock to ensure exclusive access of the FIFO.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: January 10, 2017
    Assignee: NVIDIA Corporation
    Inventors: Stephen Jones, Xiaohuang Huang
  • Patent number: 9535937
    Abstract: A method for implementing a geometric array in a computing environment is disclosed. In one embodiment, such a method includes providing an array of slots, where each slot is configured to store a pointer. Each pointer in the array points to a block of elements. Each pointer with the exception of the first pointer in the array points to a block of elements that is twice as large as the block of elements associated with the preceding pointer. Such a structure allows the geometric array to grow by simply adding a pointer to the array that points to a new block of elements that is twice as large as the block of elements associated with the preceding pointer in the array. A corresponding computer program product, as well as a method for accessing data in the geometric array, are also disclosed.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventor: Michael Stephen Fulton
  • Patent number: 9513809
    Abstract: A main data storage system has a main computer-implemented storage control and data storage, and a user interface, the main storage control in communication with a local computer-implemented storage control of a local data storage system with local data storage. In response to a request to increase data storage from the user interface, the main storage control determines whether the main data storage is out of space. If so, the main storage control sends a command to the local storage control to create data space in local data storage. The local storage control creates the data space and associates the data space with the main storage control; and, in response to the local storage control creating data space in the local data storage and notifying the main storage control, the main storage control updates its metadata with respect to the data space.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: December 6, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juan A. Coronado, Sara M. Coronado, Jennifer S. Shioya, Edgar Xavier Somoza
  • Patent number: 9495652
    Abstract: Discrete Business Activity Management is a method whereby continuous streams of data formatted in one or more taxonomies, originating from two or more networked entity domain nodes within a Grid Framework or equivalent, are extracted at two or more independent times and synchronized to an assigned time index, then translated into each other's taxonomy or harmonized, securely filtered and, routed thereby creating a universal or federated view of business activity over time, which may be viewed in the context of any single domain. An apparatus which performs DBAM consists of processing, storage and network hardware and software, along with software which integrates the function of the DBAM within a Grid Framework or equivalent. The apparatus is further configured as a service for sale to subscribers through the addition of administrative software architecture to manage subscriber access, proprietary information, data element integrity and quality of service in connection with distributed applications.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: November 15, 2016
    Inventor: Daniel M. Cook
  • Patent number: 9489405
    Abstract: A method for implementing a geometric array in a computing environment is disclosed. In one embodiment, such a method includes providing an array of slots, where each slot is configured to store a pointer. Each pointer in the array points to a block of elements. Each pointer with the exception of the first pointer in the array points to a block of elements that is twice as large as the block of elements associated with the preceding pointer. Such a structure allows the geometric array to grow by simply adding a pointer to the array that points to a new block of elements that is twice as large as the block of elements associated with the preceding pointer in the array. A corresponding computer program product, as well as a method for accessing data in the geometric array, are also disclosed.
    Type: Grant
    Filed: June 25, 2011
    Date of Patent: November 8, 2016
    Assignee: International Business Machines Corporation
    Inventor: Michael S. Fulton
  • Patent number: 9448929
    Abstract: A computer-implemented method for compilation of applications can include receiving a set of software instructions and traversing the set of software instructions based on a control-flow order of the set of software instructions. The traversing can include identifying a first allocation instruction in the set of software instructions, the first allocation instruction being configured to allocate a first amount of memory for a first object and identifying a second allocation instruction in the set of software instructions, the second allocation instruction being configured to allocate a second amount of memory for a second object. The method can include determining that the first allocation instruction dominates the second allocation instruction and, in response to the determining, combining the first allocation instruction and the second allocation instruction into a folded allocation instruction that allocates the first amount of memory and the second amount of memory in a single memory allocation operation.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: September 20, 2016
    Assignee: Google Inc.
    Inventors: Hannes Payer, Daniel Kenneth Clifford, Ben Titzer, Michael Starzinger
  • Patent number: 9436596
    Abstract: Described is using flash memory, RAM-based data structures and mechanisms to provide a flash store for caching data items (e.g., key-value pairs) in flash pages. A RAM-based index maps data items to flash pages, and a RAM-based write buffer maintains data items to be written to the flash store, e.g., when a full page can be written. A recycle mechanism makes used pages in the flash store available by destaging a data item to a hard disk or reinserting it into the write buffer, based on its access pattern. The flash store may be used in a data deduplication system, in which the data items comprise chunk-identifier, metadata pairs, in which each chunk-identifier corresponds to a hash of a chunk of data that indicates. The RAM and flash are accessed with the chunk-identifier (e.g., as a key) to determine whether a chunk is a new chunk or a duplicate.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: September 6, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sudipta Sengupta, Biplob Kumar Debnath, Jin Li