Abstract: An appliance is described. A write engine may process a write request from an application to write a first data into a memory. The write request may including the first data and an address. A compression engine may compress the first data to produce a first compressed data. A write module may store the first compressed data in the memory. The first data may be a first part of a page that may further include a second data as a second part. The first compressed data may be a first part of a compressed page that may further include a second compressed data as a second part.

Abstract: A performance monitoring system includes a metric collector configured to receive, via metric exporters, telemetry data comprising metrics related to a network of computing devices. A metric time series database stores related metrics. An alert rule evaluator service is configured to evaluate rules using stored metrics. The performance monitoring system may include a machine learning module and is configured to determine optimized metric collection sampling intervals and rule evaluation intervals, and to automatically determine recommended alert rules.

Abstract: A memory system includes a memory device including an array of storage transistors organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, a write queue configured to store active write requests for writing data to the memory device, a command selector to select one or more commands issued by the read queue or the write queue, and a virtual to physical address translator to convert the memory address of the selected command encoded with the virtual bank index to a corresponding memory physical addresses, the selected command with the memory physical address being issued to the memory device for execution at the memory device.

Abstract: An interactive graphic design system design interface is described to enable design users to create a variant component that links multiple design elements as variants, where each variant represents a state or version of a run-time object, feature or user-interface.

Abstract: The present disclosure relates to fragmentation evaluation in a memory system. In one example, a method for operating a memory controller includes receiving, from a host, a request for a fragmentation level of a file stored in a memory device. The method further includes determining a read performance level of the file based on a logical-to-physical (L2P) address mapping table corresponding to the file without reading the file from the memory device. The method further includes determining the fragmentation level based on the read performance level.

Abstract: The disclosure provides a method, a distributed controller and a system for managing sequential storage devices in a distributed storage environment. The method comprising receiving a client allocation request from a client device and determining at least one zone set from a plurality of zone set based on the client allocation request and predefined I/O parameters. Each zone set of the plurality of zone set comprises a plurality of zones of sequential storage devices. Thereafter, method comprises provisioning the at least one zone set to the client device based on the client allocation request, thereby, managing the sequential storage devices. Each zone of a sequential storage device is arranged into a zone set based on at least one of sequential storage device parameters, and zone parameters. The use of the distributed controller allows optimizing the performance of the sequential storage devices and optimizing the network bandwidth utilization.

Abstract: Methods and systems are provided for configuring static memory in a device by analyzing a set of functionalities of a first device based on at least one use case wherein the at least one use case are associated with configuring available static memory in processing at least one functionality of the first device; configuring at least a first profile composed of the first part for memory allocation of the available static memory to a first processor, and a second part for memory allocation of the available static memory to a second processor of the first device; selecting the first profile either automatically or via a graphical user interface (GUI) by identifying a set of performance characteristics related to the functionality, and implementing the memory allocation by the first profile in processing the at least one functionality in the use case by the first device.

Abstract: A victim management unit (MU) for performing a media management operation is identified. The victim MU stores valid data. A source cursor associated with the victim MU is identified from an ordered set of cursors. A target cursor following the source cursor in the ordered set of cursors referencing one or more available MUs is identified. In response to determining that the source cursor is a last cursor in the ordered set of cursors, the source cursor is utilized as the target cursor. The valid data is associated with the identified target cursor.

Abstract: Techniques are described herein that are capable of dynamically re-allocating computing resources while maintaining network connection(s). Applications of users are run in a computing unit. Computing resources are allocated among the applications based at least in part on dynamic demands of the applications for the computing resources and resource limits associated with the respective customers. In a first example, the computing resources are dynamically re-allocated among the applications, as a result of changing the resource limit of at least one customer, while maintaining at least one network connection between a client device of each customer and at least one respective application. In a second example, the computing resources are dynamically re-allocated among the applications, as a result of changing the resource limit of at least one customer, while maintaining at least one network connection between an interface and a client device of each customer.

Abstract: A non-volatile memory includes physical blocks each including a respective plurality of cells, where each cell is capable of storing multiple bits of data. A controller maintains dynamically resizable pools of physical blocks, including at least a low-density pool in which cells are configured to store fewer bits and a high-density pool in which cells are configured to store more bits. The controller repeatedly dynamically resizes the low-density and the high-density pools based on write utilization of the non-volatile memory.

Abstract: Provided is an operating method of a storage device including a memory controller and a memory device, the operating method including storing a plurality of streams received from a host in the memory device; performing a management operation on a first storage region of the memory device in which a first stream from among the plurality of streams is stored; and performing a management operation on a second storage region of the memory device in which a second stream selected from among the plurality of streams based on an attribute of the first stream is stored.

Abstract: Improved bit error correction for non-volatile memory can be implemented in multiple stages achieving improved correction capacity. As an example, bit error correction for a set of data can utilize a logic or a differential algorithm applied to one or more copies (N) of the set of data to produce a logic (or differential) output. An error correction code (ECC) can be applied to the logic (or differential) output to produce corrected data that corrects bit errors of the set of data, if any, up to a maximum for the ECC selected. An algorithm can be selected to address measured bit error rates or variations in bit error rates among binary bit states of a non-volatile memory.

Abstract: Systems, methods, and apparatuses to low-latency page decompression and compression acceleration are described. In one embodiment, a system on a chip (SoC) includes a hardware processor core, and an accelerator circuit coupled to the hardware processor core, the accelerator circuit comprising a decompressor circuit and a direct memory access circuit to: in response to a first descriptor sent from the hardware processor core, cause the decompressor circuit to decompress compressed data from the direct memory access circuit into decompressed data and store the decompressed data in a buffer in the accelerator circuit, and in response to a second descriptor sent from the hardware processor core separately from the first descriptor, cause the decompressed data to be written from the buffer to memory external to the accelerator circuit by the direct memory access circuit.

Abstract: This application is directed to managing garbage collection using a plurality of queues of memory bands of a memory system. The memory system obtains a request to organize data stored in a plurality of memory bands of the memory system, and each memory band has a data validity level. In response to the request, the memory system generates the plurality of queues of memory bands based on the data validity levels of the plurality of memory bands, and the plurality of queues correspond to a plurality of non-overlapping validity level ranges. The plurality of memory bands are assigned into a subset of queues based on the data validity levels of the plurality of memory bands. The memory system 200 allocates a first memory bandwidth among the subset of queues, and implements garbage collection operations on the subset of queues in parallel using respective portions of the first memory bandwidth.

Abstract: A method and system for providing memory in a computer system. The method includes receiving a memory access request for a shared memory address from a processor, mapping the received memory access request to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.

Abstract: A distributed storage space management method, a computing device and a storage medium are provided. An embodiment is applied to a hardware smart card, which is deployed on a local host as a local hardware smart card. A corresponding storage space is partitioned for a local virtual device from a pre-configured storage device; the partitioned storage space is simulated to generate a simulated storage device corresponding to the local virtual device, for use by the local virtual device. A storage space application request of a remote hardware smart card is received, and according to the request, a corresponding storage space is partitioned for a remote virtual device from the pre-configured storage device, so that the partitioned storage space is simulated by means of the remote hardware smart card to generate a simulated storage device corresponding to the remote virtual device, for use by the remote virtual device.

Abstract: Methods, systems, and devices for memory system logical unit number (LUN) procedures are described. A memory system may receive an indication to convert a LUN for storing LBAs associated with an application from a first type to a second type, where the second type is associated with a higher performance defragmentation process than the first type. The memory system may perform defragmentation on data associated with the LUN based on converting the LUN to the second type. The memory system may determine whether the LBAs stored in the LUN are ordered based on the defragmentation, and the memory system may operate (e.g., execute) the application based on the LBAs being ordered.

Abstract: The present application relates to a garbage collection method and a storage device for reducing write amplification. A method for selecting a data block to be collected in garbage collection, including: obtaining, according to a first selection policy, a first data block to be collected; determining, according to a first rejection policy, whether to refuse to collect the first data block to be collected; and if according to the first rejection policy, rejection to collect of the first data block to be collected is determined, not performing garbage collection on the first data block to be collected.

Abstract: An electronic device including an application processor and a communication processor. The communication processor, for managing a resource memory, configured to monitor an occupancy rate of the resource memory for detecting a memory leakage, release a network connection when the electronic device is in an idle state, in response to the detecting of the memory leakage, initialize the resource memory after the network connection is released, and reconnect the network connection, wherein the idle state indicates a state when the electronic device is not occupied or used by a user, and wherein the initialization is performed at a non-flag area from among the resource memory.

Abstract: A technique for computing resource management involves determining a first resource request frequency based on the number of trigger signals received from a storage device during a first period. The trigger signals are generated when a data amount of modified metadata stored in the storage device reaches a threshold data amount. The technique further involves determining a second resource request frequency based on the number of trigger signals received from the storage device during a second period subsequent to the first period. The technique further involves adjusting computing resources for performing an operation of copying the modified metadata in the storage device to a storage medium based on a comparison of the first resource request frequency and the second resource request frequency. Accordingly, computing resources can be fully utilized, and an operation of copying modified metadata to a magnetic disk can be timely performed.

Abstract: A method and system for providing a lock-free self-service queue. The method includes enqueuing at least one node in the queue; competing, by producer threads, to append their respective nodes to a last node of the queue; allowing only one producer thread to append its respective node to the last node of the queue, in which unsuccessful producer threads either give up or reattempt to append their nodes to the appended node; and allowing at least one of the producer threads to temporarily operate as a consumer thread to process the first non-deleted node, and then logically delete at least one non-mark-deleted node among the nodes, in which the at least one consumer thread and others of the producer threads are concurrently executed; and modifying the next node pointer field of the last node of the enqueued at least one node to include an address of the appended node.

Abstract: A data management system includes: a transceiver; a memory; and a processor communicatively coupled to the transceiver and the memory and configured to: receive, via the transceiver, a copy data request for unstructured data; access, via the transceiver in response to the copy data request, a plurality of backed-up files of unstructured data stored in a first data storage device; send, in response to the copy data request, a plurality of Virtual Data Files (VDFs) to a second data storage device, the processor being configured to respond to receipt of information from each of the plurality of VDFs to retrieve a respective backed-up file of unstructured data of the plurality of backed-up files of unstructured data stored in the first data storage device.

Abstract: A serial presence detect (SPD) device includes nonvolatile memory to store SPD information. Parity information suitable for single error correct and double error detect (SEC-DED) is also stored in association with the SPD information in the nonvolatile memory. The combination of SPD information and parity information is organized into codewords addressable at each memory location. During an initialization period occurring after a power on reset and before the SPD device is accepting I2C commands, the SPD device checks each memory location (codeword) for errors. Each error detected is counted to provide an indicator of device health. Before the initialization period expires, the SPD device writes a corrected codeword back to the nonvolatile memory.

Abstract: Systems and methods for recovery from power events in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform and an Out-of-Band (OOB) Microcontroller Unit (MCU) integrated into the heterogeneous computing platform or an Embedded Controller (EC) integrated into or coupled to the heterogeneous computing platform, where the OOB MCU or EC is configured to, in response to detection of an impending power event, store an OOB command onto a non-volatile memory.

Abstract: A computer system comprising: a data storage medium comprising a plurality of storage devices configured to store data; and a data storage controller coupled to the data storage medium; wherein the data storage controller is configured to: determine a target number of storage devices in a group of storage devices in a storage system that may exhibit variable I/O response times; detect one or more conditions associated with the group of storage devices; and after detecting the one or more conditions, change the target number of storage devices that may exhibit variable I/O response times.

Abstract: Another electronic device includes a processor configured to, while the processor maintains user privilege, receive a deallocation request for a dynamically allocated target memory area, while the processor maintains kernel privilege, determine whether another memory area including a code accessing the target memory area exists, and when the other memory area does not exist, while the processor maintains the user privilege, deallocate the target memory area.

Abstract: When a host I/O request is received, logging each transaction that is to be performed to process the host I/O request includes selecting from between a first persistent storage and a second persistent storage to identify the location to which the transaction is to be logged, and then logging the transaction to the selected location. The selection may be made based on a log policy indicating percentages of transactions to be logged to each of the first persistent storage and the second persistent storage. The percentages may be calculated periodically based on a dynamically measured performance characteristic of the first data storage, such as latency. All transactions for host I/O requests below a threshold minimum size, and/or all transactions for host I/O requests received while the current system throughput is below a minimum system throughput, may be logged to the first persistent storage.

Abstract: Disclosed herein are an apparatus, non-transitory computer readable medium, and method for querying big data and displaying the results of the query. A multilevel hierarchy of data structures is associated with a particular date to reduce the linearity of the search. The client receiving the query results stores the results in a linked list with a record format consistent with the resulting records. The client also periodically refreshes a graphical user interface with the query results until all the results are received.

Abstract: Provided are systems, methods, and apparatuses for transferring computational tasks. In one or more examples, the systems, methods, and apparatuses include a first host configured to detect a trigger to offload instruction code from the first host to a second host; identify, based on the trigger, an address translation binding for the instruction code and an address translation binding for application data associated with the instruction code; copy the address translation binding for the instruction code and the address translation binding for the application data to a memory; and transfer control of execution of the instruction code to the second host based on the copying.

Abstract: A data processing system with a dataset multiplexer that enables applications to be written to specify access to datasets as operations on logical datasets. During execution of an application by the data processing system, operations that access a dataset are implemented by accessing an entry in a dataset catalog for the logical dataset. That entry includes information to access the physical data source storing the logical dataset, including conversion of data from the format of the physical data source to the format of the logical dataset. An entry in the catalog may be created based on registration of a data source with the dataset multiplexer and may be updated automatically based on changes in storage of the dataset. This maintenance of the catalog may be partially or totally automated such that the system automatically adjusts to any changes in storage of the dataset without need for modification of any application.

Abstract: Workload distribution in a system including a non-volatile memory device is disclosed. A request is received including an address associated with a memory location of the non-volatile memory device. A hash value is calculated based on the address. A list of node values is searched, and one of the node values in the list is identified based on the hash value. A processor is identified based on the one of the node values, and the address is stored in association with the processor. The request is transmitted to the processor for accessing the memory location.

Abstract: The application relates to a computing device comprising one or more processors and one or more memory devices having stored thereon computer readable instructions which, when executed by the one or more processors, cause the computing device to establish a storage module for storing a data file. The storage module is configured to: load a data file from a data source into the storage module; compute a hash value of the data file loaded into the storage module and make said hash value available to a hash value consumer; grant read-only access to data consumer(s) for accessing said data file loaded into the storage module. The storage module is further configured to detect any change and/or attempted change of the data file and terminate all data consumers which have been granted access to the data file.

Abstract: According to one embodiment, a controller identifies a fourth storage location on which a second step program operation is executed last among storage locations of a block and determines whether a condition that a fifth storage location stores unreadable data and each of memory cells of a sixth storage location has a threshold voltage corresponding to an erased state, is satisfied. Among the storage locations, in response to completion of a first step program operation on the fifth storage location, the second step program operation on the fourth storage location has been executed, and the first step program operation on the sixth storage location is to be executed after completion of the second step program operation on the fifth storage location.

Abstract: Read Quality of Service in a solid state drive is improved by allowing a host system communicatively coupled to the solid state drive to control garbage collection in the solid state drive. Through the use of controlled garbage collection, the host system can control when to start and stop garbage collection in the solid state drive and the number of NAND dies engaged in garbage-collection operations.

Abstract: A management system for managing a cache memory including a randomization module configured for generating a random value for each process of accessing the cache memory, and for transforming addresses of the cache memory with said random value into randomized addresses, a history table configured to store therein on each line an identification pair associating a random value corresponding to an access process, with an identifier of the corresponding access process, so forming identification pairs that are operative to dynamically partition the cache memory while registering the access to the cache memory, and a state machine configured to manage each process of accessing the cache memory according to the identification pairs stored in the history table.

Abstract: This application discloses a data access method and apparatus, and relates to the storage field. In this application, a write request is received; a destination address of a memory area corresponding to to-be-written data is obtained based on address indication information included in the write request; and the to-be-written data is written, in an append write manner, into the memory area indicated by the destination address. After the to-be-written data is written into the memory area, a read/write attribute corresponding to the destination address is set, so that data in the memory area cannot be modified, thereby effectively avoiding illegal tampering with the data stored in the memory area, and implementing read-only protection on data in a storage class memory (SCM) medium.

Abstract: A process includes providing a first signal to a first conductive mesh of a semiconductor package to provide a wireless transmission, and receiving, by a second conductive mesh of the semiconductor package, the wireless transmission to provide a second signal. The process includes determining a signature of the second signal and generating, by a cryptographic security parameter generator of the semiconductor package, a cryptographic security parameter based on the signature.

Abstract: Migrating content between enterprise content management systems is described. A source object identifier is identified for metadata tables for content for a source enterprise content management system, based on a migration job definition. The metadata tables are retrieved from the source enterprise content management system, based on the source object identifier. A target object identifier is identified for a target enterprise content management system, based on the metadata tables and the migration job definition. An object identifier map is created that maps the source object identifier to the target object identifier. The metadata tables are stored to the target enterprise content management system, based on the object identifier map. The content for the source enterprise content management system is retrieved. The content is stored as content for the target enterprise content management system.

Abstract: A memory system includes a non-volatile memory device and a performance manager. The performance manager activates a plurality of sub-controllers according to a setting of a host device, allocates memory regions respectively to the plurality of sub-controllers, the memory regions being included in the non-volatile memory device, and determines, according to maximum performance values and a size ratio of the memory regions, credit sets to be allocated respectively to the plurality of sub-controllers.

Abstract: A method, computer program product, and computing system for generating a plurality of artificial storage devices for a storage system, wherein each artificial storage device includes a defined storage capacity. A total useable storage capacity for the storage system is defined based upon, at least in part, the defined storage capacity for each artificial storage device and a storage capacity associated with a plurality of physical storage devices. One or more input/output (IO) requests are processed on the storage system. An IO request concerning an artificial storage device of the plurality of artificial storage devices is discarded.

Abstract: According to an example of the present disclosure, a system is provided. A system may include a main memory including a dynamic memory cell electrically coupled to a bitline and a word line, and a memory controller configured to selectively omit a restore operation during a read operation of the dynamic memory cell.

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to enumerate respective sideband addresses to ten or more memory devices, and provide bi-directional communication with an individual memory device of the ten or more memory devices with a particular sideband address enumerated to the individual memory device. Other embodiments are disclosed and claimed.

Abstract: A memory chip includes at least two memory blocks. In a method for controlling power supply for the memory blocks of the memory chip, each memory block receives a command for switching to standby mode. The commands are issued, for example by a processor, separately for each memory block in order to be able to individually place the memory block in standby mode.

Abstract: Systems and methods for reducing the provisioned storage capacity of a disk or aggregate of disks of a storage appliance while the storage appliance continues to serve clients are provided. According to one embodiment, the size of the aggregate may be reduced by shrinking the file system of the storage appliance and removing a selected disk from the aggregate. When an identified shrink region includes the entire addressable PVBN space of the selected disk, the file system may be shrunk by relocating valid data from the selected disk elsewhere within the aggregate. After the valid data is relocated, the selected disk may be removed from the aggregate, thereby reducing the provisioned storage capacity of the aggregate by the size of the selected disk.

Abstract: Disclosed herein are a memory device and a method of operating the memory device. The memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell may a plurality of main memory blocks and a plurality of sub-memory blocks included in each of the main memory blocks. The peripheral circuit may perform a program operation on the main memory blocks or the sub-memory blocks, detect an amount of data loaded for the program operation, and output data amount information. The control logic may control the peripheral circuits so that, during the program operation, at least one memory block is selected from the main memory blocks or from the sub-memory blocks according to the data amount information and the program operation is performed on the selected memory block.

Abstract: A synchronous control apparatus includes an internal clock, a plurality of internal routes that are internal routes through which a synchronization packet passes as a part of a communication route and a transmission or reception time of the synchronization packet is acquired from the internal clock, and are internal routes provided in such a manner as to correspond to communication routes of a plurality of systems that are independent of each other, a synchronous control unit configured to synchronize the internal clock using the synchronization packet, a detection unit configured to detect abnormality of the communication route, a route control unit configured to, in a case where abnormality of the communication route has been detected, connect an internal route of a system in which abnormality has been detected to an internal route of a normal system.

Abstract: Systems and methods for integrating an embedded controller (EC) into a heterogenous computing platform. In an embodiment, an Information Handling System (IHS) includes a heterogeneous computing platform having a Reduced Instruction Set Computer (RISC) processor and a plurality of devices coupled to an interconnect, and an EC coupled to the interconnect. These systems and methods may provide an EC with access to an internal System-on-Chip (SoC)'s fabric, whether in a fully internal, partially internal/external, or fully external implementation (e.g., via an enhanced serial peripheral interface or “SPI”). These systems and methods may also provide voltage segregation factor and power sequencing, as well as various possible architectural variations on General Purpose I/O (GPIO) handling.

Abstract: A device calculates a memory oversubscription threshold for a virtual machine (VM). Based on the memory oversubscription threshold, the device determines a first memory size to be physically allocated to the VM, and a second memory size to be oversubscribed to the VM. The device configures a first virtual non-uniform memory access (NUMA) node comprising a virtual processor and a first virtual memory having the first memory size. The device allocates a first physical memory to back the first virtual memory. The device configures a second virtual NUMA node comprising a second virtual memory having the second memory size. The second virtual NUMA node is a computeless NUMA node. The device configures the VM to use the first virtual NUMA node and the second virtual NUMA node. Based on the second virtual NUMA node being computeless, the VM funnels a memory access to the first virtual memory.

Abstract: An integrated circuit device includes a first memory to support address translation between local addresses and fabric addresses and a processing circuit, operatively coupled to the first memory. The processing circuit allocates, on a dynamic basis as a donor, a portion of first local memory of a local server as first far memory for access for a first remote server, or as a requester receives allocation of second far memory from the first remote server or a second remote server for access by the local server. The processing circuit bridges the access by the first remote server to the allocated portion of first local memory as the first far memory, through the fabric addresses and the address translation supported by the first memory, or bridge the access by the local server to the second far memory, through the address translation supported by the first memory, and the fabric addresses.

Abstract: Systems and methods for providing an external embedded controller (EC) with access to internal resources of a heterogenous computing platform. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include: a heterogeneous computing platform having a Reduced Instruction Set Computer (RISC) processor and a plurality of devices coupled to an interconnect; and an external EC coupled to the interconnect via a bridge integrated into the heterogeneous computing platform, where the bridge is configured to provide the external EC with access to the plurality of devices. These systems and methods may provide an EC with access to an internal System-on-Chip (SoC)'s fabric, whether in a fully internal, partially internal/external, or fully external implementation (e.g., via an enhanced serial peripheral interface or “SPI”).