Memory Configuring Patents (Class 711/170)
  • Patent number: 12088722
    Abstract: A method for executing a computer program includes incorporating, into metadata of a block containing a line of code to be accessed using a pointer, a first pointer identifier associated with the line of code to be accessed, then obtaining a pointer including a first range of bits containing the address of the line of code to be accessed, and a different second range of bits containing a second pointer identifier, then verifying that the second pointer identifier contained in the obtained pointer corresponds to the first pointer identifier associated with the line of code to be accessed and contained in the metadata of the loaded block, and when the first and second pointer identifiers do not correspond, then the security module triggers signaling of an execution fault.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: September 10, 2024
    Assignee: Commissariat à l'Energie Atomique et aux Energies Alternatives
    Inventors: Olivier Savry, Thomas Hiscock
  • Patent number: 12087357
    Abstract: Various implementations described herein are directed to a device having memory circuitry having multi-port bitcells, wherein each bitcell of the multi-port bitcells has a read-write port and a read port. The device may have read-write circuitry coupled to the read-write port, wherein the read-write circuitry has write-drive logic and read-sense logic that provide for at least one write and at least one read in a single clock cycle.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: September 10, 2024
    Assignee: Arm Limited
    Inventors: Yew Keong Chong, Sriram Thyagarajan, Andy Wangkun Chen, Arjun Singh, Ayush Kulshrestha
  • Patent number: 12086121
    Abstract: Techniques for compressing a data set in a manner such that the data set is represented as a geometric filter are disclosed. Here, the geometric filter has a small memory footprint, thereby enabling the data set to be indexable without consuming a large amount of memory. One bits can be represented within a bit vector portion of the geometric filter or in an index portion of the geometric filter. Techniques are also provided to determine a level of similarity between two data sets, where the data sets have been compressed such that the data sets are representable as geometric filters. The data sets can be indexed without consuming large amounts of memory, and the similarity determination can be performed rapidly. Approximate minimum spanning trees (MSTs) are also generated to find an optimal compression for the data sets, such that the indexes are smaller and searching operations are faster.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: September 10, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Alexander Ulrich Neubeck
  • Patent number: 12086409
    Abstract: An example method for optimizing data deletion in a storage system comprises: detecting a command to delete data from a storage volume using a file system, the data stored on one or more blocks within a storage device associated with the storage volume; monitoring a load metric associated with the storage volume, the load metric indicative of a dynamically changing operational load of the storage volume; and initiating, based on the detecting the command and on the monitored load metric, a discard request for the storage device, the discard request commanding the storage device to indicate that the one or more blocks are free for use by the file system to store additional data.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: September 10, 2024
    Assignee: Pure Storage, Inc.
    Inventors: Ganesh Sangle, Chia-Chun Lin, Prabir Paul, Vijayan Satyamoorthy Srinivasa
  • Patent number: 12086432
    Abstract: An apparatus with a solid state drive (SSD) configured to manage storage resources for proof of space activities. The SSD has a host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands and the write commands. In response to an indication of a storage space request for the host system, the apparatus identifies a portion of storage resources used to store the data of the proof of space plot, and reallocates the portion to service the host system. Subsequently, the SSD can continue proof of space activities based on the proof of space plot using the data stored in a remaining portion of the storage resources initially allocated to the proof of space plot.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: September 10, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Luca Bert, Joseph Harold Steinmetz
  • Patent number: 12086470
    Abstract: The present invention realizes a storage device that has a high data reduction effect without decreasing I/O performances. The storage device includes a processor, an accelerator, a memory, and a storage medium, the processor specifies data to be compressed that is data stored in the storage medium from data stored in the memory and transmits a compression instruction including information relating to the data to be compressed to the accelerator, and the accelerator reads the plurality of continuous items of data from the memory and compresses the plurality of items of data to be compressed obtained by excluding data that is not to be compressed from the plurality of items of data, based on the information relating to the data to be compressed received from the processor, to generate compressed data stored in the storage device.
    Type: Grant
    Filed: December 24, 2021
    Date of Patent: September 10, 2024
    Assignee: HITACHI, LTD.
    Inventors: Takashi Nagao, Tomohiro Yoshihara, Akira Yamamoto, Yuusaku Kiyota
  • Patent number: 12079121
    Abstract: Systems and methods for computer memory management by a memory coordinator and a plurality of memory consumers. An urgency and memory quota of each memory consumer is initialized by the memory coordinator, which then adjusts the memory quota of each memory consumer such that the sum of the memory quota of each memory consumer does not exceed a finite amount of computer memory. Each memory consumer adjusts its memory usage in response to the quota input and urgency input from the memory coordinator.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: September 3, 2024
    Assignee: Kinaxis Inc.
    Inventors: Angela Lin, Robert Walker, Marin Creanga, Dylan Ellicott, Alex Fitzpatrick
  • Patent number: 12079119
    Abstract: Systems, computer program products, and methods are described herein for auto-scaling volatile memory allocation in an electronic network. The present invention is configured to access metadata of at least one volatile memory component, wherein the metadata is associated with at least one application; determine a current volatile memory allocation for the metadata; determine a current metadata format of the metadata; apply the metadata to a volatile memory allocation machine learning model; generate, based on the application of the metadata to the volatile memory allocation machine learning model, a new volatile memory allocation for the metadata; and apply the new volatile memory allocation to the metadata of the at least one volatile memory component, wherein the application of the new volatile memory allocation to the metadata comprises at least one of an upscaling, a downscaling, or a constant.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: September 3, 2024
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Karthee M, Abhishek Sharma, Sudarshan Sridharan
  • Patent number: 12079472
    Abstract: A data reduction method, apparatus, and computing device and a storage medium are provided. The method includes: when reduction is to be performed on a to-be-reduced data block, obtaining a fingerprint of the to-be-reduced data block; forming an index set based on the fingerprint of the to-be-reduced data block by using index information of data blocks with identical fingerprints; and performing, in the to-be-reduced data block based on the fingerprint of the to-be-reduced data block, data reduction processing on a data block to which index information in a same index set belongs.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: September 3, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Bang Liu, Liyu Wang, Kun Guan, Wen Yang, Jianqiang Shen
  • Patent number: 12079189
    Abstract: A test query of a database is performed in response to determining that a performance associated with a user database query of the database does not satisfy a first performance threshold. In response to a determination that the performance of the test query satisfies a second performance threshold, a database buffer cache of the database is resized. Resizing the database buffer cache includes: determining a metric based at least in part on a storage size of the database and an index size of the database, and resizing the database buffer cache of the database based on the metric and a size of the database buffer cache.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: September 3, 2024
    Assignee: ServiceNow, Inc.
    Inventor: Ankit Khetarpal
  • Patent number: 12079124
    Abstract: A method to access memory in a physical memory space includes receiving a logical line address (LLA) from a processor, converting the LLA to a physical line address (PLA) and a physical channel address (PCA), and accessing the memory using the PLA and PCA. The memory has multiple memory channels, and multiple memory regions. A memory device may occupy an intersection of a memory region and a memory channel. The conversion includes determining the memory region from the LLA, and determining a region relative address (RRA) from the LLA. The method determines an interleave factor (IF) from the region, and a device line address (DLA) and an uncorrected channel address (UCA) from the RRA and the IF. The method determines the PLA from the DLA and the memory region, and it determines the PCA from the UCA and the memory region.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: September 3, 2024
    Assignee: SambaNova Systems, Inc.
    Inventors: Paul J. Jordan, Manish K. Shah
  • Patent number: 12079127
    Abstract: Systems and methods for random fill caching and prefetching for secure cache memories are provided. The system dynamically de-correlates fetching a cache line to the processor from filling the cache with this cache line, due to a demand memory access, in order to provide greater security from information leakage due to cache side-channel attacks on cache memories. The system includes a random fill engine which includes a random number generator and an adjustable random fill window. Also provided is an adaptive random fill caching system which dynamically adapts the random fill window to a wide variety of computational workloads. Systems and methods for cache prefetching to improve system performance using adaptive random fill prefetching and random fill prefetching are also provided.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: September 3, 2024
    Assignee: Coresecure Technologies, LLC
    Inventors: Ruby B. Lee, Fangfei Liu
  • Patent number: 12072808
    Abstract: A processor comprising a first storage managed as a circular buffer to store a plurality of data structures. Each data structure comprises: an identifier, a size indicator and first data associated with instructions for execution of a task. The processor is configured for searching for a data structure in the first storage. A data structure subsequent to the tail data structure can be located using a storage address in the first storage of a tail data structure and the size indicator of all data structures preceding the second data structure among the plurality of data structures. When a data structure is found, the task may be executed based at least in part on the first data of the found data structure.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: August 27, 2024
    Assignee: Arm Limited
    Inventors: Jens Olson, Jared Corey Smolens
  • Patent number: 12068939
    Abstract: A central networking system supports efficient identification and analysis of problems that occur at associated nodes on the network. Using network monitoring rules, the central networking system samples data from a subset of nodes in response to an indication that an error or problem has occurred on the network. If the collected sample data is determined to satisfy certain network conditions, the central networking system proceeds to perform network operations on nodes of the entire network, as appropriate. Thus, the system does not need to collect data from every node in a large network to address potential network threats. The central networking system also defines rules for detecting when a node experiencing a problem violates safety conditions such that it is impossible or inadvisable to pull analytical data from the node. The system performs appropriate remedial actions to address the node problems prior to requesting data for analysis.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: August 20, 2024
    Assignee: DocuSign, Inc.
    Inventor: Aaron Matthew Tyler
  • Patent number: 12061822
    Abstract: Utilizing volume-level policies in a storage system, including: identifying, for each of a plurality of volumes, one or more characteristics associated with usage of the volume; associating, using the one or more characteristics associated with the usage of the volume, one or more storage system policies with the volume; and configuring, using the one or more storage system policies that are associated with the volume, the storage system.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: August 13, 2024
    Assignee: PURE STORAGE, INC.
    Inventor: Farhan Abrol
  • Patent number: 12061792
    Abstract: A method for use in a flash memory to handle host write commands includes: performing a dummy pattern detection while programing data into a specific section of a first block or a first super block of the flash memory; setting a dummy pattern indicator if all the data that is programmed to the specific section of the first block or the first super block of the flash memory corresponds to a predetermined dummy pattern; and in response to host write commands, modifying a host-to-flash (H2F) address mapping table regarding data that is requested by the host write commands to be programmed to a second block or a second super block of the flash memory without programming the data into the second super block or the second block to complete the host write commands if the dummy pattern indicator is set.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: August 13, 2024
    Assignee: Silicon Motion, Inc.
    Inventors: Meng-Hua Yang, Chia-Chi Liang
  • Patent number: 12061911
    Abstract: An information handling system may include a processor and a basic input/output system configured to be the first code executed by the processor when the information handling system is booted and configured to initialize components of the information handling system into a known state, the basic input/output system further configured to implement a virtual machine monitor, the virtual machine monitor configured to isolate resources of the information handling system allocated to a network boot process of the information handling system from other resources of the information handling system allocated to other components of the basic input/output system.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: August 13, 2024
    Assignee: Dell Products L.P.
    Inventors: Sumanth Vidyadhara, Shubham Kumar
  • Patent number: 12056372
    Abstract: The disclosed technologies provide functionality for collecting quality of service (“QoS”) statistics for in-use child physical functions of multiple physical function (“PF”) non-volatile memory devices (“MFNDs”). A host computing device creates a child PF on a MFND and configures the child PF on the MFND to provide a specified QoS level to an associated VM executing on the host computing device. The MFND then collects child PF QoS statistics for the child PF that describe the utilization of resources provided by child PF to an assigned VM. The MFND provides the child PF QoS statistics from the MFND to the host computing device. The collected child PF QoS statistics can be utilized to inform decisions regarding reallocation of MFND-provided resources, provisioning of new MFND-provided resources, and for other purposes.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: August 6, 2024
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Scott Chao-Chueh Lee, Lei Kou, Monish Shantilal Shah, Brenda Wai Yan Bell
  • Patent number: 12058013
    Abstract: Systems, devices, and methods discussed herein enable the provisioning of one or more virtual resources within a cloud-computing environment based at least in part on user-defined constraints. By way of example, a request to provision one or more virtual resources within the cloud-computing environment may be received. The request may include a set of user-defined constraints. Placement data indicating a mapping of a particular virtual resource to a particular hardware resource may be obtained based at least in part on the set of user-defined constraints. The virtual resource(s) may be provisioned within the cloud-computing environment in accordance with the set of user-defined constraints based at least in part on utilization of the placement data.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: August 6, 2024
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventor: Eden Grail Adogla
  • Patent number: 12056089
    Abstract: A method for deleting obsolete files from a file system is provided. The method includes receiving a request to delete a reference to a first target file of a plurality of target files stored in a file system, the first target file having a first target file name. A first reference file whose file name includes the first target file name is identified. The first reference file is deleted from the file system. The method further includes determining whether the file system includes at least one reference file, distinct from the first reference file, whose file name includes the first target file name. In accordance with a determination that the file system does not include the at least one reference file, the first target file is deleted from the file system.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: August 6, 2024
    Assignee: Google LLC
    Inventors: Yasushi Saito, Sanjay Ghemawat, Jeffrey Adgate Dean
  • Patent number: 12056380
    Abstract: Methods, apparatus, systems and articles of manufacture to deduplicate duplicate memory in a cloud-computing environment are disclosed herein. An example apparatus to deduplicate duplicate memory comprises a parser to parse process information corresponding to instances of an application, a group generator to group process information into application groups based on the process information indicating instances corresponding to the same directory paths and application names, a data structure generator to generate a pair of binary search trees for an application group, and a merge controller to deduplicate duplicate memory contents detected in the application group.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: August 6, 2024
    Assignee: Intel Corporation
    Inventors: Bin Yang, Jia Bao, Ying Huang, Yao Zu Dong, Yong Yao, Fengqian Gao, Mohammad Haghighat, Mingqiu Sun, Zhen Zhou, Tao Xu
  • Patent number: 12050780
    Abstract: Methods, systems, and devices for adaptive temperature protection for a memory controller are described. In some cases, a memory system may include a set of temperature sensors distributed across the memory system. The set of temperature sensors may be used to monitor or model the temperature of one or more sections of the memory system. Upon determining that the temperature of a section exceeds a threshold, the memory system may employ one or more mitigation techniques to reduce the temperature or the rate of change of the temperature of the section. For example, the memory system may reduce a clock frequency corresponding to the section, while maintaining separate clock frequencies for other sections of the memory system. Additionally or alternatively, the memory system may transfer data or other information from the section to a separate section.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: July 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Federica Cresci, Massimiliano Patriarca
  • Patent number: 12050926
    Abstract: An example method of handling, at a hypervisor on a host in a virtualized computing system, a write input/output (IO) operation to a file on a storage device having a virtual machine file system (VMFS) is described. The method includes: generating logical transactions for the write IO operation having updates to metadata of the VMFS for the file; estimating, for the logical transactions, common space reservations for those of the updates to common fields in the metadata for the file; estimating, for the logical transactions, exclusive space reservations for those of the updates to exclusive fields in the metadata for the file; batching the logical transactions into a physical transaction, which includes a single reservation of space in a journal of the VMFS based on the common space reservations and a reservations of space in the journal for each of the exclusive space reservations, respectively.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: July 30, 2024
    Assignee: VMware LLC
    Inventors: Prasanna Aithal, Prasad Rao Jangam, Srinivasa Shantharam, Mahesh Hiregoudar, Rohan Pasalkar, Srikanth Mahabalarao
  • Patent number: 12050539
    Abstract: A data access method and apparatus and a storage medium are disclosed. In an embodiment, a storage device receives from a client a first data write request that includes target data to be written and an address of a service logical space corresponding to the target data; and determines, based on an address of the service logical space, a target hard disk in the storage device and an address of a hard disk logical space corresponding to the service logical space. The storage device further writes the target data into the target hard disk based on the address of the hard disk logical space.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: July 30, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Yang Liu
  • Patent number: 12050531
    Abstract: In accordance with the described techniques for data compression and decompression for processing in memory, a page address is received by a processing in memory component that maps to a first location in memory where data of a page is maintained. The data of the page is compressed by the processing in memory component. Further, compressed data of the page is written by the processing in memory component to a compressed block device responsive to the compressed data satisfying one or more compressibility criteria. The compressed block device is a portion of the memory dedicated to storing data in a compressed form.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: July 30, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kishore Punniyamurthy, Jagadish B Kotra
  • Patent number: 12052262
    Abstract: A system and method to manage privileges, wherein privileges are assigned to uniquely identifiable objects and a link between a uniquely identifiable object and a uniquely identifiable programmable device is established. The established link allows the uniquely identifiable programmable device to make use of at least a part of the privileges assigned to the uniquely identifiable object. The link is established under a set of preconditions, where at least the precondition of physical proximity between the uniquely identifiable object and the uniquely identifiable programmable device is verified. The uniquely identifiable object includes a irreproducible security device, which is registered to the uniquely identifiable object and can be used to verify physical proximity between the uniquely identifiable object and the uniquely identifiable programmable device by authenticating the irreproducible security device by optical authentication means.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: July 30, 2024
    Assignee: Authentic Vision GmbH
    Inventors: Thomas Weiss, Thomas Bergmüller
  • Patent number: 12045468
    Abstract: A storage device includes a nonvolatile memory device (NVM) and a storage controller. The NVM includes a first region configured to store user data and a second region not allocated to a user. The storage controller is configured to be connected with a host device through both a first-type bus and a second-type bus different from the first-type bus. The storage controller is configured to receive a first and second request from the host device through the first-type bus. In response to the first request, the storage controller is configured to perform an operation on the NVM. In response to the second request, the storage controller is configured to store first data associated with the storage device in the second region and access the second-type bus to obtain second data of at least one external device obtained by the host device and store the second data in the second region.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: July 23, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongouk Moon, Hyunjoon Yoo
  • Patent number: 12045461
    Abstract: A victim management unit (MU) for performing a media management operation is identified. The victim MU stores valid data. An ordered set cursors is maintained. A source cursor of the ordered set of cursors associated with the victim MU is identified. A target cursor of the ordered set of cursors referencing one or more available MUs is identified as the cursor following the source cursor in the ordered set of cursors. The valid data is associated with the identified target cursor.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: July 23, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Patent number: 12045477
    Abstract: An information processing apparatus includes a processor connected to a programmable logic circuit. The processor is configured to: upon initialization, reconfigure a first region of the programmable logic circuit as a first memory that stores data; reconfigure a second region different from the first region of the programmable logic circuit as a first arithmetic circuit that uses the first memory; and, in a case where the second region reconfigured as the first arithmetic circuit is reconfigured as a second arithmetic circuit different from the first arithmetic circuit, allow the second arithmetic circuit to use the first memory.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: July 23, 2024
    Assignee: FUJIFILM BUSINESS INNOVATION CORP.
    Inventor: Masahiro Ishiwata
  • Patent number: 12045466
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to receive a current access request for a storage media associated with a stream, identify a hint in the current access request which indicates one or more stream characteristics for future access requests from the stream, and handle the current access request based on the indicated one or more stream characteristics for future access requests from the stream. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: July 23, 2024
    Assignee: Intel Corporation
    Inventor: Francesc Guim Bernat
  • Patent number: 12045517
    Abstract: Techniques of the present disclosure can include: identifying blocks of storage available for allocation; generating a list denoting an allocation order of storage chunks of the blocks; receiving a write I/O operation that writes data to a first logical address; allocating a storage chunk in accordance with the allocation order of the list, wherein a first block includes the storage chunk and a second storage chunk; storing the first data in the storage chunk of the first block; removing the second storage chunk from the list; and creating a mapping between the first logical address and the first block indicating the second storage chunk is reserved for storing content written to a logical address included in a volume logical address range comprising the first logical address. The allocation order can spread allocation distance between blocks and chunks of the same block to avoid contention during flushes.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: July 23, 2024
    Assignee: Dell Products L.P.
    Inventors: Alexander Shknevsky, Oran Baruch, Maor Rahamim, Vamsi K. Vankamamidi
  • Patent number: 12045482
    Abstract: A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, a temperature of the memory block is compared to a threshold temperature range. In response to determining the temperature of the memory block is within the threshold temperature range, the processing device causes execution of a wordline leakage test of a wordline group of a set of wordline groups of the memory block. A result of the wordline leakage test of the target wordline group is determined and an action is executed based on the result of the wordline leakage test.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: July 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Wai Leong Chin, Francis Chee Khai Chew, Trismardawi Tanadi, Chun Sum Yeung, Lawrence Dumalag, Ekamdeep Singh
  • Patent number: 12045166
    Abstract: Disclosed herein is an architecture for in-memory sorting of data and methods by utilizing memristors crossbar arrays to perform in-memory sorting for both unary bit-stream and binary format data sets and method for utilizing same. Evaluations of the disclosed architecture and method reflect a significant reduction in energy costs and processing time as compared to currently available solutions.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: July 23, 2024
    Assignee: University of Louisiana at Lafayette
    Inventors: Mohammadhassan Najafi, Mohsen Riahi Alam, Nima Taherinejad
  • Patent number: 12045479
    Abstract: A storage node can include one or more processors and one or more storage disks, where the one or more storage disks include one or more local physical extents (PEs) that are local to the storage node. The storage node can include a protection pool driver executed by the one or more processors to run in a kernel space of the storage node, where the protection pool driver includes a local disk manager (LDM) and an array group module (AGRP). The LDM can be configured to manage the one or more local PEs at the one or more storage disks. The AGRP can include a number of storage arrays, where each of the storage arrays includes one or more virtual disks, where each of the one or more virtual disks is associated to at least a local PE or an external PE external to the storage node.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: July 23, 2024
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Paul Nehse, Michael Thiels, Devendra Kulkarni
  • Patent number: 12039371
    Abstract: A memory allocation method for a neural network includes determining information about N memory blocks, sorting the N memory blocks in descending order based on sizes of the N memory blocks, allocating a first memory block to the neural network, to perform an operation for a first node set in the neural network, determining whether a memory block in an allocated set is reusable for an nth memory block, where the allocated set includes a memory block that has been allocated to the neural network, if the memory block in the allocated set is reusable for the nth memory block, allocating, to the neural network, the memory block to perform an operation for an nth node set in the neural network, then updating the allocated set, and sequentially performing the foregoing determining from n=2 to n=N based on the sort sequence.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: July 16, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Lihua Huang, Hao Ding, Aoxiang Fan
  • Patent number: 12041167
    Abstract: A lock node for storing data and a protected storage unit. The lock node includes an input section which provides a plurality of key maps, each corresponding to one of a plurality of primary keys, respectively, applied to the input section, each key map including at least one main key, a variable lock section producing a derived key from a logical operation on the main keys corresponding to the primary keys applied to the input section, and an output section producing the data in response to the derived key.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: July 16, 2024
    Assignee: NUTS HOLDINGS, LLC
    Inventors: Yoon Auh, Nicholas Bennig, Sotirios Triantafillou
  • Patent number: 12039165
    Abstract: Storage bandwidth for a storage system process is adjusted responsive to an input output (I/O) write request to write data to a zoned storage device. The storage bandwidth is adjusted by calculating an allocation share for the storage system process requesting to write the data and opening a new zone for the storage system process upon determining that an open zone usage by the storage system process is under the allocation share for the storage system process.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: July 16, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Ronald Karr, Timothy W. Brennan
  • Patent number: 12040999
    Abstract: Technology for an eNodeB operable to decode a sounding reference signal (SRS) received from a user equipment (UE) is disclosed. The eNodeB can decode the SRS received from the UE, wherein 5 the SRS is received using one or more SRS resources in a subframe where each SRS resource includes one or more symbols. The subframe can be an uplink subframe dedicated for SRS transmission or a short transmission time interval (sTTI) subframe used for SRS transmission. The eNodeB can determine uplink channel quality information for a channel between the eNodeB and the UE based in part on the 10 SRS.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: July 16, 2024
    Assignee: APPLE INC.
    Inventors: Alexei Davydov, Sameer Pawar, Avik Sengupta
  • Patent number: 12035350
    Abstract: Adaptive pairing of an access point (AP) slice with other computing resource slices is disclosed. Pairing of an AP slice can comprise pairing to a radio access network (RAN) slice and/or to a network core component (core) slice. The pairing can be based on end point device information, AP environment information, user preference information, and state information for a RAN and/or CN slice. Coordinating or synchronization of AP, RAN, and/or core slices can enable streamlining of migration of a device from an AP component to a RAN component. Moreover, AP slice coordination can enable efficient use of network computing resources tailored to needs of devices connecting to an AP device. A determined pairing, e.g., AP-core, AP-RAN-core, RAN-core, etc., can be modified before provisioning or after provisioning in response to changes in device demands and/or AP state/environment.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: July 9, 2024
    Assignee: AT&T Intellectual Property I, L.P.
    Inventor: Yupeng Jia
  • Patent number: 12032967
    Abstract: Devices and methods for partial sorting for coherence recovery are provided. The partial sorting is efficiently executed by utilizing existing hardware along the memory path (e.g., memory local to the compute unit). The devices include an accelerated processing device which comprises memory and a processor. The processor is, for example, a compute unit of a GPU which comprises a plurality of SIMD units and is configured to determine, for data entries each comprising a plurality of bits, a number of occurrences of different types of the data entries by storing the number of occurrences in one or more portions of the memory local to the processor, sort the data entries based on the determined number of occurrences stored in the one or more portions of the memory local to the processor and execute the sorted data entries.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: July 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthäus G. Chajdas, Christopher J. Brennan
  • Patent number: 12032835
    Abstract: Aspects of the innovations herein are consistent with a storage system for storing variable sized objects. According to certain implementations, the storage system may be a transaction-based system that uses variable sized objects to store data, and/or may be implemented using data stores, such as arrays disks arranged in ranks. In some exemplary implementations, each rank may include multiple stripes, each stripe may be read and written as a convenient unit for maximum performance, and/or a rank manager may be provided to dynamically configure the ranks. In certain implementations, the storage system may include a stripe space table that contains entries describing the amount of space used in each stripe. Further, an object map may provide entries for each object in the storage system describing the location, the length and/or version of the object.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: July 9, 2024
    Assignee: Primos Storage Technology, LLC
    Inventor: Robert E. Cousins
  • Patent number: 12032965
    Abstract: Systems, apparatuses, and methods for arbitrating threads in a computing system are disclosed. A computing system includes a processor with multiple cores, each capable of simultaneously processing instructions of multiple threads. When a thread throttling unit receives an indication that a shared cache has resource contention, the throttling unit sets a threshold number of cache misses for the cache. If the number of cache misses exceeds this threshold, then the throttling unit notifies a particular upstream computation unit to throttle the processing of instructions for the thread. After a time period elapses, if the cache continues to exceed the threshold, then the throttling unit notifies the upstream computation unit to more restrictively throttle the thread by performing one or more of reducing the selection rate and increasing the time period. Otherwise, the unit notifies the upstream computation unit to less restrictively throttle the thread.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: July 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul James Moyer, Douglas Benson Hunt, Kai Troester
  • Patent number: 12026103
    Abstract: A resource request is received by a peripheral device from host processing logic. The resource request includes a requested resource size. The peripheral device allocates resource of the peripheral device in response to the resource request. A resource response is sent by the peripheral device to the host processing logic. The resource response includes a location of the allocated resource.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: July 2, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Georgy Machulsky, Nafea Bshara, Netanel Israel Belgazal, Evgeny Schmeilin, Said Bshara, Alexander Matushevsky
  • Patent number: 12026055
    Abstract: A storage device, and a method for operating a storage device. In some embodiments, the storage device includes storage media, and the method includes: determining, by the storage device, that the storage device is in a fault state from which partial recovery is possible by operating the storage device in a first read-only mode; and operating the storage device in the first read-only mode, the operating in the first read-only mode including: determining that the age of a first data item stored in a page of the storage device has exceeded a threshold age, and copying the first data item into a rescue space in the storage device.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: July 2, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yang Seok Ki, Dong Gi Daniel Lee, Sung Wook Ryu, Ehsan Najafabadi
  • Patent number: 12026371
    Abstract: A method, system, and device for writing compressed data to a disk, and a readable storage medium. The method includes: acquiring compressed data, and determining a length of the compressed data; storing the compressed data in a linked list, and adding the length of the compressed data to a linked list length, wherein the linked list length is a total length of all compressed data in the linked list; determining whether the linked list length exceeds a threshold value; and if YES, allocating an idle thread to merge all the compressed data in the linked list, and carrying out a write-to-disk operation on the merged compressed data.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: July 2, 2024
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventor: Guoqiang Qi
  • Patent number: 12026100
    Abstract: A method at a computing device for sharing data, the method including defining a dynamically linked data library (DLDL) to include executable code; loading the DLDL from a first process, the loading causing a memory allocation of shared executable code, private data and shared data in a physical memory location; mapping the memory allocation of shared executable code, private data and shared data to a virtual memory location for the first process; loading the DLDL from a second process, the loading causing mapping of the memory allocation of shared executable code and the shared data for the first process to be mapped to a virtual memory location for the second process; and allocating private data in physical memory and mapping to a virtual memory location for the second process.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: July 2, 2024
    Assignee: BlackBerry Limited
    Inventor: Scott Lee Linke
  • Patent number: 12019541
    Abstract: Techniques for lazy compaction are disclosed, including: selecting, by a garbage collector, multiple regions of a memory for inclusion in a relocation set; populating, by the garbage collector, a lazy free list (LFL) with the multiple regions selected for inclusion in the relocation set; subsequent to populating the LFL: determining, by an allocator, that an ordinary free list managed by the garbage collector is depleted; responsive to determining that the ordinary free list is depleted: selecting a region in the LFL; executing one or more load barriers associated respectively with one or more objects marked as live in the region, each respective load barrier being configured to relocate the associated object from the region if the associated object is still live; subsequent to executing the one or more load barriers: allocating the region.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: June 25, 2024
    Assignee: Oracle International Corporation
    Inventors: Erik Österlund, Stefan Mats Rikard Karlsson
  • Patent number: 12019890
    Abstract: A data processing method in a storage system is provided. The method includes: when the storage system is under a first load, performing an inline deduplication operation; and when the storage system is under a second load, directly storing a received second data block without performing the inline deduplication operation, where the first load is less than the second load.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: June 25, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ren Ren, Chen Wang, Haijun Dai, Fangfang Zhu
  • Patent number: 12019921
    Abstract: To speed up decoding of a range code. A decompression circuit calculates a plurality of candidate bit values for each bit of the N-bit string based on a plurality of possible bit histories of a bit before a K-th bit in parallel for a plurality of bits, and repeatedly selects a correct bit value of the K-th bit from the plurality of candidate bit values based on a correct bit history of the bit before the K-th bit to decode the N-bit string.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: June 25, 2024
    Assignee: HITACHI, LTD.
    Inventors: Nagamasa Mizushima, Kentaro Shimada
  • Patent number: 12019422
    Abstract: A control device configured to control an industrial machine, the control device having: a plurality of memories including a first memory configured to hold data when a power supply is off and a second memory configured to inhibit data from being held when the power supply is off; and circuitry configured to: set, in each of a plurality of data units, an attribute indicating whether the data unit is to be held when the power supply is off; and set an address of each data unit such that each data unit is stored in one of the plurality of memories corresponding to the attribute.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: June 25, 2024
    Assignee: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Masaomi Kudo, Takefumi Matsunaga, Hiroyuki Ishibashi, Yuki Yoshida