Abstract: An access circuit for efficiently accessing a buffer memory in accordance with an instruction from an external circuit. An access data unit for accessing a SDRAM in one operation clock cycle of the access circuit may be switched between one byte, one word, and two words. The switching of the access data unit is performed in accordance with a data unit designation signal generated by decoding address data, which is provided to a control unit, with an address decoder. The memory interface receives a request signal that is in accordance with the data unit designation signal from a request generator and accesses the buffer memory in the access data unit that is in accordance with the request signal.

Abstract: Disclosed is a circuit for implementing a special mode in a packet-based semiconductor memory device, which performs the special mode in the same manner as a normal operation without changing the semiconductor memory devie from a special mode register to a control register mode prior to a normal operation or at the middle of the normal operation after an initial operation having a reset operation. A packet receiving part receives external packet data. A register controller generates a control signal to select a special mode register according to a value of a first field among the external packet data received by the packet receiving part. A register value generator generates a value of the special mode register selected by the control signal from the register controller according to a value of a second field among the received external packet data when the register controller generates the control signal.

Abstract: A multiprocessor computer system to selectively transmit address transactions using a broadcast mode or a point-to-point mode. Either a directory-based coherency protocol or a broadcast snooping coherency protocol is implemented to maintain coherency. A node is formed by a group of clients which share a common address and data network. The address network determines whether a transaction is conveyed in broadcast mode or point-to-point mode. The address network includes a table with entries which indicate transmission modes corresponding to different regions of the address space within the node. Upon receiving a coherence request transaction, the address network may access the table to determine the transmission mode which corresponds to the received transaction. Network congestion may be monitored and transmission modes adjusted accordingly. When network utilization is high, the number of transactions which are broadcast may be reduced.

Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.

Abstract: An apparatus and method for generating a comparand in a content addressable memory array. The apparatus includes a content addressable memory (CAM) array and translation circuitry to receive translation information indicative of translation of a bit group from an initial position in input data to a different position in a comparand transmitted to the CAM array. The translation circuitry includes a switch circuit, one or more storage elements to store the translation information, and one or more decode circuitry to decode the translation information and establish switch circuit connections between the initial position and the position in the comparand. The apparatus also includes program circuitry to provide a bit level programming interface with the translation circuitry. The apparatus may also include a programming bit register to store programming information in the form of a binary pattern where each bit represents a bit group of the input data.

Abstract: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time.

Abstract: A data processing (10) includes memory management circuitry (14) which allows additional control over the physical address (83) and over the address attributes (84) which are provided for use by data processing system (10). One use of this additional control over the physical address (83) and over the address attributes (84) is to avoid address translation failure and unintended modification of cache (13) and memory (18) system state during debugging.

Abstract: Techniques are provided for recycling addresses in memory blocks. Address signals in memory blocks are stored temporarily in a set of parallel coupled address registers. The address registers transfer the address signals to an address decoder block, which decodes the address signals. The address decoder block transfers the decoded addresses to a memory array. A stall state occurs when the cache memory block needs a new set of data to replace the old set of data. Address signals are stored in the address registers during the stall state by coupling each register's output to its data input using a series of multiplexers. The multiplexers are controlled by an address stall signal that indicates the onset and the end of a stall state. After the end of a stall state, the address registers store the next address signal received at the memory block.

Abstract: The invention concerns a device for storage and search of textual and graphic data in electronic form, said device comprising display means, user-interface means, control means, means for storing said data, means for selecting data to be displayed according to the user's instructions. The invention is characterized in that it comprises a multiplexed address bus.

Abstract: A novel method of providing alternate access to a storage element for holding a data element in a network interface. The storage element is accessed via a first access path when the network interface operates with a first type of software, and via a second access path when a second type of software is used. The first access path is allocated in response to a first address signal identifying a first register required by the first type of software to hold the data element. The second access path is allocated in response to a second address signal identifying a second register required by the second type of software to hold the data element.

Abstract: A computer system provides improved routability for memory modules. Chips are placed on the back side of the module directly behind the chips on the front side, and vias connects destination pins on the front side to the back side. Internal assignments are routed to the pins so as to be bilaterally symmetrical. These functions can include any of the pins used on the memory chip, including the address bus and the command bus. The bit positions of the internal assignments routed to pins connected together need not be identical. Where bit positions are coupled together, a remap multiplexer is used to perform rerouting of logical information onto different physical bus lines. The remap multiplexer may be implemented in the system BIOS, in the memory controller, or altematively on the memory module. Further, the rerouting may be accomplished through any combination of hardware or software.

Abstract: A method and apparatus for a source synchronous address receiver for a system bus. In one embodiment, a flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin. Other embodiments are described and claimed.

Abstract: A memory management unit (MMU) includes a translation look-aside buffer (TLB) that stores memory access steering data within corresponding TLB entries for use in steering memory access operations.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: An apparatus comprising a memory, a plurality of modules, an address translation unit and a controller. The memory may be arranged as a plurality of memory banks. Each of the plurality of modules may be configured to generate one or more addresses for accessing a particular one of the plurality of memory banks. The address translation unit may be configured to modify the one or more addresses in response to a control signal. The controller may be configured to generate the control signal in response to a computer executable instruction.

Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem A for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the I/O subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: To provide a communication apparatus that can relieve the processing load when packet transfer is made with hardware. A packet transfer apparatus includes an input buffer for storing temporarily an input packet, an address acquiring section for acquiring the information needed for the transfer, a retrieval circuit for retrieving the information regarding the output with the acquired destination address as a key, a label insertion circuit for encapsulating a packet with the labels in the maximum number of stack layers M designated for a packet group having a unit of destination address, and a switch section for switching the encapsulated packet to a desired output destination port.

Abstract: A memory controller provides programmable flexibility, via one or more configuration registers, for the configuration of the memory. The memory may be optimized for a given application by programming the configuration registers. For example, in one embodiment, the portion of the address of a memory transaction used to select a storage location for access in response to the memory transaction may be programmable. In an implementation designed for DRAM, a first portion may be programmably selected to form the row address and a second portion may be programmable selected to form the column address. Additional embodiments may further include programmable selection of the portion of the address used to select a bank. Still further, interleave modes among memory sections assigned to different chip selects and among two or more channels to memory may be programmable, in some implementations.

Abstract: A heterogeneous computer system, a heterogeneous input/output system and a data back-up method for the systems. An I/O subsystem A for an open system and an I/O subsystem B for a mainframe are connected by a communication unit. In order to back up data from at least a disk connected to the I/O subsystem B in a MT library system and in order to permit the mainframe to access the data in the I/O subsystem B, the I/O subsystem A includes a table for assigning a vacant memory address in a local subsystem to the memory of the I/O subsystem A for an open system. A request of variable-length record format received from the mainframe is converted into a fixed-length record format for the subsystem B. The disk designated according to the table is accessed, and the data thus obtained is sent to the mainframe and backed up in the back-up system.

Abstract: A micro-controller is connected to an external circuit via an address bus and a read control signal line. The external circuit includes an enable circuit, a decoder and a register group. The enable circuit produces an enable signal from the sixteenth bit of 16-bit information on the address bus and a control signal on the read control signal line. The decoder creates an address from the ninth to fifteenth bits of the 16-bit information. When the enable signal is valid, the register group writes a signal value of the first to eighth bits of the 16-bit information into a register specified by the address. Accordingly, the micro-controller can send the read control signal, the register address and the register data to the external circuit via the address bus. It is therefore possible to write data into the external circuit without using a write control signal line.

Abstract: A multiplexed addressed data bus are provided for transferring data between two microprocessors. The multiplexed address and data bus include a plurality of multiplexed lines for communicating between the two microprocessors. A read/write signal line is also provided for communicating between the two microprocessors for indicating whether a read or a write operation is to be preformed. A chip select line is provided for transitioning to an enable condition during a data transfer cycle. A data strobe line is in communication between the two microprocessors and provides a strobe signal for each sequence of a data transfer cycle.

Abstract: A multiplexed address and data bus are provided for transferring data between two microprocessors. The multiplexed address and data bus include a plurality of multiplexed lines for communicating between the two microprocessors. A read/write signal line is also provided for communicating between the two microprocessors for indicating whether a read or a write operation is to be performed. A chip select line is provided for transitioning to an enable condition during a data transfer cycle. A data strobe line is in communication between the two microprocessors and provides a strobe signal for each sequence of a data transfer cycle.

Abstract: A system for optimizing data storage and retrieval by an audio/video system using a number of different tables is disclosed. According to one aspect of the system, the system includes two different types of hierarchical file allocation tables (HFATs), a contiguous space table, a track table and a list table. The two different types of HFATs are a 0th order HFAT and a 1st order HFAT. Each of the two types of HFATs contains a number of entries. Each 0th order HFAT entry corresponds to a specific disk block and each 1st order HFAT entry corresponds to a specific subdivision within a subdivided disk block. A 0th order HFAT entry and an 1st order HFAT entry is linkable to one another to allow disk blocks and subdivisions which make up a file to be identified. The contiguous space table is used to store information relating to the location and availability of contiguous spaces or disk blocks. The track table contains a number of records. Each record, in turn, contains various track, HMSF and descriptor information.

Abstract: An apparatus generates addresses for circular address buffers in a memory, in which a higher boundary of a circular buffer is implied from the current address. This approach is applied alone, and in combination with circular buffers which rely on an implied lower boundary to improve memory usage and flexibility in the design of circular buffers for integrated circuits. The dual mode address generator comprises inputs that receive a current address A, an address offset M, a buffer length L and a control signal; and logic configured to compute a first memory address for a buffer with an implied lower boundary and a second memory address for a buffer with an implied higher boundary in response to A, M, and L. One of the first and second memory addresses is provided in response to the control signal.

Abstract: The present invention relates to a micro controller development system (MDS) capable of helping a development of hardware and related software of a micro control unit (MCU).

Abstract: A method and apparatus for a source synchronous address receiver for a system bus is described. A flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin.

Abstract: The present disclosure relates to an address sub-sampling apparatus and method, and an image sensor employing the same. An address sub-sampling apparatus includes a counting unit that generates a binary address of N bits, N being a natural number larger than 2. The address sub-sampling apparatus also includes an address conversion unit that sub-samples the binary address of N bits to output a sub-sampled address having first, second and third bit groups, wherein the sub-sampled address is arranged in order of the third, the first and the second bit groups from the MSB (Most Significant Bit).

Abstract: A scalable multicast protocol buffers the multicast messages at a subset of “C” members, where C is selected to reduce to an acceptable level the probability that a given message will be lost before it reaches at least one of the C members. When a member receives a multicast message, the member determines whether or not it should buffer the message by manipulating a string of bytes that is unique to both the message and the member and determining if the result is less than a calculated value C/n, where “n” is the number of known members. When one of the C bufferers thereafter receives a gossip message that indicates that the multicast message has been lost to the gossiping member, the bufferer retransmits the message to the gossiping member. When a member that is not one of the C bufferers receives such a gossip message, the member determines which members are bufferers of the lost message and requests that one of the bufferers retransmit the message to the gossiping member.

Abstract: A semiconductor circuit device (encoder) is provided with: a functional block for carrying out an encoding process and for generating a first access signal for accessing a memory; a slave IF terminal for receiving a second access signal; and a first selector having a first connection mode for electrically connecting the functional block and the memory so as to supply the first access signal to the memory and a second connection mode for electrically connecting the slave IF terminal and the memory so as to supply the second access signal to the memory. Each of the first and second access signals has an address signal for specifying a storing position in the memory and a control signal for controlling the operation of the memory.

Abstract: A set of related methods for detecting the existence and exact nature of any rearrangements and/or inversions of address lines and/or data lines to a memory device, relative to a second set of address lines and/or data lines to the same memory, are disclosed. Moreover, a set of related methods for correcting these relative rearrangements and/or inversions are disclosed. These methods allow meaningful access to memory shared by two or more devices using different address and data paths in the case where the relative nature of the address and data paths is unknown a priori. These methods of detecting and correcting such mismatches in separate address and data lines to shared memory may be implemented either in hardware or software or a combination of both.

Abstract: A switching router memory map is organized as 64-bit wide double words. The bi-directional data bus is only 32-bits wide, so the Least Significant Words (LSW) are mapped to the even addresses and the Most Significant Words (MSW) are mapped to the odd address. When the host writes to the even address the 32-bit data is stored in the bidirectional data bus buffer. When the host writes to the odd address the entire 64-bit double word access is posted to the appropriate global access bus. When a read operation is performed from an even address the entire 64-bit double word access is performed by the appropriate global access bus. The LSW is available on the bi-directional data bus address data pins and the 32-bit MSW is buffered within the bi-directional data bus. The host can access the MSW by performing a read from the odd address.

Abstract: There is here set out a storage access unit, which contains an address register and a data register. A processor has access to these registers independently of any operational mode for access to a static storage unit or a dynamic storage unit.

Abstract: An object of the invention is to provide an image memory system capable of efficiently reading out image data also in case of consecutively reading out image data from an image memory along a direction other than the direction in which a burst access can be performed. In case that a bit-map image is partitioned into square or rectangular blocks and image data of pixels contained in one block are made to correspond to one row space, row spaces respectively corresponding to two blocks being adjacent to each other with a common side between them are made to belong to different synchronous DRAMs without fail and all of row spaces respectively corresponding to four blocks having commonly one vertex are made to belong to different banks.

Abstract: A semiconductor device is disclosed that has a plurality of I/O pins that are configurable to selectively output three sets of signals selected from the group consisting of (i) a read enable signal and a write enable signal, (ii) a combined read and write enable signal, (iii) a read enable signal and a pair of byte write enable signals, and (iv) a row address strobe signal, and a column address strobe signal.

Abstract: A database management system that stores and retrieves large data objects (LOBs) from a database storage of a computer system storage device containing a LOB data space having LOB data values of a database. The space management system permits a user of the computer system to generate requests for access to LOBs of a database and includes a plurality of allocation units for storing data. Each allocation unit has an address, and the allocation units are grouped into a plurality of blocks, each block including at least two allocation units. The space management system includes first and second types of space allocation maps. Each of these two types of space allocation maps has a predetermined number of bits. The first type space allocation map represents blocks of allocation units below a predetermined size, and each bit in the first type space allocation map represents the allocation status of a corresponding one of the allocation units at a particular address.

Abstract: An address generation unit (AGU) and a digital signal processor (DSP) including such an AGU are disclosed. The AGU (3) has a register file (4) providing order (R), stage (S), and displacement (N) values to a digital addressing unit (DAU) (5) for performing one of eight addressing operations. The register file provides an input (X) to the DAU and receives an output (Y) from the DAU. Within the DAU (5), selection multiplexers (13, 14) select full adder outputs to provide Y, or bit-select from adders and the input (X) to provide Y. For a radix-4 operation, most significant bits (MSBs) are taken from the input (X), middle bits are taken from the output of a first adder (adder1), and the least significant bits (LSBs) are taken from the output of a second adder (adder2) if there is a carry out from the first adder. The AGU may also include bit reverse blocks connected at both the input and output of an adder.

Abstract: A method and apparatus for accessing data elements of an N-element data block on N memory locations distributed over Q memory modules via Q parallel accesses. The Q memory modules are addressable in a q-bit module address and an (n−q) bit row address in a power-of-two stride fashion. The row address is selected from (n−q) bits of the index address, and the module address for one of the Q accesses is obtained from bitwise exclusive-OR operation on bits obtained from corresponding positions in a plurality of q-bit fields grouped from the index address.

Abstract: A memory controller provides programmable flexibility, via one or more configuration registers, for the configuration of the memory. The memory may be optimized for a given application by programming the configuration registers. For example, in one embodiment, the portion of the address of a memory transaction used to select a storage location for access in response to the memory transaction may be programmable. In an implementation designed for DRAM, a first portion may be programmably selected to form the row address and a second portion may be programmable selected to form the column address. Additional embodiments may further include programmable selection of the portion of the address used to select a bank. Still further, interleave modes among memory sections assigned to different chip selects and among two or more channels to memory may be programmable, in some implementations.

Abstract: A memory to support an Address-Data Multiplexed protocol in response to a substantially simultaneous assertion of RAS and CAS, and an Address—Address Multiplexed protocol in response to an assertion of RAS followed by an assertion of CAS.

Abstract: A system for accessing memory devices includes a processing module coupled to a set of outputs and memory operably coupled to the processing module. The memory stores operational instructions that cause the processing module to perform a plurality of operations. A first one of the plurality of operations includes utilizing a first output to provide a first data lane enable to facilitate accessing of a portion of a first memory storage location associated with a first memory address when in a first mode of operation. A second one of the plurality of operations includes utilizing the first output to provide an address bit of a second memory address to facilitate designation of a second memory storage location when in a second mode of operation.

Abstract: In a digital signal processing unit, addressing apparatus implements a multiplicity of addressing modes. The addressing modes include a circular buffer memory mode, a frame mode, and a sorting mode. To increase the speed of the address modification, the index, the index in the presence of a positive wrap-around, and the index in the presence of negative wrap-around are determined together. Other apparatus determines the addressing mode and provides control signals for the selection of the correct index. The correct index is combined with the base address to provide the next new address.

Abstract: If a word line is selected by inputting an immediate value and base address, whose values are determined at different timings, to an adder, the access speed decreases due to the constraint of the base address whose value is determined at a later timing. According to this invention, decoding is performed by inputting only the immediate value whose value is determined earlier to an address decoder AD. Thereafter, a word line WL is selected by performing rotation using the base address whose value is determined at a later timing. This makes it possible to start decoding processing without waiting for the determination of the value of the base address and increase the overall access speed.

Abstract: A data processing system having a central processing (CPU) unit and a method of operation is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory target ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports. A data transfer address for each load/store instruction is formed by fetching the instruction, decoding the instruction to determine instruction type, transfer data size, and scaling selection, selectively scaling an offset provided by the instruction and combining the selectively scaled offset with a base address value.

Abstract: An apparatus which generates even addressed words and odd addressed words in a memory. The apparatus consists of a port adapted for receiving an address, one or more even units in operative communication with the port and one or more odd units in operative communication with the port. The even units output an even address and the odd units output and odd address. If the input address is even the even address is equal to the input address and if the input address is odd the even address is spaced from the input address by N addresses, where N is an odd integer. If the input address is odd, the odd address is equal to the input address and if the input address is even, the odd address is spaced from the input address by N addresses.

Abstract: A diagnostic program can check the security of a program. The program is stored at predetermined non-relocatable physical address in memory. The diagnostic program is loaded and checks the program at the predetermined physical address against a standard. The diagnostic program then indicates that the program is verified as secure if it meets the standard or non-verified as secure if it does not meet the standard. If the program is not verified as secure, then the diagnostic program may take remedial action such as disabling normal operation of the program, be transmitting a predetermined message via the system modem or downloading another copy of the program via the modem. The program is made non-relocatable using a special table look-aside buffer having a fixed virtual address register and a corresponding fixed physical address register.

Abstract: An information processing apparatus has a DRAM for storing at least predetermined data, a system bus to which the DRAM is connected, a CPU for controlling the DRAM, and a CPU bus to which the CPU is connected. The information processing apparatus also has an SRAM connected to the system bus and the CPU bus, for storing data transferred from the DRAM, an address counter for generating an address of the SRAM based on an initial value, and a DMA controller for controlling data transfer between the DRAM and the SRAM using the address generated by the address counter. At a certain time, the DMA controller outputs an address D2 next to an initial address in the DRAM via the system bus to the DRAM, reads data B from the address D2, and outputs the data B via the system bus to the SRAM. At the same time, the address counter increments a stored address S1 into an address S2, and outputs the address S2 to the SRAM, which stores the data B at the address S2.

Abstract: A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses, using a bypass of the memory array.

Abstract: A PCI read access management system and method to manage read access between two agents providing PCI read requests to conduct contiguous read operations to a central resource at a PCI bus. Dual transaction control logic units are each respectively coupled to a separate one of the agents. An arbitration request connection couples the dual transaction control logic units. A PCI read request by one of the agents (e.g., agent A), and recognized by one of the dual transaction control logic units (e.g., unit 1), is signaled to the arbitration request connection, which arbitrates between the transaction control logic units for reserving the PCI bus for the one agent (agent A), and the one transaction control logic unit (unit 1) provides read access to the PCI bus for the one agent (agent A) for the contiguous read operations. The one transaction control logic unit (unit 1) then maintains the reservation until completion of the contiguous read operations.

Abstract: A resampling address generator updates period data in a resampling period address register when the periods of input and output clocks are not stable, and generates a read address by supplying the output of a register to an accumulative adder. When the periods of the input and output clocks are stable, and a command is internally or externally received, the resampling address generator stops updating of the period data in the register, and generates the read address by supplying the output of the register to the accumulative adder. When the updating of the period data in the register is stopped, and a phase difference detector finds that the phase difference between the write address and the read address is outside a predetermined allowable range, the data in the register is updated based on correction data, and the read address is generated by supplying the output of the register to the accumulative adder.