Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

Abstract: A method for simultaneously accessing a first DRAM device and a second DRAM device includes the steps of: in an active phase, generating a first signal at a first pad, wherein the first signal is provided for the first DRAM device to select a first memory bank group, and the first signal is not for the second DRAM device to select any memory bank group; and generating a second signal at the first pad, wherein the second signal is provided for the first DRAM device to select the first bank group, and the second signal and the first signal correspond to a same digital value.

Abstract: A memory controller for recovering data due to transient effects of nonvolatile memory is provided. A memory controller receives a read request for a page stored in the nonvolatile memory. The memory controller issues a first read command. The memory controller records a time stamp for the first read command. In response to a failure during the first read command, the memory controller waits for a delay after the recorded time stamp and the memory controller issues a second read command to the page, wherein the second read command applies a read voltage offset that is dependent on the delay between the first read command and the second read command and at least one other parameter.

Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

Abstract: Methods of operating a memory device are disclosed. A method may include receiving, at a first die of a number of dies, a first number of bits including one or more command bits, one or more identification bits, and a first number of address bits associated with a command during a first clock cycle. The method may further include conveying, from the first die to at least one other die, at least some of the first number of bits. Further, the method may include receiving, at the first die, a second number of bits including a second number of address bits associated with the command during a second, subsequent clock cycle. Also, the method may include conveying, from the first die to the at least one other die, at least some of the second number of bits. Memory devices and electronic systems are also disclosed.

Abstract: A data processing system comprising: a first memory system coupled to a host through a first external channel, a second memory system coupled to the host through a second external channel, and an internal channel suitable for coupling the first and second memory systems with each other, the host, when read-requesting first and second data to the first memory system, transfers a first external channel control information for selecting sole use of the first external channel or simultaneous use of the first and second external channels, to the first and second memory systems, the first memory system, when the first external channel control information indicates simultaneous use, the first memory system outputs the first data through the first external channel and outputs the second data through the internal channel, and the second memory system outputs the second data inputted through the internal channel, through the second external channel.

Abstract: A data processing system includes: a first memory system coupled to a host through a first external channel, a second memory system coupled to the host through a second external channel, and an internal channel suitable for coupling the first and second memory systems with each other, the host, when read-requesting first and second data to the first memory system, transfers a first external channel control information for selecting sole use of the first external channel or simultaneous use of the first and second external channels, to the first and second memory systems, the first memory system, when the first external channel control information indicates simultaneous use, the first memory system outputs the first data through the first external channel and outputs the second data through the internal channel, and the second memory system outputs the second data inputted through the internal channel, through the second external channel.

Abstract: Methods and apparatus for performing memory access are provided. In one example, an apparatus comprises a hardware processor, a memory, and a bus interface. The hardware processor is configured to: receive, from a host device and via the bus interface, a packet including a host input address, the host input address being defined based on a first host address space operated by the host device; determine, based on the host input address, a host relative address, the host relative address being relative to a first host base address of the first host address space; determine, based on the host relative address, a target device address of the memory; and access the memory at the target device address on behalf of the host device.

Abstract: A method is used in determining suitability of storage. Storage data of a data storage system is analyzed. The storage data includes information associated with use of a storage object of the data storage system by an application of the data storage system. A storage suitability characteristic for the storage object is determined. The storage suitability characteristic for the storage object is provided to a user for provisioning storage for the application in the data storage system.

Abstract: An example method for facilitating multi-level paging and address translation in a network environment is provided and includes receiving a request for memory in a physical memory of a network element, associating the request with a first virtual address space, mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space, remapping the first window in the first virtual address space to the second window in the second virtual address space, and responding to the request with addresses of the second window in the second virtual address space.

Abstract: A peripheral component interconnect (PCI) device includes a PCI register including a base address register (BAR) configured to determine a first memory area accessed by a PCI host, an offset register configured to store an offset transmitted from the PCI host, an address translation unit (ATU) configured to detect an operation of the PCI host writing the offset to the offset register and to change an accessed area by the PCI host to a second memory area based on the offset stored in the offset register, and a device memory including the first memory area and the second memory area, the device memory configured to store data transmitted from the PCI host and to transmit data stored therein to the PCI host.

Abstract: An example method for facilitating multi-level paging and address translation in a network environment is provided and includes receiving a request for memory in a physical memory of a network element, associating the request with a first virtual address space, mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space, remapping the first window in the first virtual address space to the second window in the second virtual address space, and responding to the request with addresses of the second window in the second virtual address space.

Abstract: Disclosed is a nonvolatile storage system including: a memory block having a plurality of flash memories; a flash memory power supply circuit outside of the memory block; and a flash memory controller. The flash memory power supply circuit has a plurality of types of power supply circuits for process execution, the power supply circuits for process execution generating and supplying power at a plurality of voltage levels needed to execute processes in the flash memories. The flash memory controller monitors changes of the internal states of the flash memories by communicating with the flash memories, thereby controlling the power supply circuits for process execution and the flash memories.

Abstract: A system and method for using a Non-Volatile Dual In-Line Memory Module (NVDIMM) (110, 115) is disclosed. The NVDIMM (110, 115) can support two or more access modes. An application can specify which access mode is desired for an address space requested by the application. A Non-Volatile Memory (NVM) governor (150) can store an address mask and the access mode for the address space (305, 310, 315) in an NVM control register (155). When the application requests read or write access to an address (605), the NVM governor (150) can compare the requested address (605) with the address masks in the NVM control register (155), determine the access mode from the access mode corresponding to the matched address mask, and use that access mode to satisfy the request for the address (605).

Abstract: A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of electrical interconnections, and allows the memory device to be placed a greater distance from the processor than is conventional without power-consuming I/O buffers.

Abstract: A multi-core processor system includes a multi-core processor that has plural core groups; and a storage device that stores a constraint on execution time for each application. A first identified core of the multi-core processor is configured to identify a constraint on execution time of a given application that is among the applications and for which an invocation instruction is received; determine whether the identified constraint meets a performance drop condition; assign the given application to a predetermined core of the multi-core processor, upon determining that the identified constraint meets the performance drop condition; and notify a second identified core of a core group among the core groups, of an assignment instruction for the given application, upon determining that the identified constraint does not meet the performance drop condition.

Abstract: Embodiments of the present technology are directed toward techniques for balancing memory accesses to different memory types.

Abstract: An example method for facilitating multi-level paging and address translation in a network environment is provided and includes receiving a request for memory in a physical memory of a network element, associating the request with a first virtual address space, mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space, remapping the first window in the first virtual address space to the second window in the second virtual address space, and responding to the request with addresses of the second window in the second virtual address space.

Abstract: A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of electrical interconnections, and allows the memory device to be placed a greater distance from the processor than is conventional without power-consuming I/O buffers.

Abstract: The provisioning of a volume that has multiple tiers corresponding to different trait sets. The volume to be provisioned is identified along with multiple tiers that are to be in the volume. For each of the tiers that are to be provisioned within the volume, a corresponding trait set is identified as to be applied to each tier. This corresponding trait set may be based on underlying storage systems that are available at the time of provisioning, or which are anticipated to be available. The volume is then caused to be provisioned with the corresponding tiers having the corresponding trait sets. Also, the provisioning of a file, which is determined to have one or more storage traits. Based on these storage traits, the file is then caused to be assigned to an appropriate tier.

Abstract: A resource allocation system begins with an ordered plan for matching requests to resources that is sorted by priority. The resource allocation system optimizes the plan by determining those requests in the plan that will fail if performed. The resource allocation system removes or defers the determined requests. In addition, when a request that is performed fails, the resource allocation system may remove requests that require similar resources from the plan. Moreover, when resources are released by a request, the resource allocation system may place the resources in a temporary holding area until the resource allocation returns to the top of the ordered plan so that lower priority requests that are lower in the plan do not take resources that are needed by waiting higher priority requests higher in the plan.

Abstract: A memory device includes a memory cell with an elementary SRAM-type cell and an elementary module coupled between a supply terminal and the elementary SRAM-type cell. The elementary module has a single nonvolatile EEPROM elementary memory cell that includes a floating gate transistor. The elementary module also has a controllable interconnection stage that can be controlled by a control signal external to the memory cell. The nonvolatile elementary memory cell and the controllable interconnection stage are connected to one another. The floating gate transistor of the nonvolatile memory cell is controllable to be turned off when a data item stored in the elementary SRAM-type cell is programmed into the nonvolatile elementary cell.

Abstract: Separate microchannel voltage domains in a stacked memory architecture An embodiment of a memory device includes a memory stack including one or more coupled memory dies, wherein a first memory die of the memory stack includes multiple microchannels, and a logic chip coupled with the memory stack, the logic chip including a memory controller. Each of the microchannels includes a separate voltage domain, and a voltage level is controlled for each of the plurality of microchannels.

Abstract: An integrated circuit may have configurable storage blocks. Multiple configurable storage blocks may share one or more internal address busses with selected configurable storage blocks having access a given address bus. An address bus may be unidirectional or bidirectional and may convey the same address signal from one configurable address block to another or to several other configurable storage blocks. Tri-state buffers or multiplexers may selectively couple or decouple the address bus between configurable storage blocks. Redundant address bus paths may bypass configurable address blocks in neighboring rows or columns allowing for disabling the respective row or column. The address bus may further have pipeline registers to allow for pipelined access to configurable storage blocks.

Abstract: Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories provide data to the data bus responsive, at least in part, to a first address. The plurality of memories further provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories provide N bits of data to the data bus at different times.

Abstract: A processor includes a translation lookaside buffer (TLB) including a data array and a compare unit. The data array includes a number of entries each configured to store a respective translated physical address. In response to a read access to a given entry of the TLB, the data array is configured to output within a particular clock cycle, the respective translated physical address stored in the given entry. In addition the compare unit may be configured to compare the respective translated physical address output by the data array with a number of additional addresses. The compare unit may also be configured to provide a hit indication for each of the additional addresses within the particular clock cycle.

Abstract: Technologies are generally described for power channel monitoring in multicore processors. A power management system can be configured to monitor the power channels supplying individual cores within a multicore processor. A power channel monitor can provide a direct measurement of power consumption for each core. The power consumption of individual cores can indicate which cores are encountering higher or lower usage. The usage determination can be made without sending any data messages to, or from, the cores being measured. The determined usage load being serviced by each processor core may be used to adjust power and/or clock signals supplied to the cores.

Abstract: Various embodiments of systems and methods for memory access are provided. In one embodiment, a data segment is stored in a plurality of memory segments of at least one memory bank. The data segment stored in the memory segments is selected, where the data segment has a bit boundary that is arbitrarily misaligned with at least one memory segment boundary of the memory segments.

Abstract: A memory interleaver includes a channel selection unit to receive a system memory address for a memory request. The interleaver also includes a local memory address computation unit and a de-multiplexer. The channel selection unit examines a predetermined plurality (n) of bits in a memory address of a memory transaction and assigns the memory transaction to one of a plurality of memory channels in a multi-channel memory unit based on a state of the predetermined plurality of bits. Preferably, 2n is greater than the number of memory channels in the multi-channel memory unit.

Abstract: Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories provide data to the data bus responsive, at least in part, to a first address. The plurality of memories further provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories provide N bits of data to the data bus at different times.

Abstract: Various methods and systems for securing access to hash-based storage systems are disclosed. One method involves receiving information to be stored in a storage system from a storage system client and then generating a key. The key identifies the information to be stored. The value of the key is dependent upon a secret value, which is associated with the storage system. The key is generated, at least in part, by applying a hash algorithm to the information to be stored. The key can then be returned the key to the storage system client. The storage system client can then use the key to retrieve the stored information.

Abstract: An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped, a bank select register which is not mapped to the data memory for selecting a memory bank, and with an indirect access register mapped to at least one memory bank, wherein the instruction set includes a plurality of instructions operable to directly address all memory locations within a selected bank, at least one instruction that provides access to the bank select register, and at least one instruction performing an indirect address to the data memory using the indirect access register.

Abstract: A memory management unit comprises register and control logic and arranged to support a microprocessor controller unit accessing physical address space via an address bus wherein the microprocessor controller unit comprises a program counter having a first address size, the memory management unit wherein the register and control logic comprises a register having a second address size greater than the first address size and arranged to provide an extended address bus between the microprocessor controller unit and physical address space.

Abstract: An address generator includes a storage device in which one or more second-protocol-family address prefixes are stored, the one or more second-protocol-family address prefixes each corresponding to a corresponding combination of at least a multiplexing identifier and a first-protocol-family address, and a controller configured to read, from the storage device, the second-protocol-family address prefix corresponding to a combination of at least the multiplexing identifier and the first-protocol-family address that is contained in a data block to be transferred via a backbone network to a destination network which uses the first protocol family, the read second-protocol-family address prefix serving as an address prefix for a network that is overlaid with the destination network, and configured to generate a second-protocol-family address containing the first-protocol-family address, the multiplexing identifier, and the read second-protocol-family address prefix, the generated second-protocol-family address ser

Abstract: The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.

Abstract: A microcontroller has a data memory divided into a plurality of memory banks, an address multiplexer for providing an address to the data memory, an instruction register providing a first partial address to a first input of the address multiplexer, a bank select register which is not mapped to the data memory for providing a second partial address to a the first input of the address multiplexer, and a plurality of special function registers mapped to the data memory, wherein the plurality of special function registers comprises an indirect access register coupled with a second input of the address multiplexer, and wherein the data memory comprises more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped.

Abstract: An automation device comprising a first functional unit, a second functional unit, a first network connection for connection to a first data network and a bus master unit for connecting a peripheral component. The first functional unit includes a first interface unit that is assigned a first network address, and the second functional unit includes a second interface unit that is assigned a second network address. A partitioning device can be used to logically partition an address space of the peripheral component, and a first address space can be directly assigned, as a partitioned part of the address space, to a superordinate computation unit that can be connected through the first network connection.

Abstract: Methods and apparatus for termination of signal lines coupled to a number of memory devices are disclosed. One such method includes adjusting an input impedance of one or more terminals of an interface of a memory device in response to the memory device receiving a particular address. One such apparatus includes memory devices configured to selectively adjust an input impedance seen by one or more of the signal lines in response to receiving a particular address.

Abstract: Various embodiments for reducing communication between cluster nodes and optimizing failover processing in a distributed shared memory (DSM)-based application by at least one processor device are provided. In one embodiment, for a data structure operable on a DSM, a read-mostly portion is maintained in a single copy sharable between the cluster nodes while an updatable portion is maintained in multiple copies, each of the multiple copies dedicated to a single cluster node.

Abstract: Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories are configured to provide data to the data bus responsive, at least in part, to a first address. The plurality of memories are further configured to provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may be configured to provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories configured to provide N bits of data to the data bus at different times.

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs) and multiple key values from memory. Each key value is indicates a single RV to be output by the TM. A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV is a key selector value. A key value is selected based upon the key selector value. A RV is selected based upon the key value. The key value is selected by a key selection circuit. The RV is selected by a result value selection circuit.

Abstract: A memory controller that generates interface signals for a memory device determines an interface signal frequency based on a timing mode of the memory device and a corresponding clock division ratio. Based on the timing mode, a look up table (LUT) is selected and then a timing parameter corresponding to the clock division ratio and the interface signal frequency is fetched from the LUT. An interface signal is generated based on the interface signal frequency and fetched timing parameter.

Abstract: A communications system includes a communications device having a plurality of access modules each having a port and connected to a communications line and a plurality of transmitters with the respective transmitter associated in one-to-one correspondence with the communications line of an access module. Each transmitter has a line driver and is configured to couple communications signals to a respective communications line. A voltage source is connected to the line drivers and configured to provide a bias voltage to the line drivers that varies depending on a selected minimum power level. A controller is connected to the voltage source and has logic configured to change the bias voltage to the line drivers. The controller is responsive to a minimum data rate for each bias voltage.

Abstract: A method for handling a request of storage on a serial fabric comprising formatting an address for communication on a serial fabric into a plurality of fields including a field comprising at least one set selection bit and a field comprising at least one tag bit. The address is communicated on the serial fabric with the field comprising the at least one set selection bit communicated first.

Abstract: Methods and apparatus for termination of signal lines coupled to a number of memory devices are disclosed. One such method includes adjusting an input impedance of one or more terminals of an interface of a memory device in response to the memory device receiving a particular address. One such apparatus includes memory devices configured to selectively adjust an input impedance seen by one or more of the signal lines in response to receiving a particular address.

Abstract: A content addressable memory (CAM) (100) can include a CAM memory array (102) having both a data field (102-0) and a mask field (102-1). A multiplexer (MUX) (108) can selectively load data from either a register (104) or an external data input (106) to one or both fields (102-0 and 102-1) of CAM memory array (102).

Abstract: A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical record showing a propensity to experience cache-misses at a particular address-offset from a prior cache-miss address within a region of memory provides an indication that data needed by future instructions has an increased likelihood to be located at a similar offset from a current cache-miss address. The prefetch device disclosed herein maintains a record of the relationship between a cache-miss address and subsequent cache-miss addresses for the most recent sixty-four unique data manipulation instructions that resulted in a cache-miss. The record includes a weighted confidence value indicative of how many cache-misses previously occurred at each of a selection of offsets from a particular cache-miss address.

Abstract: A memory and a method for controlling a memory including: a set of first memory blocks of identical size, intended to contain first words, a set of second memory blocks of identical size, intended to contain second words, the number of second words being identical to the number of first words, a third memory block identical to the first blocks, a fourth memory block identical to the second blocks, each memory address comprising a first portion identifying a same line in all blocks, and each first word of the third block identifying a free word from among the second words sharing a same second address portion.

Abstract: To facilitate efficient communications in a multi bus master system that communicates with a plurality of peripheral devices, a two channel bus is used that shares write and read addresses with data on a transmit channel to reduce wiring density and provide efficient, reliable, and high speed data transfers. The two channel bus includes the transmit channel, a receive channel, and a single control channel that provides control information for both the transmit channel and the receive channel further reducing the signaling requirements of the two channel bus. The control information includes a control flag that specifies control information for data transfers on the two channel bus. The control flag and control information may be supplied in two bus cycles or in a single bus cycle depending on the control requirements for two data transfers occurring in parallel on the two channel bus.

Abstract: Some of the embodiments of the present disclosure provide a method for predicting, for a first virtual address, a first descriptor based at least in part on the one or more past descriptors associated with one or more past virtual addresses; and determining, for the first virtual address, a first physical address based at least in part on the predicted first descriptor. Other embodiments are also described and claimed.