Abstract: A method of filtering a target pixel in an image forms, for a kernel of pixels comprising the target pixel and its neighbouring pixels, a data model to model pixel values within the kernel; calculates a weight for each pixel of the kernel comprising: (i) a geometric term dependent on a difference in position between that pixel and the target pixel; and (ii) a data term dependent on a difference between a pixel value of that pixel and its predicted pixel value according to the data model; and uses the calculated weights to form a filtered pixel value for the target pixel, e.g. by updating the data model with a weighted regression analysis technique using the calculated weights for the pixels of the kernel; and evaluating the updated data model at the target pixel position so as to form the filtered pixel value for the target pixel.

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

Abstract: A method for operating a data storage device which includes a nonvolatile memory device including a plurality of memory blocks, includes generating a valid page count table including the number of valid pages of each of closed blocks among the plurality of memory blocks in which data are written in all pages thereof and the number of valid pages of at least one open block among the plurality of memory blocks in which data is written in a part of pages thereof; generating a valid page scan table including a scan pointer for scanning the number of valid pages of the open block; and backing up the valid page count table and the valid page scan table in a meta block among the plurality of memory blocks.

Abstract: Managing access control lists (ACLs) across replicated data repositories can include selecting, from a first data processing system, a controlled object and an ACL object bound to the controlled object, wherein the first data processing system is associated with a first user identity space, and creating, using a processor, a replicated version of the controlled object within a second data processing system associated with a second user identity space, wherein the second user identity space is different from the first user identity space. Managing ACLs further includes, creating, using the processor, a replicated version of the ACL object within the second data processing system and substituting, within the replicated version of the ACL object, an identity from the first user identity space with a selected identity from the second user identity space.

Abstract: A method includes monitoring a given workload running on one or more storage systems to obtain performance data, detecting a given potential performance-impacting event affecting the given workload based at least in part on a given portion of the obtained performance data, and generating a visualization of at least the given portion of the obtained performance data. The method also includes providing the generated visualization as input to a machine learning algorithm, utilizing the machine learning algorithm to classify the given potential performance-impacting event as one of (i) a true positive event affecting performance of the given workload and (ii) a false positive event corresponding to one or more changes in storage resource utilization by the given workload, and modifying provisioning of storage resources of the one or more storage systems responsive to classifying the given potential performance-impacting event as a true positive event affecting performance of the given workload.

Abstract: A memory device includes a memory array having non-volatile memory cells, and a memory controller configured to dynamically construct a superblock during each garbage collection process based, at least in part, on an amount of valid data present in each physical block of the memory array. Another memory device includes physical blocks of memory cells and a memory controller configured to construct a new superblock dynamically each time garbage collection occurs for the physical blocks regardless of whether any physical blocks are determined to be bad. Additional methods for managing operation of a memory device and related electronic systems are also described.

Abstract: The disclosed embodiments are directed to improvements in log-structured merge (LSM) tree databases. In one embodiment, a method is disclosed comprising receiving data to be written to a log-structured merge (LSM) tree, the data including a key and value; determining that an in-memory buffer lacks capacity to store the data to be written; compacting key-ranges stored in at least one level of the LSM tree stored in an object storage device (OSD), each of the key-ranges associated with a respective object identifier; generating a key range object, the key range object including object identifiers associated with a subset of the key-ranges; erasing physical blocks corresponding to each of the object identifiers included in the key range object; and writing the key range object to at least one physical block of the OSD.

Abstract: A system for memory management includes an incoming memory data strobe connecting a memory data interface, and a clock distribution network. The clock distribution network includes an internal clock aligned to the incoming memory data strobe. The system also includes an asynchronous clock domain that is asynchronous with the clock distribution network; and a strobe select circuit configured to align to the incoming memory data strobe. The clock distribution network is configured to propagate read data with reduced latency from the memory data interface to a second interface.

Abstract: A design apparatus includes a processing unit configured to allocate a plurality of RAMs to a FPGA block RAM in at least one of a word direction and a bit direction thereof, and to generate a description, in a hardware description language, of a control circuit that controls input and output signals of each of the plurality of RAMs so as to allow each of the plurality of RAMs to be accessed as a single RAM.

Abstract: A system and method for using virtual physical addresses in a non-volatile memory device are disclosed. The physical layout of the non-volatile memory device may have physical die that are not a power-of-2 in number. In order to advantageously use the power-of-2 die number, which enables using a power-of-2 die interleave, a virtual physical addressing scheme is used. In particular, the virtual physical addressing scheme includes virtual die and virtual blocks, wherein the virtual die are a power-of-2 in number. Further, a conversion between the virtual physical addressing scheme and the actual physical addressing scheme is provided. In this way, for certain operations of the memory device, the virtual addressing scheme is used. For other operations, such as reading from, writing to or erasing, the actual physical addressing scheme is used.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: Memory access in data processing is provided using a time-based technique in which memory locations are mapped to respectively corresponding periods of time during which they are made available for access.

Abstract: An apparatus and associated methodology providing a data storage system including a memory having a first addressable storage space and a second differently addressable storage space. A controller selectively accesses stored instructions that when executed store a first amount of a user data set to the first addressable storage space and store a different second amount of the user data set to the second addressable storage space. The controller subsequently calculates an address increment between the stored first and second amounts, and then shifts one of the stored first and second amounts by the address increment.

Abstract: A method of address generation and corresponding index generator for one or more locations in a buffer with received data, determining an offset address for a specific data element in the buffer; calculating a correction factor in parallel with the determining an offset address; and providing an address for the specific data element in the buffer by combining the offset address and the correction factor, the correction factor adjusting for any impact on the offset address resulting from null elements.

Abstract: A memory system with integrated memory built-in self-test (BIST) circuitry has one or more pipeline registers interposed between combinational logic elements. These combinational logic elements can include write data decoding logic, memory control signal decoding logic, address counter logic, address comparison logic, data comparison logic, and next state decoding logic. Features can be included that compensate for the delay inherent in the pipeline registers.

Abstract: Techniques are provided for accessing sector data. An embedded storage function is received. One or more data management functions are generated in response to receiving the embedded storage function. The one or more data management functions are invoked to retrieve the sector data from a sector table.

Abstract: A convolutional interleaver uses local memory of a first IC in combination with burst-type memory of a second IC. When a burst of data is read from memory of the second IC, one data value is provided to a data output and the remaining values are temporarily stored in local memory. After the memory of the second IC is initially filled, burst WRITE and burst READ operations provide efficient data transmission between the ICs.

Abstract: A file system and method of file access are disclosed. In a particular embodiment, a method is performed at a host device coupled to a non-volatile memory, where the host device includes a memory having a first file data structure. A first directory entry in a file directory of a file system is located where the first directory entry corresponds to a first file stored in the non-volatile memory. First data associated with the first directory entry, including first location data indicating a location of the first file in the non-volatile memory, is retrieved and stored in the first file data structure. A request to open the first file is received. In response, the first location data of the first file is retrieved from the first file data structure and data of the first file from the non-volatile memory is read. First metadata associated with the first file is extracted from the data read from the non-volatile memory.

Abstract: After serially receiving several MSBs of the address, a microcontroller may determine whether a write operation is occurring in the same particular partition. If it is determined that a write operation is not occurring in the same partition, then the microcontroller may immediately perform the read operation. If a write operation is occurring, however, then the microcontroller may first begin to interrupt the write operation before beginning the read operation.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: A non-volatile memory system of a type having blocks of memory cells erased together and which are programmable from an erased state in units of a large number of pages per block. If the data of only a few pages of a block are to be updated, the updated pages are written into another block provided for this purpose. The valid original and updated data are then combined at a later time, when doing so does not impact on the performance of the memory. If the data of a large number of pages of a block are to be updated, however, the updated pages are written into an unused erased block and the unchanged pages are also written to the same unused block. By handling the updating of a few pages differently, memory performance is improved when small updates are being made.

Abstract: A method, computer management apparatus, and computer program product are provided for processing data stored on a sequential storage media within a computational computing environment. A block reference table and most often read blocks are loaded from a modified tape format of a sequential storage media into an internal memory of a sequential storage media device. During write command processing, a data deduplication procedure is performed using a modified block reference table. It is determined if entries from the block reference table must be deleted and responsive to this identifying and deleting host block and device block entries from the block reference table.

Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for managing free chains of compute resources. A system configured to practice the method divides a free chain of compute resources into a usable part (UP) which contains resources available for immediate allocation and an unusable part (UUP) which contains resources not available for immediate allocation but which become available after a certain minimum number of allocations. The system sorts resources in the UP by block number, and maintains a last used object (LUO) vector, indexed by block number, which records a last object in the UP for each block. Each time the system frees a resource, the system adds the freed resource to a tail of the UUP and promotes an oldest resource in the UUP to the UP. This approach can manage free chains in a manner that is both flaw tolerant and has relatively high performance.

Abstract: Systems and methodologies are described that facilitate automatically generating interleaved addresses during turbo decoding. An efficient recursive technique can be employed in which layers of nested loops enable the computation of a polynomial and a modular function given interleaved parameters “a” and “b” from a look up table. With the recursive technique, interleaved addresses can be generated, one interleaved address per clock cycle which can maintain turbo decoding performance.

Abstract: An address generation apparatus for a quadratic permutation polynomial (QPP) interleaver is provided. It comprises a basic recursive unit, and L recursive units represented by first recursive unit up to Lth recursive units. The apparatus inputs a plurality of configurable parameters according to a QPP function ?(i)=(f1i+f2i2) mod k, generates a plurality of interleaver addresses in serial via the basic recursive unit, and generates L groups of corresponding interleaver addresses via the first up to the Lth recursive units, wherein ?(i) is the i-th interleaver address generated by the apparatus, f1 and f2 are QPP coefficients, and k is information block length of an input sequence, 0?i?k?1.

Abstract: A burst address generator includes a burst bit counter for receiving at least one burst bit, and increasing or decreasing the at least one burst bit, a burst bit splitter for receiving the increased or decreased at least one burst bit from the burst bit counter, and dividing the increased or decreased at least one burst bit into an X burst bit and a Y burst bit, and a selector for receiving an X address, a Y address, the X burst bit, and the Y burst bit, and generating an X burst address based on the X address and the X burst bit and a Y burst address based on the Y address and the Y burst bit.

Abstract: A data storage system is disclosed comprising a non-volatile memory and a first interface operable to receive a write command from a host, the write command comprising a host write data block having a host logical block size. A block mapping bridge divides the host write data block into a plurality of transfer data blocks, wherein each transfer data block having a device logical block size smaller than the host logical block size. The transfer data blocks are transmitted through a second interface to control circuitry that accumulates the transfer data blocks into a physical data block having a device physical block size equal to a first integer multiple of the device logical block size, wherein the host logical block size is a second integer multiple of the device physical block size. The physical data block is then written to the non-volatile memory.

Abstract: An address generation system and method is provided for internally storing and thereafter producing an address to be sent to a memory device. The address that is stored need not be sent from an external address bus at each clock cycle, but the processing can remain internal to the memory device. The burst-block starting address can be stored in the mirror register and output from a selector circuit, such as a multiplexer, when that address is chosen. Otherwise, the multiplexer can simply perform its normal operation of selecting between an address pointed to by a counter, the external address, or the incremented counter output, based on the state of the external counter control signals. The system includes a mirror register, a counter, and a multiplexer that selects either the mirror register stored address or the internally processed address.

Abstract: A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.

Abstract: Circuit, method, and computer program for reordering data units of a data block in accordance with a first pre-determined function. The method includes, for each data unit of the data block—(i) generating an address corresponding to a memory location of a single-port memory module into which the data unit is to be stored, and (ii) storing the data unit in the memory location based on the address generated for the data unit. Each address is generated in accordance with the first pre-determined function, and each memory location of the single-port memory has a different delay associated with the memory location. The method further includes reading each data unit out of the single-port memory in accordance with the first pre-determined function, wherein data units of the data block are reordered based on each different delay associated with each memory location.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: A network device determines the presence of the pre-specified string in a message based on a sequence matching rule. A sequence represents non-contiguous portions of the message. A combination of content addressable memory, programmable processing units, and the programmable control unit may determine the presence of the pre-specified string in the message by comparing the non-contiguous portions of the message. Such an approach may reduce the computational resources required for searching the pre-specified string in the message.

Abstract: A method for generating addresses for a processor is provided. The addresses are for use by an application that may be executed by the processor. The application comprises a plurality of instructions, and each instruction comprises at least one line. The method includes storing a plurality of predetermined addresses and, for each line of each instruction, generating at least one address for the processor based on the predetermined addresses.

Abstract: A table-based driving circuit for displays that switches between a normal operational mode and a read table block mode. The driving circuit comprises an address sequencer and a memory. The memory comprises the full table of individual sequences, such as interlacing or color-sequential sequence. In the read table mode, the next upcoming addresses are read, i.e. are downloaded, from the memory into an address table register in the address sequencer. In the normal operational mode, the address sequencer generates the addresses for the video data to be stored in the memory or to be displayed.

Abstract: A method of reading a group of memory words from an integrated circuit memory of a contactless tag, comprising the sending by a remote interrogation unit to the contactless tag of a specific command for reading the group of memory words from a given start address, the initialization of an address counter for the contactless tag to the value of the given start address, and the sending by the contactless tag of the memory word at the start address, as well as an iterative process comprising in succession a first step of sending by the remote interrogation unit to the contactless tag of an incrementation marker recognizable by the contactless tag, a second step of incrementation of the address counter for the contactless tag in response to the incrementation marker, and a third step of sending by the contactless tag to the remote interrogation unit of a data frame comprising the memory word stored in the memory at the address pointed at by the current value of the address counter.

Abstract: Certain aspects of a method and system for combining page buffer list entries (PBLEs) to optimize caching of translated addresses are disclosed. Aspects of a method may include encoding at least two page buffer list entries in a remote direct memory access (RDMA) memory map into at least two contiguous memory locations by utilizing a remainder of a physical address corresponding to the two page buffer list entries. The first memory location of the two contiguous memory locations may comprise a base address and a contiguous length of the first page buffer list entry. The second memory location of the two contiguous memory locations may comprise a virtual address and a contiguous length of the second page buffer list entry.

Abstract: A method, system, and computer program product are provided for verifying out of order instruction address (IA) stride prefetch performance in a processor design having more than one level of cache hierarchies. Multiple instruction streams are generated and the instructions loop back to corresponding instruction addresses. The multiple instruction streams are dispatched to a processor and simulation application to process. When a particular instruction is being dispatched, the particular instruction's instruction address and operand address are recorded in the queue. The processor is monitored to determine if the processor executes fetch and prefetch commands in accordance with the simulation application. It is checked to determine if prefetch commands are issued for instructions having three or more strides.

Abstract: A memory access system for accessing a basic input output system (BIOS) program is provided. The memory access system includes a flash memory, a CPU, a peripheral component interconnect (PCI) slave, an address converter and a flash memory controller. The flash memory stores a number of BIOS data of the BIOS program, and each BIOS data corresponds to a default BIOS address and is allocated in a flash memory type BIOS address. The CPU delivers a BIOS access instruction. The BIOS access instruction corresponds to a default target address of the default BIOS addresses. After the PCI slave interprets the BIOS access instruction, the address converter converts the default target address into a flash memory type target address, which is one of the flash memory type BIOS address. The flash memory controller accesses the BIOS data allocated at the flash memory type target address accordingly.

Abstract: A storage group configured by a plurality of storage devices is configured by a plurality of storage sub-groups, and the respective storage sub-groups are configured from two or more storage devices. A sub-group storage area, which is the storage area of the respective storage sub-groups, is configured by a plurality of rows of sub-storage areas. A data set, which is configured by a plurality of data elements configuring a data unit, and a second redundancy code created on the basis of this data unit, is written to a row of sub-storage areas, a compressed redundancy code is created on the basis of two or more first redundancy codes respectively created based on two or more data units of two or more storage sub-groups, and this compressed redundancy code is written to a nonvolatile storage area that differs from the above-mentioned two or more storage sub-groups.

Abstract: A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising i) an embedded processor (EP) adapted to run the program, ii) an internal memory (IM) for storing at least a bootstrap code of this program, iii) an external memory interface (EMI) connected to the memory bus (MB), and iv) a processor bus (PB) connecting the internal memory (IM) and the external memory interface (EMI) to the embedded processor (EP). The external memory (EM) also stores, at a chosen address, an N-bit data word (C) having a value representative of its size (equal to N/8 bits) and of the Endian form of the stored program data.

Abstract: A memory comprises at least one array of memory elements, a partition of the at least one array into a plurality of sub-arrays of the memory elements, and an array configuration circuit for selectively putting the at least one array in one of two operating configurations. In a first operating configuration, the memory elements of the at least one array are coupled one to another to form a monodimensional sequentially-accessible memory, while in a second operating configuration the memory elements in each sub-array are coupled to one another so as to form an independent monodimensional sequentially-accessible memory block, a data content of any memory element of the sub-array being rotatable by shifts through the memory elements of the sub-array. A sub-array selector, responsive to a first memory address, selects one among the at least two sub-arrays according to the first memory address, and enables access to the selected sub-array.

Abstract: A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a suitably equipped processing system, the reference tables can be passed to a memory management processor which can open the appropriate memory pages to expedite the retrieval of data referenced in the execution pipeline. The disclosed method and system create such reference tables at the beginning of each routine so that the table can be passed to the memory management processor in a suitably equipped processor. Resulting object code also allows processors lacking a suitable memory management processor to skip the reference table, preserving upward compatibility.

Abstract: Certain aspects of a method and system for combining page buffer list entries (PBLEs) to optimize caching of translated addresses are disclosed. Aspects of a method may include encoding at least two page buffer list entries in a remote direct memory access (RDMA) memory map into at least two contiguous memory locations by utilizing a remainder of a physical address corresponding to the two page buffer list entries. The first memory location of the two contiguous memory locations may comprise a base address and a contiguous length of the first page buffer list entry. The second memory location of the two contiguous memory locations may comprise a virtual address and a contiguous length of the second page buffer list entry.

Abstract: A serial decoding technique may employ one or more circular shift register strings in which an input to an element of a shift register string may be gated by either an address input or the inverse of the address input. An output word line of the decoder may be driven by a respective shift register stage in the case of a single shift register string, or by a logical combination of shift register stages from respective shift register strings in the case of multiple shift register strings.

Abstract: A storage switch is disclosed that facilitates mirroring of data. For example, a target is mirrored when an identical (or almost identical) copy of the data is stored in two or more separate physical data stores. Because the various data stores may not be homogenous, they may provide for different burst sizes. To accommodate the different burst sizes, the switch provides different sequence counts for data packets sent to the different data stores that store the mirrored data.

Abstract: An apparatus and a method for enhancing digital processing implementation using non-power-of-two even count Gray coding are disclosed. The even count encoding device includes a first circuit, a second circuit, and a coding circuit. The first circuit, in one embodiment, is configured to identify a first portion of entries in a table in response to an input number. The second circuit is capable of determining a second portion of entries in the table in response to the input number, wherein the number of the first portion of entries and the number of the second portion of the entries are substantially the same. The coding circuit is operable to concatenate the second portion of the entries to the first portion of the entries to form an output table, which includes a sequence of even count integers wherein the difference between two adjacent integers is one bit position.

Abstract: Embodiments in accordance with the present invention enable a disk drive of an address system to write data normally, wherein track groups of different track widths are discretely disposed on the storage medium in a same disk drive and the dimensional relationship among physical block addresses of a sector is valid for the dimensional relationship among logical block addresses. Track groups are managed corresponding to their respective track width in a disk drive and for disposing successively in a logical block address space the respective track groups located discretely on the physical block address space.

Abstract: A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, and an instruction sequencing unit that fetches instructions for execution by the execution unit. The processor further includes an operand data structure and an address generation accelerator. The operand data structure specifies a first relationship between addresses of sequential accesses within a first address region and a second relationship between addresses of sequential accesses within a second address region. The address generation accelerator computes a first address of a first memory access in the first address region by reference to the first relationship and a second address of a second memory access in the second address region by reference to the second relationship.

Abstract: A method for automatically detecting a plurality of parameters for a NAND-Flash memory. A first step of the method may include generating a plurality of address cycles for the NAND-Flash memory. A second step may set an address number parameter of the parameters based on (i) a first number of the address cycles generated and (ii) a status signal generated by the NAND-Flash memory responsive to the address cycles. A third step generally includes generating at least one read cycle for the NAND-Flash memory after determining the address number parameter. A fourth step may set a page size parameter of the parameters based on (i) a second number of the read cycles generated and (ii) the status signal further responsive to the read cycles.