Generating A Particular Pattern/sequence Of Addresses Patents (Class 711/217)
  • Patent number: 10762452
    Abstract: A system for designing and executing control loops in a cloud environment includes a control platform implemented in the cloud environment having a data collection, analytics and events module, a policy module and an application controller module. The system includes a business process management application coupled to the control platform having a control loop designer module for designing a control loop template and a workflow engine for distributing the control loop template. The business process management application is coupled to the data collection analytics and events module of the control platform as well as the policy module in the application controller module to control platform. The control loop is activated by the control platform.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: September 1, 2020
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Rittwik Jana, Mazin Gilbert, Eric Noel, Vijay Gopalakrishnan
  • Patent number: 10747444
    Abstract: A semiconductor storage device comprises a nonvolatile semiconductor memory with memory regions, threads, and a controller. Each thread includes a buffer region in which write data from a host are stored before the write data are written to one of the memory regions, and the buffer region of each thread is different from buffer regions of the other threads. The controller receives stream data from the host, each stream data being associated with one of multiple stream identifications, allocates each stream identification to one of the threads according to priority levels assigned to the stream identifications, such that a stream identification assigned a highest priority level is allocated to a thread to which none of other stream identifications are allocated, and writes each stream data stored in the buffer regions to one of the memory regions according to stream identification of the stream data.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Motohiro Matsuyama, Yoshihisa Kojima
  • Patent number: 10713173
    Abstract: Embodiments of the present disclosure relate to a controller that includes a monitor to determine an access pattern for a range of memory of a first computer memory device, and a pre-loader to pre-load a second computer memory device with a copy of a subset of the range of memory based at least in part on the access pattern, wherein the subset includes a plurality of cache lines. In some embodiments, the controller includes a specifier and the monitor determines the access pattern based at least in part on one or more configuration elements in the specifier. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij Doshi
  • Patent number: 10644721
    Abstract: Methods and systems regarding the rapid and efficient compression and decompression of sparse data are disclosed. One method for compressing a set of data from a sparse matrix includes, evaluating a sequence of data entries from the set of data, extracting a sequence of sparse data values from the sequence, extracting a sequence of non-sparse data value run lengths from the sequence, formulating a set of row pointers from the sequence, storing the sequence of sparse data values in a first set of memory addresses, and storing the sequence of non-sparse data value run lengths in a second set of memory addresses. The set of row pointers identify a set of rows of the sparse matrix in both the first and second sets of memory addresses. Rapid decompression can be conducted using the row pointers.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: May 5, 2020
    Assignee: Tenstorrent Inc.
    Inventors: Ljubisa Bajic, Alex Cejkov, Lejla Bajic
  • Patent number: 10572404
    Abstract: A processor device is provided with hardware-implemented logic to receive an instruction including a pointer identifier and a pointer change value, the pointer identifier including a pointer address field encoded with an address of a line of memory corresponding to a location of a pointer of a particular one of the one or more cyclic buffers, one or more cushion bits, and a buffer identifier field encoded with a buffer identifier assigned to the particular cyclic buffer. The logic further enables the processor to identify that the instruction is to apply to the particular cyclic buffer based on the buffer identifier, determine that the pointer change value causes a wraparound of the pointer in the particular cyclic buffer, and fix location of the pointer in the particular cyclic buffer based on the wraparound.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventor: Moshe Maor
  • Patent number: 10276205
    Abstract: A library control device moves a desired record medium from a magazine, which is configured to load a plurality of record media into a plurality of slots, to a drive so as to read or write data. The library control device stores identifications of record media in correlation with slots loading recording media. Upon detecting a malfunction in reading or writing data with a record medium, an operator needs to extract the record medium from the magazine. At this time, the library control device rewrites the identification of a slot, which is stored in correlation with the record medium subjected to extraction, with the identification of a predetermined slot so as to move the record medium to the predetermined slot. Thus, it is possible for an operator to extract the record medium detecting a malfunction from the predetermined slot without making any mistake.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: April 30, 2019
    Assignee: NEC Platforms, Ltd.
    Inventor: Naoto Oota
  • Patent number: 10216515
    Abstract: Circuitry may be configured to identify a particular element position of a bit vector stored in a register, where a value of the element occupying the particular element position matches a first predetermined value, and determine an address value dependent upon the particular element position of the bit vector and a base address. The circuitry may be further configured to load data from a memory dependent upon the address value.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: February 26, 2019
    Assignee: Oracle International Corporation
    Inventors: Erik Schlanger, Charles Roth, Daniel Fowler
  • Patent number: 10152352
    Abstract: Devices, systems and methods are provided for writing, by a plurality of computing resources, to contiguous memory addresses of memory that supports random access, without having to specify actual write addresses of the memory.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: December 11, 2018
    Assignee: Friday Harbor LLC
    Inventors: Andy White, Doug Meyer
  • Patent number: 10073780
    Abstract: Systems and methods for tracking addresses stored in non-home locations in a cache. A method includes determining if an address that is to be stored in a cache is to be stored in a non-home location, determining if a directory has a location available for storing an identifier of the non-home location and if one or more locations of the directory are available for storing an identifier of the non-home location, storing an identifier of the non-home location in one of the one or more locations of the directory. The method further includes invalidating a non-home location in the cache that corresponds to one of the one or more locations of the directory, if none of the one or more locations of the directory are available for storing an identifier of the non-home location, and storing an identifier of the non-home location in the one of the one or more locations.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventor: Karthikeyan Avudaiyappan
  • Patent number: 10073781
    Abstract: Systems and methods for invalidating a way of a directory for non-home locations (DNHL) set that stores an identifier of a home location of an address is disclosed. As a part of a method, a request to store data in a location of a special cache that is being tracked by the way of the DNHL set is accessed, it is determined if an address stored in the location of the special cache is stored in a non-home location, a DNHL set is identified that tracks the location of the special cache if the address is not stored in a non-home location, and a set and way of the location of the special cache is compared with a set and way identifier stored in each way of the DNHL set. The way of the DNHL set that stores a matching set and way identifier is invalidated.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventor: Karthikeyan Avudaiyappan
  • Patent number: 10013253
    Abstract: An apparatus and method for performing a vector bit reversal. For example, one embodiment of a processor comprises: a source vector register to store a plurality of source bit groups, wherein a size for the bit groups is to be specified in an immediate of an instruction; vector bit reversal logic to determine a bit group size from the immediate and to responsively reverse positions of contiguous bit groups within the source vector register to generate a set of reversed bit groups; and a destination vector register to store the reversed bit groups.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Jesus Corbal, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Mark J. Charney
  • Patent number: 9886197
    Abstract: A method for operating a memory system includes detecting a size of a data requested by a host, generating a first data that represents the size of the requested data and a second data that represents a remaining empty space other than a space for the requested data in a first region having a unit size of data storage in a memory device when the size of the requested data is smaller than the first region and the request is to write the requested data into the memory device, and storing the first data and the second data in the memory device along with the requested data.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: February 6, 2018
    Assignee: SK Hynix Inc.
    Inventor: Dong-Gun Kim
  • Patent number: 9852814
    Abstract: A rupture control device may include an address control circuit configured to generate a rupture address in response to a first rupture command signal, a rupture mask signal and an external address, wherein the rupture address is generated according to whether the rupture mask signal is activated, and wherein an address and fuse data are compared, and a rupture mask signal indicating whether a fuse is ruptured is determined. Further, a fuse array configured to perform a rupture operation in response to the rupture address when a rupture enable signal is activated, and output the fuse data in response to a read enable signal.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: December 26, 2017
    Assignee: SK hynix Inc.
    Inventor: Kwi Dong Kim
  • Patent number: 9785437
    Abstract: An apparatus and method for performing a vector bit reversal and crossing. For example, one embodiment of a processor comprises: a first source vector register to store a first plurality of source bit groups, wherein a size for the bit groups is to be specified in an immediate of an instruction; a second source vector to store a second plurality of source bit groups; vector bit reversal and crossing logic to determine a bit group size from the immediate and to responsively reverse positions of contiguous bit groups within the first source vector register to generate a set of reversed bit groups, wherein the vector bit reversal and crossing logic is to additionally interleave the set of reversed bit groups with the second plurality of bit groups; and a destination vector register to store the reversed bit groups interleaved with the first plurality of bit groups.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Jesus Corbal San Adrian, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Mark J. Charney
  • Patent number: 9519278
    Abstract: A method performed by a control unit in an array of multiple self-addressable control units arranged in at least two dimensions involves obtaining information to be used to determine a self-address, determining a self-address value based upon the information, storing the determined self-address value, based upon the self-address value, specifying first data to be provided to a next self-addressable control unit in a first group of self-addressable control units for a first dimension of the array, providing the first data to the next self-addressable control unit in the first group, based upon the self-address value, specifying second data to be provided to a different self-addressable control unit in a second group of self-addressable control units for a second dimension of the array different from the first dimension of the array, and providing the second data to the different self-addressable control unit in the second group.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: December 13, 2016
    Inventor: Richard J. Petrocy
  • Patent number: 9355146
    Abstract: Embodiments of the present invention provide a database processing system for efficient partitioning of a database table with column-major layout for executing one or more join operations. One embodiment comprises a method for partitioning a database table with column-major layout, partitioning only the join-columns by limiting the partitions by size and number, executing one or more join operations for joining the partitioned columns, and optionally de-partitioning the join result to the original order by sequentially writing and randomly reading table values using P cursors.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 31, 2016
    Assignee: International Business Machines Corporation
    Inventors: Stefan Arndt, Gopi K. Attaluri, Ronald J. Barber, Guy M. Lohman, Lin Qiao, Vijayshankar Raman, Eugene J. Shekita, Richard S. Sidle
  • Patent number: 9268597
    Abstract: One example method includes identifying synchronous code including instructions specifying a computing operation to be performed on a set of data; transforming the synchronous code into a pipeline application including one or more pipeline objects; identifying a first input data set on which to execute the pipeline application; executing the pipeline application on a first input data set to produce a first output data set; after executing the pipeline application on the first input data set, identifying a second input data set on which to execute the pipeline application; determining a set of differences between the first input data set and second input data set; and executing the pipeline application on the set of differences to produce a second output data set.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: February 23, 2016
    Assignee: Google Inc.
    Inventors: Robert Bradshaw, Craig D. Chambers, Ezra Cooper, Ashish Raniwala, Frances J. Perry
  • Patent number: 9262162
    Abstract: A register file is provided. The register file includes a plurality of registers configured to form at least one register cluster, each of the registers being configured to have a virtual index defined for each cluster and a physical index defined for each register, and an index converting unit configured to convert the virtual index to the physical index.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: February 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bernhard Egger, Dong-Hoon Yoo, Won-Sub Kim
  • Patent number: 9257159
    Abstract: A method of operation within a memory device is disclosed. The method comprises receiving address information and corresponding enable information in association with a memory access request. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and the enable information includes first and second enable values that correspond respectively to first and second storage locations within the row of storage cells. The method involves selectively transferring data between the first and second storage locations and sense amplifier circuitry according to states of the first and second enable values. This includes transferring data between the first storage location and the sense amplifier circuitry if the first enable value is in an enable state and transferring data between the second storage location and the sense amplifier circuitry if the second enable value is in the enable state.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: February 9, 2016
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, Craig E. Hampel
  • Patent number: 9185046
    Abstract: A network device includes multiple packet processing engines implemented in parallel with one another. A spraying component distributes incoming packets to the packet processing engines using a spraying technique that load balances the packet processing engines. In particular, the spraying component distributes the incoming packets based on queue lengths associated with the packet processing engines and based on a random component. In one implementation, the random component is a random selection from all the candidate processing engines. In another implementation, the random component is a weighted random selection in which the weights are inversely proportional to the queue lengths.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: November 10, 2015
    Assignee: Juniper Networks, Inc.
    Inventors: Dennis C. Ferguson, Chi-Chung Chen, Thomas M. Skibo
  • Patent number: 9165493
    Abstract: A video-rendering chip performs gain correction on received display input, based on a display temperature, to produce output values that are shown on the display. The video-rendering chip includes multipliers, a microprocessor, and a memory. The microprocessor receives a display temperature from a sensor, determines gain correction coefficients that correspond to the display temperature, and provides the correction coefficients to the multipliers. The multipliers then multiply the display input by the correction coefficients to produce the output values. The microprocessor may determine the correction coefficients utilizing a lookup table or a correction coefficient formula stored in the memory. The microprocessor may receive an updated display temperature periodically and may determine new correction coefficients that correspond to the updated display temperature. The microprocessor may receive updated display temperatures at fixed periods or at varying periods based on the previous display temperature.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: October 20, 2015
    Assignee: Apple Inc.
    Inventors: Gabriel G. Marcu, David Lum, Wei Chen
  • Patent number: 9106857
    Abstract: A system and method for limiting fixed pattern noise (FPN) in a time delay and integration (TDI) mode of operation of a complementary metal oxide semiconductor (CMOS) imaging device is disclosed. The system and method provide for each line time, selecting a pixel for each column of photosensitive elements in the along track direction to capture dark information such that the selected pixel does not correspond to a portion of a scene that was previously selected to capture dark information in a current TDI period. The dark information for the selected pixels is captured and summed for each column of photosensitive elements. This sum is then used during a next TDI time period to subtract FPN effects from the output of the corresponding column. This allows the dark sum information to be constantly updated while the image sensor is in use while only decreasing the responsitivity by (N?1)/N relative to an N pixel column of a traditional TDI operation.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: August 11, 2015
    Assignee: Teledyne DALSA, Inc.
    Inventor: Naser Faramarzpour
  • Patent number: 9092328
    Abstract: A terminal and a method extend a storage space. The terminal includes a contents receiver, an interface, an external memory measure unit, a store determining unit, and a transmission controller. The contents receiver receives contents via a network. The interface accesses at least one external memory. The external memory measure unit measures at least one of a speed of the interface, an available capacity and a use history of the external memory accessed via the interface. The store determining unit determines whether to store the contents in the external memory based on a value measured by the external memory measure unit. The transmission controller controls to transmit the contents to the external memory via the interface when it is determined that the contents are stored in the external memory.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 28, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-Seob Kang, Woo-Jin Park, Hun-Je Yeon, Seong-Il Hahm
  • Patent number: 9032184
    Abstract: A method, apparatus and a data storage device are provided for implementing drive list mode for read and write transfers on a recordable surface of a storage device. Drive List mode provides a queue in a linked list to chain together multiple independent transfers on a single track. The multiple drive independent transfers include at least one of sequential transfers, near-sequential transfers, and random transfers on the single track. A drive list mode transfer of multiple independent transfers on the single track is enabled in one disk revolution, and requiring a single hardware setup for the drive list mode transfer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 12, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Thomas James Despins, Christopher Scott Dudley, Christopher Scott Taylor, Shad Henry Thorstenson, Anthony Edwin Welter
  • Patent number: 9003165
    Abstract: A system in accordance with the invention may include a data memory storing a multi-dimensional (e.g., a two-dimensional) data structure. An address generation unit is provided to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate real addresses by moving across the multi-dimensional data structure between pairs of end points. The pairs of end points (as well as parameters such as the step size between the end points) may be pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. A processor, such as a vector processor, may be configured to access (e.g., read or write data to) the data structure at the real addresses calculated by the address generation unit.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: April 7, 2015
    Inventors: Shlomo Selim Rakib, Marc Schaub
  • Patent number: 8966180
    Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Daehyun Kim, Christopher J. Hughes, Yen-Kuang Chen, Partha Kundu
  • Patent number: 8954674
    Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: February 10, 2015
    Assignee: Intel Corporation
    Inventors: Daehyun Kim, Christopher J. Hughes, Yen-Kuang Chen, Partha Kundu
  • Patent number: 8929829
    Abstract: A data movement controller (20) for controlling the movement between a shared data store (18) and a local data store (16) such that the data can be used by a plurality of parallel data processing elements is described. The data movement controller (20) comprises a set of data registers (56, 58, 60) which, in use, are loaded with different data parameters (57, 61, 62) to define a plurality of different ways in which data is transferred between the shared data store (18) and a set of processing elements (12). The data parameters (57, 61, 62) define a set of time delays for transferring portions of the data to predefined ones of the plurality of processing elements (12) and the type of overall data transfer that is to be carried out.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: January 6, 2015
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventor: Martin Whitaker
  • Patent number: 8930547
    Abstract: Techniques for achieving storage and network isolation in a cloud environment are presented. A single Internet Protocol (IP) address is presented to multiple storage tenants that use storage in a cloud environment. When each tenant accesses the IP address, a specific identity of the tenant is resolved and the storage stack for that tenant is sent to the tenant's storage machine having the tenant's storage. The tenant is directly connected to its tenant storage machine thereafter.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: January 6, 2015
    Assignee: CloudByte, Inc.
    Inventors: Umasankar Mukkara, Felix Xavier
  • Patent number: 8923045
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a first block of data is written to a group of memory cells at a first memory location in single-level cell (SLC) mode. The first block of data is copied from the first memory location to a group of memory cells at a second memory location to provide a backup copy of the first block of data during a protected mode of operation. A second block of data is subsequently overwritten to the group of memory cells at the first memory location so that the first memory location stores both the first and second blocks of data in multi-level cell (MLC) mode.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: December 30, 2014
    Assignee: Seagate technology LLC
    Inventors: Ryan James Goss, Mark Allen Gaertner, David Scott Seekins
  • Patent number: 8925074
    Abstract: Incoming files are examined to detect abnormal files. The incoming files may be examined for a weak file structure, such as a weak file format structure or a weak file data structure, to detect abnormal files. A weak file structure includes file structures that do not conform to the file format of the file yet still loadable by a file loader of the file format. The incoming files may also be examined for suspicious loading in memory to detect abnormal files.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: December 30, 2014
    Assignee: Trend Micro Incorporated
    Inventor: Chik-Kun Ho
  • Patent number: 8918616
    Abstract: The subject disclosure relates to analyzing memory allocations for one or more computer-implemented processes. In particular, in conjunction with employing tags for tracking memory allocation commands, currently allocated memory can be examined for various characteristics of inefficient memory use. For example, as memory is initially allocated, a predetermined bit pattern can be written to the newly allocated memory. Thus, detection of the predetermined bit pattern can be indicative of wasted memory use. Moreover, additional features can be provided to both analyze data and present views associated with that analysis relating to identification of memory fragmentation, over-allocation, sparse memory use, duplication of allocations, multiple module loads, and so forth.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: December 23, 2014
    Assignee: Microsoft Corporation
    Inventor: Calvin Hsia
  • Patent number: 8880848
    Abstract: A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Yasuyuki Ninomiya
  • Patent number: 8881107
    Abstract: Memory leak detection can be automated by assigning and recording an increasing sequence number to each memory allocation requested by an action. Call stacks associated with the action are also recorded. Several repetitions of the action can be executed. Allocations that occur in each action and that have similar or matching callstacks are defined as leaks. Allocations that do not have matches can be ignored.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: November 4, 2014
    Assignee: Microsoft Corporation
    Inventors: Benjamin W. Bradley, Calvin Hsia
  • Patent number: 8874858
    Abstract: A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: October 28, 2014
    Assignee: NXP, B.V.
    Inventor: Nur Engin
  • Patent number: 8843699
    Abstract: In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: September 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Moon Cheon, Seon-Taek Kim, Chan-Ik Park, Sung-up Choi
  • Patent number: 8831229
    Abstract: A key transport method for transporting a key from a buffer memory to an encryption/decryption unit is provided. The method includes logically dividing bits of the key into key segments, wherein each of the key segments has a start position and a segment length. The method also includes setting a transmission length belonging to each of key segments based on the start positions and the segment lengths of the key segments; assigning a transmission bit stream belonging to each of the key segments from the bits of the key according to the start positions and the transmission lengths of the key segments; determining a transmission sequence; and sending the start position, the segment length and the transmission bit stream belonging to each of the key segments to the encryption/decryption unit from the buffer memory based on the transmission sequence. Accordingly, the method can transport the key safely.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: September 9, 2014
    Assignee: Phison Electronics Corp.
    Inventor: Ching-Wen Chang
  • Patent number: 8832385
    Abstract: Read messages are grouped by a plurality of unique sequence identifications (IDs), where each of the sequence IDs corresponds to a specific read sequence, consisting of all read and read-ahead requests related to a specific storage segment that is being read sequentially by a thread of execution in a client application. The storage system uses the sequence id value in order to identify and filter read-ahead messages that are obsolete when received by the storage system, as the client application has already moved to read a different storage segment. Basically, a message is discarded when its sequence id value is less recent than the most recent value already seen by the storage system. The sequence IDs are used by the storage system to determine corresponding read-ahead data to be loaded into a read-ahead cache.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Lior Aronovich, Konstantin Mushkin, Oded Sonin
  • Patent number: 8826023
    Abstract: Various methods and systems for securing access to hash-based storage systems are disclosed. One method involves receiving information to be stored in a storage system from a storage system client and then generating a key. The key identifies the information to be stored. The value of the key is dependent upon a secret value, which is associated with the storage system. The key is generated, at least in part, by applying a hash algorithm to the information to be stored. The key can then be returned the key to the storage system client. The storage system client can then use the key to retrieve the stored information.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 2, 2014
    Assignee: Symantec Operating Corporation
    Inventor: Craig K. Harmer
  • Patent number: 8799574
    Abstract: A method for installing linked MIFARE applications (TK1-A, TK1-B, TK1-C) in a MIFARE memory (MM) being configured as a MIFARE Classic card or an emulated MIFARE Classic memory comprises storing the first linked MIFARE application (TK1-A) in a first free sector of the MIFARE memory, storing the second linked MIFARE application (TK1-B) in a second free sector of the MIFARE memory and writing link information (LK) indicating this second sector in a link information memory location of the first sector where first linked MIFARE application (TK1-A) has been stored, and repeating the steps of storing linked MIFARE applications and writing link information (LK) until the last linked MIFARE application (TK1-C) has been stored.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: August 5, 2014
    Assignee: NXP, B.V.
    Inventor: Alexandre Corda
  • Patent number: 8799750
    Abstract: A convolutional interleaver uses local memory of a first IC in combination with burst-type memory of a second IC. When a burst of data is read from memory of the second IC, one data value is provided to a data output and the remaining values are temporarily stored in local memory. After the memory of the second IC is initially filled, burst WRITE and burst READ operations provide efficient data transmission between the ICs.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: August 5, 2014
    Assignee: Xilinx, Inc.
    Inventor: Hemang M. Parekh
  • Patent number: 8799367
    Abstract: The technique introduced here involves using a block address and a corresponding generation number as a “fingerprint” to uniquely identify a sequence of data within a given storage domain. Each block address has an associated generation number which indicates the number of times that data at that block address has been modified. This technique can be employed, for example, to determine whether a given storage server already has the data, and to avoid sending the data to that storage server over a network if it already has the data. It can also be employed to maintain cache coherency among multiple storage nodes.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: August 5, 2014
    Assignee: NetApp, Inc.
    Inventors: Michael N. Condict, Steven R. Kleiman
  • Patent number: 8751769
    Abstract: Techniques for efficiently generating addresses for pruned interleavers and pruned de-interleavers are described. In an aspect, a linear address may be mapped to an interleaved address for a pruned interleaver by determining the total number of invalid mappings corresponding to the linear address. The linear address may be summed with the total number of invalid mappings to obtain an intermediate address. The interleaved address for the pruned interleaver may then be determined based on a non-pruned interleaver function of the intermediate address. The pruned interleaver may be a pruned bit-reversal interleaver, a pruned Turbo interleaver composed of a bit-reversal function and a linear congruential sequence function, or some other type of interleaver. The total number of invalid mappings may be determined iteratively, and each iteration may be performed in different manners for different types of pruned interleaver.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: June 10, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Mohammad Mansour
  • Patent number: 8739274
    Abstract: A device that implements a method for performing integrated caching in a data communication network. The device is configured to receive a packet from a client over the data communication network, wherein the packet includes a request for an object. At the operating system/kernel level of the device, one or more of decryption processing of the packet, authentication and/or authorization of the client, and decompression of the request occurs prior to and integrated with caching operations. The caching operations include determining if the object resides within a cache, serving the request from the cache in response to a determination that the object is stored within the cache, and sending the request to a server in response to a determination that the object is not stored within the cache.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: May 27, 2014
    Assignee: Citrix Systems, Inc.
    Inventors: Prakash Khemani, Prabakar Sundarrajan, Lakshmi Kumar, Kailash Kailash, Ajay Soni, Rajiv Sinha, Saravanakumar Annamalaisami
  • Patent number: 8732436
    Abstract: A device for storing data includes a sequence generator configured to generate a first number sequence that is a pseudorandom number sequence, a cross-correlation unit configured to produce a second number sequence that is a cross-correlation between the first number sequence and a third number sequence, and a write and read unit configured to write the second number sequence in memory and read the second number sequence from the memory, wherein the cross-correlation unit is further configured to reconstruct the third number sequence by obtaining a cross-correlation between the first number sequence and the second number sequence read from the memory.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: May 20, 2014
    Assignee: Empire Technology Development LLC
    Inventor: Tomoaki Ueda
  • Patent number: 8732435
    Abstract: An input data stream is received for processing at an integrated circuit (IC) through multiple channels. The input data stream is interleaved and the interleaved input data stream is stored in a memory buffer associated with the IC. An addressing scheme is defined for reading and writing data samples from and to the memory buffer within the IC. The addressing scheme includes determining a current increment by analyzing a pattern associated with data samples within the memory buffer and determining the memory address for each data sample within the memory buffer using the current increment. A data sample for a frame is read from a corresponding address within the memory buffer using the addressing scheme and a subsequent data sample from the interleaved input data stream is written into the corresponding address of the memory buffer. The current increment and the addressing scheme are stored in the memory buffer.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: May 20, 2014
    Assignee: Altera Corporation
    Inventors: Shin-I Chou, Jianchuan Li
  • Patent number: 8719540
    Abstract: A system, method, and computer-readable storage medium for mapping block numbers within a region to physical locations within a storage system. Block numbers are mapped within a region according to a fractal-based space-filling curve. If the region is not a 2k by 2k square, then the region is broken up into one or more 2k by 2k squares. Any remaining sub-region is centered within a 2k by 2k square, the 2k by 2k square is numbered using a fractal-based space-filling curve, and then the sub-region is renumbered by assigning numbers based on the order of the original block numbers of the sub-region.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: May 6, 2014
    Assignee: Pure Storage, Inc.
    Inventors: Ethan Miller, John Colgrove, John Hayes, Cary Sandvig
  • Patent number: 8713285
    Abstract: An apparatus, system, and method for providing a multi-dimensional data structure and address generation unit configured to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate the real addresses by executing a series of nested loops pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. The address generation unit may receive as inputs a set of parameters defining characteristics of the nested loops such as a starting offset, number of iterations or step size for loops, data structure dimensions, or loop starting point inheritance. A vector processor may then access the multi-dimensional data structure at the real addresses calculated by the address generation unit. The multi-dimensional data structure may be stored in a buffer in a data memory.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: April 29, 2014
    Inventors: Shlomo Selim Rakib, Marc Schaub
  • Patent number: 8705533
    Abstract: A network device assigns unique encoded values, represented by mnemonics, to protocol headers supported by the network device, and defines a plurality of templates, where each template includes a set of the mnemonics. The network device also stores the plurality of templates in a template table, where the template table enables the network device to create one or more protocol headers for packets transmitted by the network device.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: April 22, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Chandrasekaran Venkatraman, Avanindra Godbole
  • Patent number: 8707132
    Abstract: An information processing apparatus comprising: a reception unit adapted to receive a packet containing first data to be stored in a storage unit, a first address indicating an address of second data held in the storage unit, and a second address indicating an address at which the first data is to be written in the storage unit; an access unit adapted to read out the second data from the storage unit based on the first address, and write the first data in the storage unit based on the second address; and a transmission unit adapted to replace the first data of the packet received by the reception unit with the second data read out by the access unit, and transmit the packet.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: April 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akio Nakagawa, Hisashi Ishikawa