Abstract: A disc control apparatus handles an even number of disc-shaped recording mediums run in rotation at a constant angular velocity and to which addresses are accorded for incrementing from an inner disc rim side or from an outer disc rim side. The disc control apparatus effectuates data accessing with the disc-shaped recording mediums in terms of a pre-set block as a unit. The control apparatus includes an accessing control unit which effectuates data accessing on the block basis by addressing from the outer disc rim side for one of the disc-shaped recording mediums of the set while effecting data accessing on the block basis by addressing from the inner disc rim side for the other disc-shaped recording medium of the set. During data recording/reproduction, one of two contiguous blocks is recorded/reproduced on the disc-shaped recording medium accessed from the outer disc rim side while the other block is recorded/reproduced on the disc-shaped recording medium accessed from the inner disc rim side.

Abstract: A method for burst transferring of data in a processing system is provided. The processing system has a data bus width of W bytes (W even) and a cache line length of L bytes (L even). The cache line has L/W banks, the lowermost bank being in an odd position and the uppermost bank being in an even position. In a request for a particular data entity, a series of addresses are issued on the address bus to fill the associated cache line. The first address is always for a particular cache bank to which the particular data entity is mapped. The remaining addresses are sequenced ascending linearly, modulo L. If the particular data entity is mapped to an even cache bank, but not to the uppermost cache bank, then L/W remaining addresses are issued, beginning with the base address of the cache bank immediately following the cache bank to which the particular data entity is mapped.

Abstract: Method for increasing data-processing speed in computer systems containing at least one microprocessor, a memory device, and a so-called cache connected to the processor, in which the cache is arranged to fetch data from the addresses in the memory device requested by the processor and then also fetches data from one or several addresses in the memory device not requested by the processor. The computer system includes a circuit called the stream-detection circuit, connected to interact with a cache such that the stream-detection circuit detects the addresses which the processor requests in the cache and registers whether the addresses requested already existed in cache. The stream-detection circuit is arranged such that it is made to detect one or several sequential series of addresses requested by the processor in the cache.

Abstract: The invention provides a read-only memory and a latching circuit wherein data held in a first memory location is used to address the next memory location, in addition to providing a synchronous portion of the code. Accordingly, the data at the next memory address is used as a succeeding address and a subsequent portion of the code. The data is organized to repeat when the data stored in the address location is equal to the starting address.

Abstract: A non-volatile memory system having a memory controller, an array of memory cells and a memory operation manager. The operation manager carries out memory program, read and erase operation upon receipt of program, read and erase instruction from the controller, typically over a system bus. The address block circuitry is provided in the manager which is capable of performing an memory operation on a single address or on multiple addresses depending upon the state of the address block circuitry as determined by the controller. Multiple addresses can be generated based upon a single address provided by the controller so that sectors of the memory can be programmed or read thereby simplifying memory operations and reducing the overhead of the memory controller.

Abstract: (The present invention discloses) a method of pre-programming a flash memory cell. According to the present invention, it makes it possible to execute a continuous programming by performing a pre-programming step of internal algorithms with a bulk program verification step not with a byte or word pre-programming step when an erasure operation of a flash memory cell using a stack gate cell is performed.

Abstract: A method for compressing a plurality of contiguous addresses for storage in a queue. The method includes recognizing that a first address of the plurality of addresses is an individual address that corresponds to a memory location that is transferred individually. A first value of a block identifier bit is associated with the first address, with the first value identifying the first address as an individual address. The first address and the first value of the block identifier bit are stored into the queue. A further address of the plurality of addresses is recognized as a block address corresponding to a plurality of contiguous data words that reside at a respective plurality of contiguous addresses, that begin with the further address, and that are transferred as a block unit. A second value of the block identifier bit is associated with the further address, the second value identifying the further address as a block address.

Abstract: An information processing system 400 includes a subsystem 402 having a processing resource 404 and a bus interface 403. An active logic mapping signal is presented to a mapping input bus interface 403. The system also includes a master processing device which is operable to write at least some bits of a starting address into bus interface 403, determine an ending address for subsystem 402 and lock subsystem 402.

Abstract: A method and hardware apparatus for data prefetching. In one embodiment, the method of the present invention comprises first calculating a local stride value by computing the value between two address references of a first load instruction. The local stride value of the first load instruction is used as a global stride value for address prefetching for a second load instruction, where the second load instruction is different from the first load instruction. An appropriate global stride value is added to a previous address value associated with a previous occurrence of the second load instruction, producing an address location for prefetching a block of data.

Abstract: The present invention relates to a modulo address generator and method thereof. The apparatus includes an adder which adds a current address value and an address increment value to generate an incremented address value. Also included is an adder/subtracter circuit which adds a data region size value to the incremented address value when the sign bit of the address increment value is negative and subtracts the data region size value from the incremented address value when the sign bit is positive in order to generate a revised address value. An output selection circuit selects either the incremented address value, when the sign bit is negative, or the revised address value, when the sign bit is positive, for comparison to a minimum address of the data region in order to generate a comparison result value.

Abstract: In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit includes a sign detector adapted to determine whether a sum of an address pointer and a precomputed comparison term is of a first state or a second state. A first adder adds an address pointer and a precomputed correction term to generate a first potential next address pointer. A second adder, operating in parallel with the first adder, adds the address pointer and a displacement to generate a second potential next address pointer. A selector adapted to select the first potential next address pointer as an output when the sign detector output and a sign bit of the displacement are different, and to select the second potential next address pointer as an output when the sign detector output and a sign bit of the displacement are the same.

Abstract: A single-instruction multiple-data (SIMD) processor (10) that incorporates features for horizontal scaling of video data. The processor (10) has a data input register (11) that is operable to store input data word in sequential locations in the data input register (11) and transfer the input data words to an array of processing elements. The processor (10) also has an output data register (16) operable to receive data output words from the array of processing elements and to output said data output words from sequential locations of said output data array. An input skip signal input to the processor causes a sequential data write operation to skip a location of the input data register while an output skip signal to the processor causes a sequential data read operation to skip a location of the output data register.

Abstract: In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing a circular buffer. The address arithmetic unit includes a first selector adapted to receive as a first input a value representative of one greater than an ending address, a second input that is a beginning address, and a select input that is the sign of a displacement for stepping through addresses in a circular buffer. The first selector is adapted to select one of its inputs as an output. A carry-save adder adapted to receive as inputs an inverted representation of the first selector output, an address pointer, and a displacement. The carry-save adder is adapted to add the inputs to produce sum bits and carry bits as outputs. A sign detector adapted to determine whether a sum of the sum bits and carry bits is greater than or equal to zero, or less than zero, and for providing an output indicative of whether the sum is greater than or equal to zero, or less than zero.

Abstract: A method of automatic address generation by units within clusters of a plurality of such units in which individual configurable elements of a unit can be addressed. It is thus possible to address the individual elements directly for reconfiguration. This is a prerequisite for being able to reconfigure parts of the unit by an external primary logic unit without having to change the entire configuration of the unit. In addition, the addresses for the individual elements of the units are automatically generated in the X and Y directions, so that the addressing scheme represents the actual arrangement of units and configurable elements. Furthermore, manual allocation of addresses is not necessary due to automatic address generation.

Abstract: An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a block size by a logical block number, to obtain the start address for a memory array read or write operation. The dedicated multiplier circuit advantageously provides very quick computation of these relatively large numbers, which typically involves a 32 bit by 16 bit multiplication. The multiplier includes a shift register initially holding the logical block number which is shifted a particular number of times, the number of shift pulses representing a value of the block length. The output of the shift register is the desired address.

Abstract: In a storage disk control apparatus, a load of a computer caused by transferring data is reduced, and a waiting time until a data transfer operation is commenced is shortened. In the disk control method for controlling a disk apparatus including a disk having a plurality of storage regions for storing data therein by way of an external apparatus external addresses produced from the external apparatus are related to internal addresses indicative of positions of the storage regions the external addresses are converted into the internal addresses related thereto, and the disk is accessed based on the internal addresses.

Abstract: A sequential memory access circuit for access to various memory units is provided. The sequential memory access circuit is coupled between an external system and at least two memory units including a RAM unit and a ROM unit. The sequential memory access circuit includes a common data pointer circuit, responsive to a reset signal, a write request signal, and a read request signal from said external system, for generating accordingly a RAM enable signal, a ROM enable signal, and a counter signal, for control of the access to the RAM unit and the ROM unit. Further, a length register is used to generate a bound control signal to said common data pointer circuit in response to the write request signal and the counter signal. A sequential access dedicated comparator is used to provide the controls for the access to the two memory units. The structure of the sequential memory access circuit allows for a small circuit layout area and a reduced delay time.

Abstract: The disclosure of the current invention describes the methods and systems for inputting and outputting to and from the large capacity memory cards which are used as external data storage and expanded random access memory.

Abstract: The invention is a system providing adaptive stream buffers using instruction-specific prefetching avoidance (ISPA). According to the invention, each time the CPU executes an instruction resulting in prefetched cache lines not being used, the instruction address is stored in a table. Subsequent instruction addresses are compared to the instruction addresses in the table, and a stream buffer is not allocated when the subsequent instruction address is found within the table.

Abstract: A method and apparatus for generating addresses. The present invention provides for fast generation of a series of addresses in an array where the series comprises a column or diagonal of the array, such as for layered ECC code words in CD-ROM. Whereas each address is computable individually using multipliers and modulo circuits, the present invention operates on the series of addresses as a whole, forming a dependence between successive addresses. The dependence is separated into multiple address indices that may be summed together for the desired address. The present invention is thus able to generate a series of addresses by accumulation processes requiring only selection of the appropriate increment value and addition to a previously stored address index value. Address generation throughput is increased with savings in layout area and power.

Abstract: An address pattern generator for testing a semiconductor device, particularly, a synchronous DRAM (SDRAM) is disclosed. The address pattern generator can switch an interleave mode and a sequential mode of address generation for a SDRAM during a test process in real time and generates column addresses for the SDRAM by a Y address generation section alone. The address generator includes an address selector that selects and outputs from a lower Y address signal, a Z address signal, and an operation mode control signal, a conversion memory that outputs data based on a conversion table, a multiplexer that selects and outputs an output from the conversion memory and the lower Y address signal in accordance with a burst length control signal.

Abstract: A memory speed testing circuit including a memory addressing circuit (11, 13, 15) for sequentially providing to the address input of the memory device a binary address A and a binary address A which is a binary 1's complement of the binary address A, wherein the binary address A is provided within a selected time interval after the provision of the binary address A when the memory device is in a read mode; a data circuit (21, 23, 24) for generating a first binary test word and a second binary test word that is a 1's complement of the first binary test word; wherein the first binary test word is input to the data port of the memory device when the binary address A is provided the address input of the memory device when the memory device is in the write mode, and wherein the second binary test word is input to the data port of the memory device when the binary address A is provided to the address input of the memory device when the memory device is in the write mode; and a comparator (25) for comparing the firs

Abstract: An address generator has a designating value storing section for storing a designating value for designating each of register sections of an offset register into an address register. The address generator also has a designating value storing section for storing a designating value for designating each of register sections of a modulo register into the address register. Each of the register sections of the offset register and each of the register sections of the modulo register are automatically designated by designating the address generator. In this address generator, a degree of freedom of addressing can be increased while an increase in hardware scale is avoided as much as possible.

Abstract: A memory design which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address generation facility built into the memory's decoding circuitry. The introduction of an internal address generation facility simplifies extraneous control of typical requesters built into a memory system. The memory design also reduces power consumed by requests which exploit the memory's internal address generation facility. Power consumption is further reduced while maintaining memory access times by selectively gating data bits vital to the memory's logic flow at an earlier stage in the memory when the gating or steering address bits are known in advance of the data arriving to that stage.

Abstract: A bridge logic takes non-burst write cycles that appear one at a time as an address followed by an associated data word on a first bus, detects consecutive addresses, and uses this information to create burst cycles on a second bus that has protocols that allow burst cycles such as a Peripheral Component Interconnect (PCI) bus.

Abstract: A data writing and reading method for a frame memory which provides a high speed data access by using a memory which is divided into a plurality of portions each of which has a plurality of banks. The frame memory stores sets of data corresponding to an image to be displayed on a screen of a display unit. A set of data is written in one of the banks of one of the frame memory portions in accordance with two-dimensional accessing. Then another set of data is written in another one of the banks of one of the frame memory portions when that one of the memory portions is next accessed. The sets of data written in the frame memory is read in accordance with one-dimensional accessing.

Abstract: A method for fault detection in microcontroller program memory includes a new move instruction. An address of program instruction data is placed in a word register and a mode register. The new address points to a new instruction in a program memory. The program instruction data is read from the program memory into an instruction register and then transferred from the instruction register to the word register and the mode register. The contents of the word register and the mode register are then written to a data memory. With the program instruction data now available in the data memory, the new instruction can be tested for data integrity and validity using, for example, fault detection mechanisms or processes. A system for fault detection to check instructions or data in the program memory for data integrity and validity in a program memory also is disclosed.

Abstract: A multimedia data encoding and decoding system capable of handling various types of data arranged in variable-size blocks. Frames of image, graphics and text data are supplied to a frame buffer. In response to an encoding command from a CPU, an MPEG encoder compresses the data from the frame buffer in accordance with the MPEG compression algorithm, and outputs to a texture buffer a variable-size data block that corresponds to the frame portion to be displayed. The size of the data block is set by the CPU, and may vary from one macroblock to, e.g., 22.times.16 macroblocks (one frame for MPEG-1). An MPEG decoder reads the variable-size data block from the texture buffer, decompresses and supplies it to a graphics engine that manipulates various type of data to create a picture to be displayed at a video monitor.

Abstract: An improved method for performing memory writes from a processor in a personal computer system is provided whereby single writes are combined into burst writes based on detection of suitable write operations in instruction code. In a preferred embodiment, the improved method is implemented in microcode. The method includes detecting multiple suitable write operations prior to the execution, collecting the data elements in a storage unit, and writing the data elements as burst write operations. Write operations that meet specific conditions for quantity of data elements to be written and specific conditions for destination address are suitable for bursting. The improved method can be implemented in existing personal computers, thereby improving system performance without requiring new software applications or a new computer board design.

Abstract: An apparatus for generating an address to increase efficiency in parallel processing in a multiprocessor system. A global address generating unit is provided within a vector unit of each of processing elements (PE) constituting a parallel computer system. An adder provided within the global address generating unit sequentially adds an increment of an address, d.sub.-- Adr.sub.-- exl, and d.sub.-- Adr.sub.-- in to an address Adr.sub.-- exl and Adr.sub.-- in, respectively. A subtracter outputs a quotient obtained by dividing d.sub.-- Adr.sub.-- exl by band width bexl as a logical PE number. Additionally, a remainder obtained as an output from a subtracter is added to Adr.sub.-- in, thereby enabling a logical in-PE address to be obtained. The logical PE number and the logical in-PE address thus obtained are converted to a real PE number and a real in-PE address. Generating a global address by hardware reduces overhead incurred by parallel operation of array data.

Abstract: An improved burst address generator that is coupled to a memory array receives as its inputs a N-bit start address and dynamically generates a burst sequence of 2.sup.N decoded addresses. The burst address generator is responsive to a mode-select signal that determines whether the burst address generator operates in a linear mode or a non-linear mode. A decoder is provided for decoding the start address. A wrap-around up-down 2.sup.N -bit shift register, coupled to the address decoder, receives the decoded start address from the address decoder and dynamically provides the proper burst address sequences in accordance to the selected mode. A start address storage element is also coupled to the shift register and the address decoder to keep track of the start address.

Abstract: A computer system having a central processing unit ("CPU"), a main memory divisible into allocable units, a secondary storage unit and an operating system for allocating the allocable units to tasks for use thereby is provided with a suspend circuit for creating an optimized compressed image of data in the main memory.

Abstract: There is provided by the present invention a mirror disk device, in which specific numbers identical to those written in disks and name of a drive used as for a master disk are recorded in a set-up memory incorporated therein, this data is compared to a specific number written in a disk to determine a master disk or to transfer data to a slave disk. In the mirror disk according to the present invention, ranges of specific numbers are discretely defined without any conflict according to switching positions of a rotary switch. A first specific number is decided within each of the ranges by a random function and then serial numbers subsequent to the first specific number are assigned as specific numbers. With this feature, it is possible to prevent effective data from being lost due to, for instance, instruction miss because of manual operation.

Abstract: A Method for increasing data-processing speed in computer systems containing at least one microprocessor (1), a memory device (3), and a cache (2,4) connected to the processor, in which the cache (2,4) is arranged to fetch data from the addresses in the memory device (3) requested by the processor (1) and then also fetches data from one or several addresses in the memory device (3) not requested by the processor (1). The computer system includes a circuit called the stream-detection circuit (5), connected to interact with a cache (2,4) such that the stream-detection circuit (5) detects the addresses which the processor (1) requests in the cache (2,4) and registers whether the addresses requested already existed in cache (2,4) . The stream-detection circuit (5) is arranged such that it is made to detect one or several sequential series of addresses requested by the processor (1) in the cache (2,4).

Abstract: An expansion module address method and apparatus for a Programmable Logic Controller (PLC) is taught. Briefly stated, a PLC base unit sends an address to an expansion module or modules attached thereto. Each expansion module takes the address number it receives and considers it to be its own address number. Unless the number presented to it is a zero, the expansion module decrements the number and passes it onto the next module. Thereby each module knows its own address. Each expansion module has contained therein a plurality of address and data lines which are common to all modules with the exception of one address line which is interrupted by each module circuitry, which is used to decrement the address number and then passes it along the interrupted address line to the next module.

Abstract: A digital signal processor includes first and second counters which increment from each initial address value in first and second address areas synchronous with first and second sampling clock signals, an address generating circuit which generates a first address number in the above first address area according to a counter value in the above first counter and generates a second address number in the above second address area according to a counter value in the above second counter, a data memory which stores information signals supplied synchronous with the above first and second sampling clock signals in the first and second address numbers generated by the above address generating circuit readably and an arithmetic operating circuit which performs arithmetic operation of information signals stored in the above data memory.

Abstract: Memory control circuitry is provided which includes circuitry for generating a sequence of gray code values. Counter circuitry is coupled to the gray code circuitry and controls the duration of assertion of each of the generated gray code values. Bus circuitry is also coupled to the gray code circuitry for transmitting the gray code values generated by circuitry. Programmable logic array circuitry is also coupled to the bus circuitry for transmitting, receiving and decoding each of the gray code values and providing at least one memory control signal in response.

Abstract: Data storage apparatus comprises: a memory having a plurality of addressable memory locations for storage of data items and memory address input means for receiving addresses of locations to be accessed; main input means for receiving an input address corresponding to a memory location; a counter for changing a count in response to a clock signal; address adjustment means for combining the count with an input address to generate an adjusted address corresponding to a memory location and supplying the adjusted address to the memory address input means; and means for accessing the memory location at the address supplied to the memory address input means. Also provided is a data storage method, and data processing systems including the data storage systems.

Abstract: A memory control circuit improves the read speed of a program memory stored in a ROM. The memory control circuit includes a memory divided into four blocks, an address translation circuit for providing address 4N+1 to blocks 0 and 1 only when the required read address is 4N+2 or 4N+3, a set of latch circuits for latching data read from each of the blocks, and a selector circuit for selecting necessary data from among the latched data and outputting it to a data bus. Accordingly, three or more blocks of memory are made readable in every latched operation.

Abstract: Data block identification within a processor 100 may be accomplished when the processor 100 receives an interrupt while performing a main set of operational codes. Upon receiving the interrupt, the processor 100 determines whether the interrupt is of a fast interrupt type. When the interrupt if of a fast interrupt type, the processor executes the operational codes identified by the interrupt without having to flag the main set of operational codes. Upon completion of the fast interrupt, the processor 100 resumes performing the main set of operational codes. In addition to performing the fast interrupt, the processor 100 contemporaneously performs a data block identification routine. When the data block identification routine identifies a data block, the main set of operational codes is interrupted to perform a data block service routine. The processor 100 includes an address generation unit 102 and a peripheral address generation unit 104.