Abstract: The present disclosure concerns a method and apparatus for accessing a memory device, such as a dynamic random access memory (DRAM). The DRAM has a plurality of rows, wherein each row has a plurality of DRAM paragraphs comprised of a plurality of contiguous columns. A linear shift register (LSR) translates a plurality of logical addresses to corresponding physical address locations in the DRAM. Each translated physical address is comprised of a row address and a column address. A physical address, including the row and column addresses, is accessed from the LSR. To access the DRAM paragraph at the accessed physical address, the row in the DRAM at the accessed row address location is strobed to setup and precharge the row. Following, all columns in the DRAM paragraph at the accessed physical address are strobed. After strobing the columns in a DRAM paragraph, the next physical address in the LSR, including the next row and column addresses, is accessed.

Abstract: An improved apparatus and method for providing addresses for accessing circular memory buffers is provided. An apparatus comprised of a first feedback circuit, a second feedback circuit, a beginning address register, an ending address register, and a comparator circuit. A control circuit is also provided. The beginning and ending address registers preferably include the beginning and ending addresses respectively of a circular memory buffer. The first feedback circuit is comprised of a first register, a first phase delay register, a first adder, a first displacement register, and a first multiplexer. The second feedback circuit is preferably comprised of a second register, a second phase delay register, a second adder, and a second displacement register.

Abstract: A superscalar microprocessor implements a microcode instruction unit that patches existing microcode instructions with substitute microcode instructions. A flag bit is associated with each line of microcode in the microcode instruction unit. If the flag bit is asserted, the microcode instruction unit branches to a patch microcode routine that causes a substitute microcode instruction stored in external RAM to be loaded into patch data registers. The transfer of the substitute microcode instruction to the patch data registers is accomplished using data transfer procedures. The microcode instruction unit then dispatches the substitute instructions stored in the patch data registers and the substitute instruction is executed by a functional unit in place of the existing microcode instruction.

Abstract: A computing device (10) includes a processor (14) coupled to a memory interface (28). The memory interface (28) supports access to a variety of memories (12) using at least two different data lengths. The memory interface (28) includes an address register (50, 52) for receiving addressing information to access the memory (12). A mode bit (80) and a high/low bit (82) in the address register (50, 52) determine the different operating modes of the memory interface (28).

Abstract: Data is read from a first-in-first-out (FIFO) queue. A first condition flag is generated which indicates whether a read transaction of a first transaction size may be performed. When a write address for the FIFO queue is greater than a read address for the FIFO queue, the first condition flag is set to true when the read address plus the first transaction size is less than or equal to the write address. When the write address for the FIFO queue is less than the read address for the FIFO queue, the first condition flag is set to true when the read address plus the first transaction size is less than the write address plus a maximum depth of the FIFO queue. A first read transaction of the first transaction size from the FIFO queue is performed only when the first condition flag is true.

Abstract: A programmable logic array integrated circuit device has a relatively large block of programmable memory cells in addition to the usual programmable logic modules and the usual programmable interconnection conductor network. In order to simplify the circuitry associated with the large block, and especially the circuitry for addressing that block during programming and/or verification of the device, the address decoder that is normally used to address the block during use of the device to perform logic is also used during programming and/or verification. During programming and/or verification a counter or other similar coded address signal generating circuitry is used to supply address information to the decoder.

Abstract: An optimized translation lookaside buffer (TLB) utilizes a least-recently-used algorithm for determining the replacement of virtual-to-physical memory translation entries. The TLB is faster and requires less chip area for fabrication. In addition to speed and size, the TLB is also optimized since many characteristics of the TLB may be changed without significantly changing the overall layout of the TLB. A TLB generating program may thus be used as a design aid. The translation lookaside buffer includes a level decoding circuit which allows masking of a variable number of the bits of a virtual address when it is compared to values stored within the TLB. The masking technique may be used for indicating a TLB hit or miss of a virtual address to be translated, and may also be used for invalidating selected entries within the TLB.

Abstract: The present invention is a method and circuit for providing a burst address counter with a fast burst-done signal. In a preferred embodiment, a synchronous memory device includes a counter for producing a sequence of burst addresses, based on an external address. In addition, the counter drives the burst-done signal to indicate completion of the burst sequence. The counter includes a register for receiving the external address, an incrementor for advancing the external address to produce the next address of the sequence of burst addresses, a minus-two subtractor for determining a second-to-last burst address of the burst sequence, and a comparator. By utilizing the minus-two subtractor, the comparator can determine the end of the burst sequence earlier than conventional counters. This is because the minus-two subtractor determines the next-to-last address of the sequence, which allows the comparator to start asserting the burst-done signal at an earlier time.

Abstract: A method for extracting a PE number and offset from an array index by recursive centrifuging. According to one aspect of the present invention, a processing element number is assigned to each processing element, a local memory address is assigned to each memory location and a linearized index is assigned to each array element in a multidimensional array. The processing element number of the processing element in which a particular array element is stored is computed as a function of a linearized index associated with the array element and a mask word determined from the distribution specification associated with the array. The mask word is generated from the distribution specification and applied to a linearized index associated with a particular array element to obtain processing element number bits and local offset bits.

Abstract: In order to precisely measure the speed of memory unit, the memory unit stores at least one bit data at a predetermined bit position at each memory word such that the logical value of the one bit data changes alternately in order of memory address. An address increment circuit, which is provided in a module including the memory unit, successively generates memory addresses which are applied to the memory. The address increment circuit increments a memory address in response to the output of the memory. The memory speed between two consecutive memory outputs is detected by measuring a pulse width of a pulse signal outputted from the memory unit. Thus, a relatively large delay otherwise caused at a buffer amplifier can effectively be compensated.

Abstract: An integrated circuit (1720) includes a dual-port memory (3330.1) having a first memory port (Port A) and a second memory port (Port B), a bus interface block (5010) including bus master (5016) and bus slave circuitry (5018), and a byte-channeling block (5310) coupled between the first memory port (Port A) and the bus interface block (5010) operable to convert non-aligned data addresses into aligned data. Advantageously, this invention includes a single bus master serving all application hardware. This relieves the host of the extra burden of communicating to slave circuits, reducing host I/O MIPS significantly. The digital signal processor with an ASIC wrapper of this invention together provide super-bus-mastering to access the entire memory space in the system, including the entire virtual memory space accessible by the host processor. Other processes, systems, devices and methods are also disclosed.

Abstract: Method, system and computer program product are provided for selectively separately updating multiple system time clocks or synchronously updating the multiple system time clocks (STCs). Separate or simultaneous updating of the system time clocks is attained by selectively adjusting the addresses to the system time clocks in updatable address register fields. A first address value is provided to a first address register associated with a first STC register and a second address value is provided to a second address register associated with a second STC register. Independent updating of the first STC register and the second STC register is performed when the first address value and the second address value are different, while synchronous updating is performed when the first address value and the second address value comprise a common address value. The technique can be extrapolated to any number of clocks to be updated.

Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset.

Abstract: A shared memory controller prevents a memory area in a shared memory from becoming unusable even if an error occurs in an address for performing read/write operations. Under the control of a write control unit, each time N units of data and an address indicative of a storage location next to this data is written into the shared memory, one of the written addresses is stored in a second memory provided separately from the shared memory. Each time N addresses are read from the shared memory, an address stored in the second memory is read to detect in a detector whether or not the address is erroneous. If an error is detected, the erroneous address is discarded.

Abstract: A semiconductor memory device is provided with a determination circuit and an address adder. The determination circuit determines whether a read start address selects upper-address banks B5-B8 or lower-address banks B1-B4. When the determination circuit determines that the lower-address banks are selected, the address adder increments a column address by 1. From the upper-address banks, data are read from the columns corresponding to the read start address. From the lower-address banks, data are read from the columns that are next to the columns corresponding to the read start address. Even when the upper-address banks are designated by the read start address, the data output from the lower-address banks corresponds to the next columns. Since there is no busy time during data output, successive access is enabled and the access cycle time can be as short as possible.

Abstract: A microprocessor is configured to execute a stride instruction. In response to the stride instruction, the microprocessor performs a series of load memory operations. The address corresponding to a particular load memory operation is the sum of a stride operand of the stride instruction and the address corresponding to another load memory operation immediately preceding the particular load memory operation in the series. A base address operand specifies the address of the first load memory operation in the series, and a repetition count operand specifies the number of load memory operations in the series. The cache lines corresponding to the series of load memory operations (i.e. the cache lines storing the bytes addressed by the load memory operations) are fetched into the data cache of the microprocessor in response to the series of load memory operations.

Abstract: A parallel type of memory is divided into P sub-arrays with which there are associated column and row decoding circuits and read circuits. Circuits are used to produce and give P addresses simultaneously to the decoding circuits on the basis of a given address so as to enable the simultaneous reading of P words from a single address. Circuits receive the P information elements extracted from the P words and give them in series at an output port at a frequency greater than the reading frequency. Thus the access time to the information elements seen from the exterior of the memory is reduced.

Abstract: A method for burst transferring of data in a processing system is provided. The processing system has a data bus width of W bytes (W even) and a cache line length of L bytes (L even). The cache line has L/W banks, the lowermost bank being in an odd position and the uppermost bank being in an even position. In a request for a particular data entity, a series of addresses are issued on the address bus to fill the associated cache line. The first address is always for a particular cache bank to which the particular data entity is mapped. The remaining addresses are sequenced ascending linearly, modulo L. If the particular data entity is mapped to an even cache bank, but not to the uppermost cache bank, then L/W remaining addresses are issued, beginning with the base address of the cache bank immediately following the cache bank to which the particular data entity is mapped.

Abstract: A circuit and method for segregating address entries of memory, internal to an address translation unit, into locked and unlocked regions. The locked region is a portion of the memory that can be invalidated by a lesser number of events than the unlocked region. In one embodiment, replacement circuitry of the address translation unit may invalidate address translations only stored in the unlocked region. The replacement circuitry comprises a counter to produce a first count value upon detecting that at least a first command has been issued to the address translation unit and each entry of the memory is currently in a valid state. Also, the replacement circuitry comprises an increment controller to control the counter to produce the first count value that addresses an entry of the memory within the second address range.

Abstract: A modulo address generation circuit for generating multiple-word memory accesses for use in a computer system. The circuit includes an address pointer latch for retaining a current address pointer, an adder for receiving the current address pointer as a first input and a displacement as a second input. The adder for adding the inputs to provide an output. A comparator compares the current address pointer to an ending address of a circular buffer ignoring least significant bits thereof when the displacement is greater than one. The comparator provides an output that is a first state when the inputs are the same and an output that is a second state when the outputs are different. A control circuit is adapted to receive an indicator of the beginning address of the circular buffer, an indicator of the current address pointer, and an indicator of the ending address of the circular buffer.

Abstract: A method for compressing a plurality of contiguous addresses for storage in a queue. The method includes recognizing that a first address of the plurality of addresses is an individual address that corresponds to a memory location that is transferred individually. A first value of a block identifier bit is associated with the first address, with the first value identifying the first address as an individual address. The first address and the first value of the block identifier bit are stored into the queue. A further address of the plurality of addresses is recognized as a block address corresponding to a plurality of contiguous data words that reside at a respective plurality of contiguous addresses, that begin with the further address, and that are transferred as a block unit. A second value of the block identifier bit is associated with the further address, the second value identifying the further address as a block address.

Abstract: An information processing system 400 includes a subsystem 402 having a processing resource 404 and a bus interface 403. An active logic mapping signal is presented to a mapping input bus interface 403. The system also includes a master processing device which is operable to write at least some bits of a starting address into bus interface 403, determine an ending address for subsystem 402 and lock subsystem 402.

Abstract: A method and hardware apparatus for data prefetching. In one embodiment, the method of the present invention comprises first calculating a local stride value by computing the value between two address references of a first load instruction. The local stride value of the first load instruction is used as a global stride value for address prefetching for a second load instruction, where the second load instruction is different from the first load instruction. An appropriate global stride value is added to a previous address value associated with a previous occurrence of the second load instruction, producing an address location for prefetching a block of data.

Abstract: The present invention relates to a modulo address generator and method thereof. The apparatus includes an adder which adds a current address value and an address increment value to generate an incremented address value. Also included is an adder/subtracter circuit which adds a data region size value to the incremented address value when the sign bit of the address increment value is negative and subtracts the data region size value from the incremented address value when the sign bit is positive in order to generate a revised address value. An output selection circuit selects either the incremented address value, when the sign bit is negative, or the revised address value, when the sign bit is positive, for comparison to a minimum address of the data region in order to generate a comparison result value.

Abstract: In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit includes a sign detector adapted to determine whether a sum of an address pointer and a precomputed comparison term is of a first state or a second state. A first adder adds an address pointer and a precomputed correction term to generate a first potential next address pointer. A second adder, operating in parallel with the first adder, adds the address pointer and a displacement to generate a second potential next address pointer. A selector adapted to select the first potential next address pointer as an output when the sign detector output and a sign bit of the displacement are different, and to select the second potential next address pointer as an output when the sign detector output and a sign bit of the displacement are the same.

Abstract: In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing a circular buffer. The address arithmetic unit includes a first selector adapted to receive as a first input a value representative of one greater than an ending address, a second input that is a beginning address, and a select input that is the sign of a displacement for stepping through addresses in a circular buffer. The first selector is adapted to select one of its inputs as an output. A carry-save adder adapted to receive as inputs an inverted representation of the first selector output, an address pointer, and a displacement. The carry-save adder is adapted to add the inputs to produce sum bits and carry bits as outputs. A sign detector adapted to determine whether a sum of the sum bits and carry bits is greater than or equal to zero, or less than zero, and for providing an output indicative of whether the sum is greater than or equal to zero, or less than zero.

Abstract: A circular buffer in a system for processing audio samples wherein the buffer includes a sample window, the length of which is the length of a plurality of samples, the length of the circular buffer is a multiple of the length of the sample window, and the entire sample window is treated as a contiguous linear address space on each iteration of the processing system, that is moved through the physical multiple sample length buffer between iterations of the processing system, and is reset to the beginning every sample window number of iterations of the processing system. The circular buffer substantially reduces the number of address calculations in processing systems where every buffer position is addressed on every iteration and where circular addressing is not provided in hardware.

Abstract: In order to generate internal addresses from an external address in a burst operation in a synchronous dynamic random access memory (SDRAM), an external address is latched in response to an external clock signal. First and second control signals are generated in synchronous with the external clock signal. An internal address for a first clock cycle of a burst operation is generated from the latched external address in a sequential mode in response to the first control signal using a first transfer path. An internal address for each of a second clock cycle and subsequent clock cycles of the burst operation in the sequential mode is generated in response to a second control signal using a second transfer path such that the internal address for each of the second clock cycle and subsequent clock cycles has substantially the same delay time as that of the internal address for the first clock cycle with respect to the external clock signal.

Abstract: A method of automatic address generation by units within clusters of a plurality of such units in which individual configurable elements of a unit can be addressed. It is thus possible to address the individual elements directly for reconfiguration. This is a prerequisite for being able to reconfigure parts of the unit by an external primary logic unit without having to change the entire configuration of the unit. In addition, the addresses for the individual elements of the units are automatically generated in the X and Y directions, so that the addressing scheme represents the actual arrangement of units and configurable elements. Furthermore, manual allocation of addresses is not necessary due to automatic address generation.

Abstract: An address generating circuit of simple configuration for repeating a selected block of instructions is provided. An instruction address maintained by program counter 72 is compared to register 76 that holds the address of the end of the selected block of instructions. When the end address is detected, the program counter is loaded with a starting address of the block of instructions, which is stored in register 80. Block repeat count register 86 maintains a repeat count. Zero detection circuit 70 delays decrements of register 86 by a number of clock cycles that is equivalent to a pipeline depth for instruction prefetching of a processor connected to program counter 72. The zero detection circuit 70 outputs a loop-end control signal which controls a selector to selectively provide an incremented address or the start address to the program counter. By delaying decrements of register 86, the state of the repeat count is correctly maintained when the processor pipeline is flushed during an interrupt.

Abstract: An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a block size by a logical block number, to obtain the start address for a memory array read or write operation. The dedicated multiplier circuit advantageously provides very quick computation of these relatively large numbers, which typically involves a 32 bit by 16 bit multiplication. The multiplier includes a shift register initially holding the logical block number which is shifted a particular number of times, the number of shift pulses representing a value of the block length. The output of the shift register is the desired address.

Abstract: Methods and systems for generating alternate and zigzag address scans in a reconfigured two-dimensional map under the MPEG-1 and MPEG-2 are provided. In one embodiment, a control signal generator determines the subsequent alternate address based on the present alternate address. In another embodiment, the control signal generator determines the subsequent zigzag address based on the present zigzag address. The subsequent address is generated by incrementing, decrementing, or resetting a pair of up/down counters that are coupled to the inputs of the control signal generator.

Abstract: A method and mechanism for converting a non-contiguous subset of values in a large range, such as selected Unicode code points, into a contiguous or mostly contiguous smaller range with a perfect hash. The large range is organized into a two-dimensional bitmap matrix of pages and offsets into the pages. The bits in the matrix equal one if the value is in the subset, and zero if not. The pages are then overlaid on one another into a one-dimensional bitmap by shifting each page as necessary to avoid conflicts with values on other pages. The shift amount is recorded and used in a hash computation, wherein a value of the large range is first separated into its page number and its offset into the page. The values are then hashed into the value of the dense subset range by looking up the shift amount for the page and adding the shift amount to the offset into the page.

Abstract: A microprocessor (10) and system implementing the same is disclosed, in which stack-based register address calculation is performed in a single add cycle for instructions involving a PUSH operation. The microprocessor (10) includes a floating-point unit (FPU) (31) having a register stack (52.sub.ST) and a stack pointer (FSP), for executing floating-point instructions containing relative register addresses (REG) based upon the contents (TOP) of the stack pointer (FSP). The instructions may involve PUSH operations, in which an operand is added to the stack of operands in the register stack (52.sub.ST). Register addressing circuitry (125, 125') includes an adder (122; 122') for generating the sum of the contents (TOP) of the stack pointer (FSP) and the relative register address (REG) of the instruction, and an adder/decrementer (120) for generating the sum of the contents (TOP) of the stack pointer (FSP) and the relative register address (REG) of the instruction minus one, to account for the PUSH.

Abstract: This invention is developed to provide a computing system which can carry out a high speed access to a cache memory within one cycle even though data needed to be read is on the border of two pages. To realize the high speed computing system accessible to a split line on the border of two pages within one cycle, the computing system includes a translation lookaside buffer (TLB) which is designed to have a dual port structure, a prefetcher and a data/code cache memory which is improved for supporting the translated lookaside buffer (TLB).

Abstract: A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

Abstract: In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit includes a first selector adapted to receive as a first input a value representative of one greater than an ending address, a second input that is a beginning address, and a select input that is the sign of a displacement for stepping through addresses in a circular buffer. The first selector is adapted to select one of its inputs as an output. A first adder combines an address pointer and displacement to produce a first potential next address pointer. A second adder combines the address pointer, the displacement, and a length modified by the sign of the displacement to produce a second potential next address pointer.

Abstract: A video graphics controller (VGC) for communicating with a frame buffer memory and a display device includes a first-in, first-out (FIFO)-configured memory, a memory controller for communicating with the frame buffer memory and controlling the FIFO-configured memory, and read and write pointers for the FIFO-configured memory. A subtractor is coupled to the read and write pointers for generating a difference signal which is coupled to the memory controller, and the read pointer generates a read carrier signal which is provided to a lock detector along with an end-of-frame signal. The lock detector generates an output signal which is coupled to the memory controller in order to place the video graphics controller in a locked mode of operation if no read carry signal is generated during an inputting of an entire frame of information into the FIFO-configured memory, and in an unlocked mode of operation if a read carry signal is generated prior to the completion of the inputting of an entire frame of information.

Abstract: An address translation unit is provided for logical to physical address conversion. In particular, apparatus and method are described for receiving a logical cylinder head sector for a logical block address and converting it into a physical cylinder head sector. If a logical block address is received, it is converted to a physical block address and then the physical block address is converted into a physical cylinder head sector. If a logical cylinder head sector is first received, it is converted into a logical block address, and then the conversion takes place just as it would for an initially received logical block address.

Abstract: A sequential memory access circuit for access to various memory units is provided. The sequential memory access circuit is coupled between an external system and at least two memory units including a RAM unit and a ROM unit. The sequential memory access circuit includes a common data pointer circuit, responsive to a reset signal, a write request signal, and a read request signal from said external system, for generating accordingly a RAM enable signal, a ROM enable signal, and a counter signal, for control of the access to the RAM unit and the ROM unit. Further, a length register is used to generate a bound control signal to said common data pointer circuit in response to the write request signal and the counter signal. A sequential access dedicated comparator is used to provide the controls for the access to the two memory units. The structure of the sequential memory access circuit allows for a small circuit layout area and a reduced delay time.

Abstract: The stack pointer is used for generating the next unutilized location in the stack memory device in order to indicate where a current value in the program counter is to be written. The stack pointer also generates a directly preceding location to the next unutilized location in order to read the last value of the program counter that was written to the stack memory device. The stack pointer will select the next unutilized location in the stack memory device for a write operation and the directly preceding location to the next unutilized location in the stack memory device for a read operation. The stack pointer will further perform either a post increment or post decrement operation on the next unutilized location in the stack memory device after execution of a current instruction.

Abstract: A microprocessor is configured to execute a stride instruction. In response to the stride instruction, the microprocessor performs a series of load memory operations. The address corresponding to a particular load memory operation is the sum of a stride operand of the stride instruction and the address corresponding to another load memory operation immediately preceding the particular load memory operation in the series. A base address operand specifies the address of the first load memory operation in the series, and a repetition count operand specifies the number of load memory operations in the series. The cache lines corresponding to the series of load memory operations (i.e. the cache lines storing the bytes addressed by the load memory operations) are fetched into the data cache of the microprocessor in response to the series of load memory operations.

Abstract: A memory speed testing circuit including a memory addressing circuit (11, 13, 15) for sequentially providing to the address input of the memory device a binary address A and a binary address A which is a binary 1's complement of the binary address A, wherein the binary address A is provided within a selected time interval after the provision of the binary address A when the memory device is in a read mode; a data circuit (21, 23, 24) for generating a first binary test word and a second binary test word that is a 1's complement of the first binary test word; wherein the first binary test word is input to the data port of the memory device when the binary address A is provided the address input of the memory device when the memory device is in the write mode, and wherein the second binary test word is input to the data port of the memory device when the binary address A is provided to the address input of the memory device when the memory device is in the write mode; and a comparator (25) for comparing the firs

Abstract: A method and apparatus for generating a modulo address for accessing a circular buffer. The method and apparatus accept as inputs a length L of the circular buffer, a current address A of the circular buffer, and an offset M between the current address and the next address to be generated. The offset M may be positive or negative. During operation of the present invention, the current address A first is broken down into a base address B and an offset from the base address a. Then, in accordance with the length L and the offset M, the invention determines an absolute offset and a wrapped offset. One of these offsets is added to the base address B to generate a next address for the circular buffer. The determination of which offset to add to the base address B is made by performing one of two comparisons.

Abstract: A buffer memory controller allows to sequentially store sampled data having variable bit length. That is, rather than assigning each sampled data to a single word of the memory, the sampled data is sequentially stored head to tail so that memory space is not wasted.

Abstract: An efficient integer-division-by-an-constant method and apparatus. This integer-division-by-an-constant is useful in calculations which must be performed often and/or quickly, and where the denominator is fixed for the calculations, such as address calculations in massively parallel, distributed memory processor systems. Also described is a method and apparatus using the integer-division-by-an-constant method and apparatus, which facilitates removing power-of two restrictions on the reorganization and redistribution of data between remote and local memory blocks in a massively parallel, distributed-memory processing system. The flexible addressing scheme provided supports data organizations which vary widely depending on the processing task. In particular, a plurality of processing elements (PEs) operating in parallel within a subset of all the PEs in a massively parallel processor system, may simultaneously operate on an array data structure, the array data structure having an arbitrary size and shape.

Abstract: A memory interface apparatus includes a plurality of data memories MEMs, and address modification units AMDs and memory access units I/Fs respectively corresponding to the plurality of data memories MEMs. Each address modification unit AMD has an offset table OFT for pre-storing a plurality of offsets, reads an offset from the table OFT based on received second data D2, modifies an address indicated by a received generation number GN using the read offset, and applies a resultant address to a corresponding memory access unit I/F. Each memory access unit I/F accesses a memory MEM based on the applied address, according to a received operation code C. Each result of access is applied in parallel to an operation unit ALU, which in turn performs operation of the applied result according to an operation code C. Thus, operation processing which compounds access to a memory can be carried out, utilizing parallelism in processing sufficiently.

Abstract: A method and apparatus for causing a data line to be fetched in an order consistent with the data structure of a processor's modified little endian mode or big endian mode of operation is accomplished when the processor requests a particular word that is not currently stored in cache memory. The request includes an address of the particular word and an indication is provided as to whether the processor is operating in the modified little endian mode or the big endian mode. A memory manager, upon receiving the request, retrieves a line of data from memory (storage device) based on the address and the mode of operation. For example, when the big endian mode is used, the line of data is retrieved using a target word first ordering and when the modified little endian mode is used, the line of data is retrieved using a reverse target word first ordering.

Abstract: An improved burst address generator that is coupled to a memory array receives as its inputs a N-bit start address and dynamically generates a burst sequence of 2.sup.N decoded addresses. The burst address generator is responsive to a mode-select signal that determines whether the burst address generator operates in a linear mode or a non-linear mode. A decoder is provided for decoding the start address. A wrap-around up-down 2.sup.N -bit shift register, coupled to the address decoder, receives the decoded start address from the address decoder and dynamically provides the proper burst address sequences in accordance to the selected mode. A start address storage element is also coupled to the shift register and the address decoder to keep track of the start address.

Abstract: An apparatus for generating an address to increase efficiency in parallel processing in a multiprocessor system. A global address generating unit is provided within a vector unit of each of processing elements (PE) constituting a parallel computer system. An adder provided within the global address generating unit sequentially adds an increment of an address, d.sub.-- Adr.sub.-- exl, and d.sub.-- Adr.sub.-- in to an address Adr.sub.-- exl and Adr.sub.-- in, respectively. A subtracter outputs a quotient obtained by dividing d.sub.-- Adr.sub.-- exl by band width bexl as a logical PE number. Additionally, a remainder obtained as an output from a subtracter is added to Adr.sub.-- in, thereby enabling a logical in-PE address to be obtained. The logical PE number and the logical in-PE address thus obtained are converted to a real PE number and a real in-PE address. Generating a global address by hardware reduces overhead incurred by parallel operation of array data.