Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: A method of operating a processor (30). The method comprises a first step of fetching an instruction (20). The instruction includes an instruction opcode, a first data operand bit group corresponding to a first data operand (D1′), and a second data operand bit group corresponding to a second data operand (D2′). At least one of the first data operand and the second data operand consists of an integer number N bits (e.g., N=32). The instruction also comprises at least one immediate bit manipulation operand consisting of an integer number M bits, wherein 2M is less than the integer number N. The method further includes a second step of executing the instruction, comprising the step of manipulating a number of bits of one of the first data operand and the second data operand. Finally, the number of manipulated bits is in response to the at least one immediate bit manipulation operand, and the manipulating step is further in response to the instruction opcode.

Abstract: A hashing method and apparatus uses a hash function that can be modified in real time by a hash control code. The hash function involves the combining together of multiple bit-shifted versions of a multi-bit input to produce a transformed value from which the hash output is formed. The hash control code is used to set the number of input versions used to produce the transformed value and their respective degrees of bit-shifting. The hashing method and apparatus may be used in executing processor branch instructions where the identity of an item to be accessed occupies a search space that varies in size and degree of population between different branch instructions.

Abstract: A system and method for providing a burst sequence of data in a desired data ordering in response to a request packet. The burst sequence of data includes a plurality of data blocks and the request packet includes one or more data ordering bits which define a data ordering. The system includes one or more random access memory modules. Each random access memory module includes a memory array having a plurality of memory cells organized in an array of rows and columns, a row address decoder connected to the memory array for generating a row address which addresses one of the rows of the memory array, and a column address decoder connected to the memory array for generating a column address which addresses one of the columns of the memory array.

Abstract: A high-speed linear address generator (LAGEN) and method for generating a linear address are disclosed, which generator is operable to generate a linear address very quickly. In a preferred embodiment, the LAGEN has a parallel design, rather than a serial design, which allows the LAGEN to generate a linear address substantially faster than 1 nanosecond after receiving input operands. The LAGEN generates a linear address within a single clock cycle of a clock operating at 1 gigahertz (GHz). The LAGEN receives three 32-bit operands IMM[31:0], SRC1[31:0], and SRC2[31:0], and compresses them into two 32-bit operands. The LAGEN then sums the two operands producing a 32-bit result res[32:0]. The LAGEN allows for both 32-bit mode operation and 16-bit mode operation. In either mode of operation the lower 16 bits of the result, res[15:0], are output for the lower 16 bits of the generated linear address.

Abstract: A fast division technique is provided to calculate the address of a slot in a paged object, when the slot is located on a different page than the beginning of the object. The fast division technique employs arithmetical-logical operations of shifting and masking, that are faster than most hardware implementations of integer division and modulus, respectively. In one aspect, the use of these operations is facilitated by requiring the page size and the size of the page header to be a power of two.

Abstract: A memory channel means transferring data streams between different blocks and an internal memory means on a data chip, wherein said memory channel means comprises several memory channels. Each channel has source and destination data stream interfaces, wherein each interface is connectable to different blocks, and a flexible address generator generating source and destination addresses for the internal memory means, wherein the order of the data being transferred is changed.

Abstract: A FIFO is operated so no changes occur on an output thereof in response to (1) only one stage of the FIFO having a signal stored therein when a read command is supplied to the FIFO exclusively of a write command and/or (2) the FIFO being flushed, i.e., erased. Result (1) is achieved by decrementing a write pointer by one without changing a read pointer or by loading the write pointer with the contents of the read pointer. Result (2) is achieved by loading the write pointer with the contents of the read pointer.

Abstract: There is disclosed DTLB in a microprocessor of the present invention, comprising an adder for adding a base address and a sign-extended offset address; a comparator for judging whether or not upper side 20 bits [31:12] of the base address match the base address stored in a upper side address storage section in CAM 35, and upper side 4 bits [15:12] of the offset address match the offset address stored in the CAM; a comparator for judging whether or not a carry signal outputted from the adder and a carry signal stored in a carry storage section in the CAM are matched; and a match detector for outputting a match signal when comparison results of the comparators are matched. With lower side 12 bits of the virtual address, the judgment of match/mismatch is performed only with the carry signal. Therefore, the match/mismatch of the virtual address can be judged before the addition processing in the adder is completed.

Abstract: The Intelligent DMA Controller (IDMAC) significantly reduces system latency by replacing one or more layers of software with hardware. The IDMAC uses controlwise and datawise intelligence. The controlwise intelligence of the IDMAC is given specific knowledge of the structure of certain pieces of memory or hardware registers, (e.g. parameter blocks), used for Inter Process Communication. This specific knowledge can be imparted during the design phase of the IDMAC, or dynamically provided during its operation as system requirements dictate. The IDMAC achieves its DMA controlwise intelligence by understanding parameter blocks (PBs). The IDMAC reads the structure of the PB from memory directly, gets all of its PB parameters directly from memory, dereferencing as required, and then begins transferring data between the source and destination as instructed by the PB(s). Examples of PB parameters are source address, destination address, transfer length, and data intelligence opcode.

Abstract: A computer system that simulates a memory stack in a non-general purpose register set in the computer's CPU. The computer system can use the simulated memory stack to store a return address before jumping to a subroutine or use the simulated stack to store a data value for subsequent retrieval and use. The non-general purpose register set may include memory type range registers (MTRRs). One of the MTRRs is designated as the stack pointer register and is used to store a pointer index value which identifies which of the other MTRR registers is associated with the top of the simulated memory stack. The computer system preferably includes a non-volatile memory, such as a ROM, which contains executable instructions for implementing the simulated memory stack. The instructions provide for incrementing and decrementing the pointer index value and writing to and reading from the MTRR registers identified by the pointer index as associated with the top of simulated stack.

Abstract: An address generator for generating addresses in an prescribed order in the case of writing/reading data to/from predetermined storage means, comprises a first address data generating means for generating a plurality of first address data which have predetermined address intervals, a second address data generating means for generating a plurality of second address data representing sequentially shifted positions of the first address data one row by one row within address intervals, and an addition means for generating addresses which have predetermined intervals in order by adding the second address data to the first address data.

Abstract: A method and apparatus for accessing successive memory locations without the need for multiple index register writes and without the need for a wide address bus from the controller into a memory control system. The memory control system includes an index register and a data register. The index register has a connection to the controller and the buffer. The data storage register has a connection to the buffer and to the controller. The index register receives an address to a location in the buffer. Each time the contents of the index register are changed, data associated with the address are automatically written into the data storage register. Each time the data storage register is accessed (read or written), the index register in incremented. The controller is able to read or write unlimited numbers of sequential locations up to the full buffer space, using only a single controller access per byte.

Abstract: The stack pointer is used for generating the next unutilized location in the stack memory device in order to indicate where a current value in the program counter is to be written. The stack pointer also generates a directly preceding location to the next unutilized location in order to read the last value of the program counter that was written to the stack memory device. The stack pointer will select the next unutilized location in the stack memory device for a write operation and the directly preceding location to the next unutilized location in the stack memory device for a read operation. The stack pointer will further perform either a post increment or post decrement operation on the next unutilized location in the stack memory device after execution of a current instruction.

Abstract: A method and apparatus for controlling and caching memory read operations is presented. A memory structure is used to store data for read operations in a manner that allows the data to be reused in order to respond to similar subsequent memory accesses. Circuitry is included that determines if data corresponding to read requests is currently buffered in the memory structure. If it is, no additional memory accesses over a bus are required to respond to the read request. If the data is not currently buffered, a read request is issued over the bus, and when the data is returned in response to the read request, it is placed in the memory structure for responding to the read request and possibly for responding to additional subsequent read requests.

Abstract: A selective output circuit of a DMA controller selectively outputs either an address change amount relevant to the transfer data size or an address change amount independent of the transfer data size to a second input port of an adder with reference to settings of control register. The adder has a first input port for receiving an address value being set in a source address register and a second input port for receiving the selected address change amount, and is arranged so as to output a summed-up result to the source address register.

Abstract: A method and system for purging translation lookaside buffers (TLB) of a computer system are described. Directed write transactions can be used to avoid deadlock and avoid the need for additional bridge buffers. Broadcast emulation can be achieved by linking the nodes in a doubly-linked list and having neighboring nodes notify each other of changes in TLB entries.

Abstract: The stack pointer is used for generating the next unutilized location in the stack memory device in order to indicate where a current value in the program counter is to be written. The stack pointer also generates a directly preceding location to the next unutilized location in order to read the last value of the program counter that was written to the stack memory device. The stack pointer will select the next unutilized location in the stack memory device for a write operation and the directly preceding location to the next unutilized location in the stack memory device for a read operation. The stack pointer will further perform either a post increment or post decrement operation on the next unutilized location in the stack memory device after execution of a current instruction.

Abstract: A buffer access control circuit to access a buffer which is divided into an upper buffer and a lower buffer which are assigned the same address and a memory unit including the buffer access control circuit. The buffer access control circuit includes latch circuits which store data in response to upper and lower buffer access signals, and a first detection circuit which detects whether data latched by the latch circuits match. A modifying circuit inputs data to the first and second latches or inputs inverted data to the first and second latches when one of the upper and lower buffer access signals is generated and the detection circuit detects a match. In this manner, the buffer access control circuit is used to update an address one by one, without the use of a delay circuit when consecutively accessing the upper and lower buffers.

Abstract: A data management method is first used for registering the plurality of entry data having n-bit length and performing match retrieval by masking a (n−m(i)) bit from the least significant bit side, whereby to detect the value of an m(i) bit from the side of the most significant bit matching a specific entry data. Then match retrieval is performed repeatedly by shifting a bit to be masked by an m(i+1) bit each time toward the low order side and detecting a corresponding value of m(i+1) bit until no bit to be masked exists so as to detect the value of an n bit matching the entry data. Further, an entry address at which the specific entry data matching the value of the n bit thus detected has been registered is obtained in order that a new entry data is registered at the entry address. A data management apparatus has a control circuit for controlling the operation of the associative memory in accordance with the data management method according to the present invention.

Abstract: A combined cache with main memory and a control method thereof, which can be configured with various structures of cache by only adding a minimized control circuit in order to be used as main memory. The N-way cache memory system includes N cache memory blocks receiving a tag field and an offset field of an address bus, a logic OR element for performing a logic OR operation with way hit signals from each cache memory block and for generating a cache hit signal when a way hit signal is produced in one of the cache memory blocks, and a first selection element for outputting data to a data bus, which results from the cache memory blocks in response to the way hit signal.

Abstract: A highly flexible and complex BIST engine provides at-speed access, testing, characterization, and monitoring of on-chip memory arrays, independent of other chip circuitry such as a CPU core. Each BIST engine has a main control block, at least one address generation block having an address local control block and one or more address-data generation blocks, and at least one data generation block having a data local control block and one or more data generation blocks. Each of the local address and data control blocks are programmed independently to define operations that will be performed by the individual address and data generation blocks, respectively. The main control block in turn controls operation of the local address and data control blocks to effect desired testing, accessing, and monitoring of the on-chip memory arrays.

Abstract: In order to precisely measure the speed of memory unit, the memory unit stores at least one bit data at a predetermined bit position at each memory word such that the logical value of the one bit data changes alternately in order of memory address. An address increment circuit, which is provided in a module including the memory unit, successively generates memory addresses which are applied to the memory. The address increment circuit increments a memory address in response to the output of the memory. The memory speed between two consecutive memory outputs is detected by measuring a pulse width of a pulse signal outputted from the memory unit. Thus, a relatively large delay otherwise caused at a buffer amplifier can effectively be compensated.

Abstract: A method (50) of operating a computing system (10). The computing system comprises a cache memory (12b), and the cache memory has a predetermined number of cache lines. First, the method, for a plurality of write addresses, writes data (64) to the cache memory at a location corresponding to each of the plurality of write addresses. Second, the method cleans (70) a selected number (68) of lines in the cache memory. For each of the selected number of lines, the cleaning step evaluates a dirty indicator corresponding to data in the line and copies data from the line to another memory if the dirty indicator indicates the data in the line is dirty. Lastly, the selected number of lines which are cleaned is less than the predetermined number of cache lines.

Abstract: An Address Generation Unit (AGU) for a processor such as Digital Signal Processor that includes a data memory addressable to obtain X and Y operands and a program decoder. The AGU is connected to the data memory and the program decoder and includes two Arithmetic Logic Units that are used to generate the X and Y operands. Each alu a has a triplet of registers associated there with and include a linear path of a first DBLC adder. The first DBLC adder has an A input, a B input, a carry input connected to receive a first control signal, and a summation output. The linear path further includes a by pass connection for by passing the first DBLC adder. A multiplexer selects either the summation output or the by pass as a linear output. Each alu also includes a modulo path that is in parallel with the linear stage. The modulo path has a series connection of a Carry Sum Adder (csa) and a second DBLC adder with a modulo output. A second multiplexer selects either the linear output or the modulo output as a result.

Abstract: An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by defining a current memory address, choosing one or more modes by which increment-generated, decrement-generated, or combination increment/decrement addresses that define a next memory address are generated, and generating the row address and the column address of the next memory address in accordance with interdependent row carry-out and column carry-out operations.

Abstract: A system, method, and program for detecting and assuring a row by column structure in a Dynamic Random Access Memory array is disclosed. By writing to and reading from each memory location of the DRAM array, memory integrity is assured. The number of columns in the DRAM array is identified by writing data to and reading data from addresses selected from a series of cell addresses. The series of cell addresses identify standard DRAM column structures. When the data written to and read from the cell address is identical, the column configuration of the DRAM arrays is identified. The number of rows in the memory array is then identified by writing data to and reading data from addresses selected from a second series of cell addresses. The second series of cell addresses identify standard DRAM row structures. When data written to and read from the cell address is identical, the row configuration of the DRAM array is identified and accordingly, the row by column structure and integrity of the DRAM array are known.

Abstract: The inventive state mechanism assigns N+1 tags to N versions of an object stored in N memory areas. Thus, one tag is unused. An additional tag is used as a null or uninitialized tag. The other tags are assigned in a particular precedence order to revisions as they are stored. Thus, each assigned tag, except the null tag, has both a unique predecessor as well as a unique successor tag. The last tag of the sequence is lower in precedence to the first tag of the sequence, and this forms the cyclic relationship. The unused tag is used to determine the tag that is to be assigned to the next revision. The unused tag is also used to determine which revision is the most current revision. The inventive state mechanism is used by a memory management controller in maintaining the revisions.

Abstract: The software system architecture supports a rotating media in the storage and retrieval of data, where the rotating media stores in data tracks of multiple sectors, through the use of a microcontroller for the execution of a control program that schedules plural control tasks temporally distributed for respective execution during the rotational period of a predetermined track and sector. The scheduling of the plural control tasks is synchronized with respect to data retrieved from the predetermined sector. The plural control tasks include a rotational control task for determining an adjustment to the spin speed of the rotating media, a track following task for determining an adjustment to the alignment of the read/write head with respect to the predetermined track and a sector timing task for determining the position of the read/write head with respect to the predetermined track.

Abstract: A method and system in a data storage system for reading stored data from the data storage system, where the data storage system comprises N data storage drives and an associated cache, where data and calculated parity are striped across the N data storage drives, where a stripe comprises multiple sectors on each of the N data storage drives. Data is requested from the data storage system. A determination is made of whether or not the requested data currently resides in a cache associated with the data storage system. In addition, a determination is made of whether or not the requested data sequentially follows other sectors also residing in the cache. Only the requested data is fetched into the cache if it is determined that the requested data does not reside in the cache and the requested data does not sequentially follow sectors in the cache.

Abstract: If a word line is selected by inputting an immediate value and base address, whose values are determined at different timings, to an adder, the access speed decreases due to the constraint of the base address whose value is determined at a later timing. According to this invention, decoding is performed by inputting only the immediate value whose value is determined earlier to an address decoder AD. Thereafter, a word line WL is selected by performing rotation using the base address whose value is determined at a later timing. This makes it possible to start decoding processing without waiting for the determination of the value of the base address and increase the overall access speed.

Abstract: A first-in-first-out (FIFO) memory device includes a plurality of FIFO memory cores that contain a plurality of cells. A variable cell size circuit supports user programmable cell sizes in a FIFO memory device to permit selection of a wide range of cell sizes. The variable cell size circuit controls successive accesses to a cell in the memory device, and it resets a byte count when the byte: count equals the cell size value to initialize the circuit for a subsequent access operation. The variable cell size circuit further includes a prediction circuit that indicates completion of access to the cell a predetermined number of counts prior to completion of the actual access. An alignment circuit generates data for write operations in cells that store an odd number of bytes per cell to compensate for the two byte per cell read operations. Each FIFO memory core includes a circuit that generates a cell available signal to indicate whether a cell in a corresponding FIFO memory core is available for reading.

Abstract: An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by exercising a programmable initialization feature.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A fast physical address is generated in parallel with a fully computed virtual-linear-physical address in a system using segmentation and optional paging. This fast physical address is used for a tentative or speculative memory reference, which reference can be canceled in the event the fast physical address does not match the fully computed address counterpart. In this manner, memory references can be accelerated in a computer system by avoiding a conventional translation scheme requiring two separate and sequential address translation operations—i.e. from virtual to linear, and from linear to physical.

Abstract: A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths. The ALUs of the data path are coupled using a carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating a signal in response to a carry bit received over the carry chain, the signal comprises a saturation signal and a saturation value. The saturation signal is generated using logic that tests for saturation in the data path. The ALUs of the data path are further coupled using a right-going carry chain for transmitting the saturation signal back down the data path. The saturation signal is transmitted from the MSB ALU through the ALUs of the data path to the LSB ALU using a first back propagation channel.

Abstract: A semiconductor circuit of the present invention comprises, a decoder responding a plurality of address signals to produce a plurality of decoded address signals, a plurality of switch circuits receiving the respective decoded address signals, each switch circuits outputting an output signal, a plurality of registers receiving the respective output signals, each registers outputting a latched output signal, and supplying the latched output signal to the switch circuits except the switch circuit corresponding to that particular latched output signal, and a control circuit generating a control signal in response to a part of the address signal, the switch circuit outputting one of the decoded address signal and the latched output signal as said output signal according to the control signal.

Abstract: In one embodiment, there is a single integrated circuit microprocessor (10). The microprocessor has an instruction pipeline (12) which comprises an execution stage (12a) operable to process an information unit of a first length. The microprocessor further includes a cache circuit (20) comprising a memory (34) operable to store a transfer unit of information of a second length and accessible by the instruction pipeline. The second length corresponding to the capability of the cache circuit is greater than the first length corresponding to the execution stage operability. Lastly, the microprocessor includes a block move circuit (24) coupled to the cache circuit and operable to read/write a transfer unit of information of the first length into the memory of the cache circuit.

Abstract: The present invention is an apparatus and method for two-stage address generation that uses pipelining to avoid one level of latency in certain address-generation situations. The first level of the present invention contains redundant three-lever hardware that performs pre-add logic on 32-bit or 16-bit operands. The pre-add logic circuit for 32-bit operands comprises three carry-save adders. For 16-bit operands, the pre-add logic circuit comprises a four-port three-level 16-bit adder. The second stage comprises a three-logic level adder that adds two operands. The method of the present invention avoids one level of latency for simple address generation, although both stages are always utilized. For complex address generation, both latency cycles are required. Regarding dependent generation, the present invention provides a single-cycle latency bypass datapath that also avoids one level of latency.

Abstract: A method is provided for controlling a stack memory with a stack pointer. The method is composed of four major steps in a four phase instruction cycle. The first phase of the method decodes an instruction at an address retained by a program counter. The second phase reads a memory location. The third phase executes the operation of the instruction. Finally, the fourth phase writes the result of the executed operation into a memory location. Various alternate embodiments can modify the above-mentioned steps. For example, the second step can be modified so that it includes a call instruction wherein the address retained by the program counter is written into a stack memory during the second phase at a stack pointer address. Additional sub-steps can include the decrementing of a stack pointer address, the selection of the stack pointer address or the decremented stack pointer address, and the provision of return instruction wherein a previously stored program counter address is read from the stack memory.

Abstract: A buffer manager divides a memory space into a plurality of buffers. Each buffer occupies a plurality of sequential memory locations. The sequential memory locations include a start and an end address. To write data to a buffer, the buffer manager provides a start address and burst size to an address translator. The address translator converts the start address and the burst size to SDRAM memory address locations. The start and end address of each buffer is mapped to a different bank in the SDRAM memory.

Abstract: A method and apparatus for efficiently translating virtual to physical addresses is provided. An embodiment of the apparatus includes a TLB descriptor table that includes a series of TLB descriptors. Each TLB descriptor includes an offset that selects a TLB segment within a translation lookaside buffer (TLB). To perform a virtual to physical address translation, a processor sends a virtual address and a descriptor ID to the memory request unit. The descriptor ID is used to select the TLB segment that will be used to perform the virtual to physical address translation. Each TLB segment may have different physical and logical characteristics. In particular, each TLB segment may be associated with a different type of memory page. In this way the present invention, enables the simultaneous use of a range of page types and sizes in a single computer system.

Abstract: The Intelligent DMA Controller (IDMAC) significantly reduces system latency by replacing one or more layers of software with hardware. The IDMAC uses controlwise and datawise intelligence. The controlwise intelligence of the IDMAC is given specific knowledge of the structure of certain pieces of memory or hardware registers, (e.g. parameter blocks), used for Inter Process Communication. This specific knowledge can be imparted during the design phase of the IDMAC, or dynamically provided during its operation as system requirements dictate. The IDMAC achieves its DMA controlwise intelligence by understanding parameter blocks (PBs). The IDMAC reads the structure of the PB from memory directly, gets all of its PB parameters directly from memory, dereferencing as required, and then begins transferring data between the source and destination as instructed by the PB(s). Examples of PB parameters are source address, destination address, transfer length, and data intelligence opcode.

Abstract: The overall transfer rate of user data is improved with the translation of certain low-number logical addresses into higher number physical addresses in order to displace inward the low-number logical data (e.g., low-level data). This makes it possible to store at least some user data on the higher transfer rate, outer cylinders. The sequence of the resulting physical addresses is changed relative to the logical addresses.

Abstract: A system for implementing a graphics address remapping table as a virtual register in system memory. The remapping table includes virtual registers that each store a target index that references a block of the system memory that stores graphics data using an indirect addressing scheme that enables the individual virtual registers of the remapping table to be accessed in response to a transaction request. Accessing a selected virtual register indirectly requested by the transaction request enables the access to the graphics data pointed to by the selected virtual register.

Abstract: The invention provides a method and apparatus that provides for a determination of a memory address for an object coordinate in a non-linear addressing scheme. To minimize computation complexity, the memory address of the object coordinate is based upon a previously computed address of an object coordinate that is in proximity to the given object coordinate.

Abstract: A microprocessor apparatus executes a program including an instruction which indicates an address for taking out an operand from a main memory in a predetermined addressing mode which belongs to a displacement-adding register indirect addressing mode. The microprocessor includes address generating portion for shifting by a predetermined number of bits the value of a displacement which is indicated by the instruction, adding the thus-shifted value to the value stored in a predetermined register and thus generating an effective address, when the operand of the instruction is taken out from the main memory.

Abstract: To accelerate read operations, or the operations that modify the operating parameters of a microcontroller, an interface is provided with three registers—an address register, an instruction and data register, and an auxiliary register. The instruction and data register supports the auxiliary register by indirect addressing. The address register is furthermore provided with an incrementation circuit mechanism for indirect incrementation. With the indirect addressing and the automatic incrementation, the number of external operations are reduced for continuous read or write operations.

Abstract: Disclosed is a method and a device to improve the data output speed of a memory associated with a central processing unit of a microcomputer, should the reading be done at consecutive addresses of the memory in the mode known as the “burst read” mode. The address register is of the type with incrementation controlled by a sequencing circuit. The read register is followed by a data register which records the contents of the read register so as to free this read register to record the contents of the memory cells that are selected by the incremented address.

Abstract: An address generator for a solid state disk drive device includes a hardware multiplier logic circuit dedicated to computation of the address by multiplying a lock size by a logical block number, to obtain the start address for a memory array read or write operation. The dedicated multiplier circuit advantageously provides very quick computation of these relatively large numbers, which typically involves a 32 bit by 16 bit multiplication. The multiplier includes a shift register initially holding the logical block number which is shifted a particular number of times, the number of shift pulses representing a value of the block length. The output of the shift register is the desired address.

Abstract: A telecommunication device has a processor for processing data and a memory which stores the data. The memory is coupled to the processor by a data bus and an address bus. A first address counter provides an output address to the memory for reading out a desired data having the output address. A count of the first address counter is changed to a current address in response to a control signal from the processor, each time the processor generates a desired address. The current address is provided to the memory as the output address which is also the desired address. A comparator compares the desired address with the output address from a second address counter and outputs a load signal to the first counter when the current address from the second address counter differs from the desired address. The load signal loads the desired address in the first counter over the address bus when the current address differs from the desired address so that the output address is equal to the desired address.