Abstract: An interconnect device may include one or more hardware-implemented modules configured to: receive a command from a processing core; perform, based on the received command, an operation including either one or both of an accumulation of sets of data stored in a memory and an aggregation of results processed by the processing core; and provide a result of the performing of the operation.

Abstract: A client system includes a client-side host device, and a client-side storage device including a storage controller and a storage memory. The storage controller includes a host interface, a processor configured to control a read operation and a write operation for the storage memory, and a homomorphic encryption and decryption accelerator configured to, based on receiving a read request from the client-side host device, perform homomorphic encryption on first plaintext data that is read from the storage memory, to generate first homomorphic ciphertext data, and provide the first homomorphic ciphertext data to the client-side host device through the host interface, and based on receiving a write request from the client-side host device, perform homomorphic decryption on second homomorphic ciphertext data that is received through the host interface, to generate second plaintext data, and write the second plaintext data in the storage memory.

Abstract: Disclosed is a cache directory including one or more cache directories configurable to interchange within each cache directory entry at least one bit between a first field and a second field to change the size of the region of memory represented and the number of cache lines tracked in the cache subsystem.

Abstract: The technology described implements attestation programs that employ “code reuse” techniques. In particular, the technology relates to auto-generating attestation programs for, among other aspects, detecting whether a program has been modified. In one non-limiting example, the technology uses a tool that scans a software program (e.g., a video game) code for usable code sequences. The tool can automatically combine code sequences to generate a large number of attestation programs of different variety (e.g., memory checks, hashing).

Abstract: Provided are a method and device for storing time series data with adaptive length encoding, including: acquiring data values corresponding to timestamps according to a sequential order of timestamps; using a ratio of storage space values required to pre-store the previous n data values to storage space values required to pre-store rule information of a preset encoding rule and encoding data according to the previous n data values as a storage gain corresponding to the time at which the n-th data value is acquired; storing the rule information of the preset encoding rule and the encoding data corresponding to a previous n?1 data values when the storage gain corresponding to the time at which the n-th data value is acquired is less than that corresponding to the time at which the (n?1)-th data value is acquired.

Abstract: A metal option structure of a semiconductor device may include: a plurality of vias connecting first metal lines provided in a first metal layer to second metal lines provided in a second metal layer disposed over the first metal layer, and configured to constitute a plurality of nodes of an option circuit; and an identification pattern disposed between the first and second metal layers and having a different layout structure from the vias.

Abstract: Aspects of the subject disclosure may include, for example, receiving, from a first network, a first request for a first global internet protocol (IP) address that is to be allocated to a first device that is provisioned on the first network, the first device being provisioned on the first network prior to allocation of the first global IP address, the first device being provisioned on the first network via use of a first subscriber identity that is associated with the first device and that is recognized by the first network, the first request including the first subscriber identity; generating, responsive to the first request, the first global IP address, the first global IP address enabling communication with the first device when the first device is subsequently registered on a second network, the first subscriber identity being stored in a database as corresponding to the first global IP address that is generated; and sending, to the first network, the first global IP address that had been generated.

Abstract: An apparatus and method are provided for interpreting permissions associated with a capability. The apparatus has processing circuitry for executing instructions in order to perform operations, and a capability storage element accessible to the processing circuitry and arranged to store a capability used to constrain at least one operation performed by the processing circuitry when executing the instructions. The capability identifies a plurality N of default permissions whose state, in accordance with a default interpretation, is determined from N permission flags provided in the capability. In accordance with the default interpretation, each permission flag is associated with one of the default permissions. The processing circuitry is then arranged to analyse the capability in accordance with an alternative interpretation, in order to derive, from logical combinations of the N permission flags, state for an enlarged set of permissions, where the enlarged set comprises at least N+1 permissions.

Abstract: An operation method of an electronic device including a core includes reading first status information from a first status register of a first functional block driven independently of the core, reading second status information from a second status register of a second functional block driven independently of the core, reading first change information from a first flag register of the first functional block, reading second change information from a second flag register of the second functional block, determining whether an operation status of the electronic device is any one status of an idle status and a busy status, based on the read first and second status information and the read first and second change information, and operating in an operation mode corresponding to the determined operation status.

Abstract: An apparatus and method are provided for generating signed bounded pointers from general purpose specified data, for example data that may exist within a backing store such as a disk. The apparatus has processing circuitry that is responsive to a bounded pointer generation request to perform a generation operation to generate a bounded pointer from the specified data provided at least one generation condition is met. The bounded pointer comprises a pointer value and associated attributes, and the associated attributes include range information indicative of an allowable range of addresses when using the pointer value.

Abstract: A variety of applications can include systems and/or methods of partial save of memory in an apparatus such as a non-volatile dual in-line memory module. In various embodiments, a set of control registers of a non-volatile dual in-line memory module can be configured to contain an identification of a portion of dynamic random-access memory of the non-volatile dual in-line memory module from which to back up content to non-volatile memory of the non-volatile dual in-line memory module. Registers of the set of control registers may also be allotted to contain an amount of content to transfer from the dynamic random-access memory content to the non-volatile memory. Additional apparatus, systems, and methods are disclosed.

Abstract: Method and apparatus for processing data are disclosed. The method may include: sorting to-be-compressed at least one piece of data in a predetermined order; for a sorted piece of data, in response to the data having a common prefix with a previous piece of data of the piece of data, adding the common prefix to a common prefix set; dividing the sorted at least one piece of data into at least one group based on the common prefix set and determining a common prefix of each group; and storing, for a group in the at least one group, a common prefix of the group and a non-common prefix portion of each piece of data in the group, and recording a common prefix corresponding to each piece of data in the each group and a shared length between the each piece of data and the common prefix.

Abstract: In an aspect, a processor supports modeless execution of 64 bit and 32 bit instructions. A Load/Store Unit (LSU) decodes an instruction that without explicit opcode data indicating whether the instruction is to operate in a 32 or 64 bit memory address space. LSU treats the instruction either as a 32 or 64 bit instruction in dependence on values in an upper 32 bits of one or more 64 bit operands supplied to create an effective address in memory. In an example, a 4 GB space addressed by 32-bit memory space is divided between upper and lower portions of a 64-bit address space, such that a 32-bit instruction is differentiated from a 64-bit instruction in dependence on whether an upper 32 bits of one or more operands is either all binary 1 or all binary 0. Such a processor may support decoding of different arithmetic instructions for 32-bit and 64-bit operations.

Abstract: A computing device may identify a series of bits representative of a first binary large object (BLOB) for navigation data including road segments and road attributes. The computing device duplicates each bit of the series of bits a predetermined number of times to form a first bit string. The first bit string is larger than the series of bits by a factor of the predetermined number. The computing device performs a binary difference of the first bit string to a second bit string representative of a second BLOB. A result of the binary difference is stored in a navigation patch file.

Abstract: A memory, a data processing system comprising a memory, a method of operating a memory and a memory compiler apparatus and method of memory compilation are provided, which relate to a memory comprising data storage circuitry to store data values at data locations. Addressing circuitry is provided to access the data value at a storage location in dependence on a received address and readout circuitry to provide an output value in dependence on the accessed data value. The memory further comprises scrambling circuitry to select at least one of: a mapping between the address and the storage location; and a mapping between the data value and the output value, in dependence on a received scrambling value. The mapping between the address and the storage location and/or the data value and the output value can thus be easily and rapidly changed.

Abstract: A processor includes a core, a hardware prefetcher, and a prefetcher control module. The hardware prefetcher includes logic to make speculative prefetch requests, through a memory subsystem, for elements for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to selectively suppress, based on a hardware-prefetch suppression instruction executed by the core, a speculative prefetch request to be made by the hardware prefetcher.

Abstract: Comparator circuitry comprises carry-save-addition (CSA) circuitry to generate a set of partial sum bits and a set of carry bits in respect of corresponding bit positions in a first input value, a second input value, a carry-in value associated with the first and second input values, and a third input value, the CSA circuitry comprising inverter circuitry to provide a relative inversion between the third input value and the group consisting of the first and second input values; and combiner circuitry to combine the set of partial sum bits, the set of carry bits offset by a predetermined number of bits in a more significant bit direction, the carry-in value and 1, to generate at least a carry output bit; in which the carry output bit is indicative of whether the third input value is greater than the sum of the first and second input values.

Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

Abstract: A memory chip, a memory system, and a method of accessing the memory chip. The memory chip includes a substrate, a first storage unit, and a second storage unit. The first storage unit includes a plurality of first memory cells may have a first storage capacity of 2n. The plurality of first memory cells may be configured to activate in response to a first selection signal. The second storage unit includes a plurality of second memory cells and may have a second storage capacity of 2n+1. The plurality of second memory cells may be configured to activate in response to a second selection signal.

Abstract: A memory device can include an interface comprising a plurality of control and address connections and at least one set of data connections; memory circuits comprising a plurality of storage locations randomly accessible for read and write operations in response to an address value received on the address connections; and accelerator circuits coupled to the memory circuits and configured to perform at least one predetermined operation on data stored in the memory device to generate modified data for storage within the memory circuits in response to at least one command received on the interface; wherein the at least one command is supplemental to read and write commands executable by the memory device.

Abstract: A processing device implements a set of instructions to perform a centrifuge operation using vector or general purpose registers. In one embodiment, the centrifuge operation separates bits in a source register to opposing regions of a destination register based on a control mask, where each source register bit with a corresponding control mask value of one is written to one region in a destination register, while source register bits with a corresponding control mask value of zero are written to an opposing region of the destination register.

Abstract: A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment of the program counter in accordance with a result of the predecoding.

Abstract: A memory chip, a memory system, and a method of accessing the memory chip. The memory chip includes a substrate, a first storage unit, and a second storage unit. The first storage unit includes a plurality of first memory cells may have a first storage capacity of 2n. The plurality of first memory cells may be configured to activate in response to a first selection signal. The second storage unit includes a plurality of second memory cells and may have a second storage capacity of 2n+1. The plurality of second memory cells may be configured to activate in response to a second selection signal.

Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes, including pass-through and active modes. Techniques are presented for the addressing of memory chips within such a topology, including an address assignment scheme.

Abstract: Apparatus comprises a processor configured for operation under a sequence of instructions from an instruction set, wherein said processor comprises: means for conditionally inhibiting at least one type of trap, interrupt or exception (TIE) event, wherein, when operating under a sequence of instructions, said inhibition means is inaccessible by said instructions to inhibit the or each type of TIE event, without interrupting said sequence. A data processing apparatus includes a processor adapted to operate under control of program code comprising instructions selected from an instruction set, the apparatus comprising: a predefined memory space providing a predefined addressable memory for storing program code and data, a larger memory space providing a larger addressable memory, means for accessing program code and data within the predefined memory space, and means for controlling the access means so as to enable the access means to access program code located within the larger memory space.

Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

Abstract: A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) having compact bitcells with embedded partial A+B=K logic to generate two speculative hit/miss signals under control of a delayed evaluate signal. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).

Abstract: To defend a computer against malware, first executable code, of the computer, that includes a signature that identifies an address, in the computer's memory, of a respective data structure that is potentially vulnerable to tampering, is identified. The first executable code is copied to provide second executable code that emulates the first executable code using its own respective data structure. The first executable code is modified to jump to the second executable code before accessing the data structure, and also so that the signature identifies the address of a guard page.

Abstract: Systems and methods are disclosed for scheduling a plurality of tasks for execution on one or more processors. An example method includes obtaining a counter value of a counter. The method also includes for each work queue of a plurality of work queues, identifying an execution period of the respective work queue and comparing a counter value to an execution period of the respective work queue. Each work queue includes a set of tasks and is defined by an execution period at which to run the respective set of queued tasks. The method further includes selecting, based on the comparing, a subset of the plurality of work queues. The method also includes scheduling a set of tasks of slower frequency queued in a selected work queue for execution on one or more processors before a set of tasks queued in a non-selected work queue. The work items may be scheduled in O(1) because the design inherently prioritizes the tasks based on the urgency of their completion, and may do so by resetting a work queue pointer.

Abstract: A method and circuit arrangement for selectively predicating an instruction in an instruction stream based upon a value corresponding to a predication register address indicated by a portion of an operand associated with the instruction. A first compare instruction in an instruction stream stores a compare result in at a register address of a predication register. The register address of the predication register is stored in a portion of an operand associated with a second instruction, and during decoding the second instruction, the predication register is accessed to determine a value stored at the register address of the predication register, and the second instruction is selectively predicated based on the value stored at the register address of the predication register.

Abstract: A semiconductor device in which the power consumption of a register is low is provided. Further, a processing unit whose operation speed is high and whose power consumption is low is provided. In the semiconductor device, a register operating at high speed and a nonvolatile FILO (first-in-last-out) register capable of reading and writing data from/to the register are provided.

Abstract: Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences such as high-level language software critical loops are converted into read/transform/write (RXW) processes with buffer based flow control between the processes. Having separate read and write processes allows an arbitrary number of sequential reads/writes to occur in any order, subject to buffer size, allowing bursting/sequential transactions that are more efficient than random accesses.

Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes conversion power logic to receive an instruction including an untranslated memory address, determine whether a code segment (CS) base address is equal to zero, and in response to a determination that the CS base address is equal to zero, execute the instruction using the untranslated memory address. Other embodiments are described and claimed.

Abstract: Technologies are generally described for a cache coherence directory in multi-processor architectures. In an example, a directory in a die may receive a request for a particular block. The directory may determine a block aging threshold relating to a likelihood that data blocks, including the particular data block, are stored in one or more caches in the die. The directory may further analyze a memory to identify a particular cache indicated as storing the particular data block and identify a number of cache misses for the particular cache. The directory may identify a time when an event occurred for the particular data block and determine whether to send the request for the particular data block to the particular cache based on the aging threshold, the time of the event, and the number of cache misses.

Abstract: A memory controller is used to receive a first request for a portion of a physical memory and metadata associated with the portion of the physical memory. The first request for the portion of the physical memory is translated to correspond to an indirect data structure. The indirect data structure comprises a reference to a data line, and a metadata associated with the data line. The data line is formed within the physical memory.

Abstract: A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.

Abstract: In various embodiments, a semiconductor component may include a semiconductor layer having a front side and a back side; at least one electronic element formed at least partially in the semiconductor layer; at least one via formed in the semiconductor layer and leading from the front side to the back side of the semiconductor layer; a front side metallization layer disposed over the front side of the semiconductor layer and electrically connecting the at least one electronic element to the at least one via; a cap disposed over the front side of the semiconductor layer and mechanically coupled to the semiconductor layer, the cap being configured as a front side carrier of the semiconductor component; a back side metallization layer disposed over the back side of the semiconductor layer and electrically connected to the at least one via.

Abstract: A method for managing commands in a command queue, a memory controller, and a memory storage apparatus are provided. The method includes: storing at least one first command in a command queue register according to a plurality of first indication bits and updating the first indication bits according to a current storage status of the command queue register; generating a plurality of updated second indication bits according to the updated first indication bits and a plurality of second indication bits. The method also includes: obtaining at least one first command index corresponding to at least one register block storing the at least one first command in the command queue register according to the updated second indication bits and adding the at least one first command index into a command index register; executing commands corresponding to un-executed command indices in the command queue register.

Abstract: Hardware-based packet editor receives a packet editing script which includes script entries indicating modifications to a data packet and a data block with data for the modified data packet. For a script entry in the packet editing script, the packet editor copies data in the data block at a block location and with a block length identified in the script entry into a packet buffer. The packet editor repeats the copying for the remaining script entries for the modified data packet. The packet editor then generates the modified data packet with the data in the packet buffer. The packet editing script is generated such that a script entry is created for data to be included in the modified data packet and data to be inserted into the modified data packet. Creation of a script entry is omitted for data to be removed.

Abstract: Hardware-based packet editor receives a packet editing script which includes script entries indicating modifications to a data packet and a data block with data for the modified data packet. For a script entry in the packet editing script, the packet editor copies data in the data block at a block location and with a block length identified in the script entry into a packet buffer. The packet editor repeats the copying for the remaining script entries for the modified data packet. The packet editor then generates the modified data packet with the data in the packet buffer. The packet editing script is generated such that a script entry is created for data to be included in the modified data packet and data to be inserted into the modified data packet. Creation of a script entry is omitted for data to be removed.

Abstract: Memory devices and methods are described that include a stack of memory dies and an attached logic die. Method and devices described provide for power management of portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.

Abstract: In one embodiment, a system wide static global stack pool in a contiguous range of random access memory is generated, a block of memory in the system global pool is assigned to a thread of a running process, and the thread stores local variable information in static global stack pool, such that the local variable is hidden from a stack frame back-trace. In one embodiment, a dynamically allocated data structure in system heap memory is generated, the data structure is locked to ensure atomic access, a block of memory in the data structure is assigned to a thread of a process, the data structure is unlocked, and the thread stores local variable information in static global stack pool, such that the local variable is hidden from a stack frame back-trace.

Abstract: A computerized method for sharing removable storage media in a network, the method comprising associating, in an index entry, a first piece of removable storage media in a first storage device with at least a first storage policy copy and a second storage policy copy; copying, to the first piece of removable storage media, data associated with the first storage policy copy; and copying, to the first piece of removable storage media, data associated with the second storage policy copy.

Abstract: In general, this disclosure describes techniques for selecting a memory channel in a multi-channel memory system for storing data, so that usage of the memory channels is well-balanced. A request to write data to a logical memory address of a memory system may be received. The logical memory address may include a logical page number and a page offset, where the logical page number maps to a physical page number and the logical memory address maps to a physical memory address. A memory unit out of a plurality of memory units in the memory system may be determined by performing a logical operation on one or more bits of the page offset and one or more bits of the physical page number. The data may be written to a physical memory address in the determined memory unit in the memory system.

Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

Abstract: A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.

Abstract: An example hashing unit includes a plurality of hardware-based hash tables, wherein each of the hash tables comprises a plurality of buckets, and wherein the plurality of hash tables comprise a set of zero or more active hash tables and a set of one or more inactive hash tables. An example hashing unit controller is configured to receive a key value to be stored in the hashing unit, determine that one of the inactive hash tables should be activated, and, based on the determination, activate the one of the set of inactive hash tables as a recently activated hash table, determine one of the buckets of the recently activated hash table to which a hash function associated with the recently activated hash table maps the received key value, and store the key value in the determined one of the buckets of the recently activated hash table.

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs), multiple reference values, and multiple mask values from memory. A selecting circuit within the TM uses a starting bit position and a mask size to select a portion of the IV. The portion of the IV is a lookup key value (LKV). The LKV is masked by each mask value thereby generating multiple masked values. Each masked value is compared to a reference value thereby generating multiple comparison values. A lookup table generates a selector value based upon the comparison values. A result value is selected based on the selector value. The selected result value is then communicated to the processor via the bus.

Abstract: The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting format information on the memory unit, calculating a logical address offset, and applying the offset to a host logical address.