Abstract: Systems and methods for reordering processor instructions. In accordance with a first embodiment of the present invention, a microprocessor comprises circuitry to process an instruction extension, wherein the instruction extension is transparent to the programming model of the microprocessor. The instruction extension may comprise a field for indicating an offset from a memory structure pointer. The microprocessor includes circuitry for adding the offset to the memory structure pointer to indicate a specific element of the memory structure. The specific element of the memory structure comprises address information corresponding to speculative data.

Abstract: A method and apparatus for decompressing relative addresses. A compressed relative address is retrieved from one or more micro-operation entries of a micro-operation storage and an uncompressed relative address is reconstructed from the compressed relative address and an instruction pointer (IP) address associated with the head of the micro-operation storage line in which the compressed relative address was stored. IP-relative addresses may be computed in a manner similar to relative branch targets, then compressed and stored in one or more micro-operation entries of a micro-operation storage line to be reconstructed later according to an IP address associated with the respective micro-operation storage line in which their compressed counterpart was stored.

Abstract: Embodiments are provided in which a method and apparatus for accessing a special mode register of a memory device are described. A command to access the special mode register is detected. The command is executed by driving data from the special mode register onto a data bus. The command self-terminates by placing the data bus in a high impedance state. One or more unused address bits may specify one of a plurality of special mode registers to be accessed by the command. The command to access the special mode register may be incapable of changing one or more bits in a mode register.

Abstract: A method for establishing a wireless connection between a first wireless device provided in a computer and a second wireless device, wherein group information that identifies the first wireless device is created and set for the first wireless device. The group information is transmitted to the second wireless device and is set for it. The first wireless device creates identification information that identifies the second wireless device with the group information to set it for the second wireless device. The first wireless device uses both of the group information and identification information to specify the second wireless device.

Abstract: In one embodiment, a cache memory system includes a cache memory coupled to a cache controller. The cache memory controller may receive an address and generate an index value corresponding to the address for accessing a particular entry within the cache memory. More particularly, the cache controller may generate the index value by performing a hash function on a first portion of the address such as an address tag, and combining a result of the hash function with a second portion of the address such as an index, for example.

Abstract: Disclosed is a vector indexed memory unit and method of operation. In one embodiment a plurality of values are stored in segments of a vector index register. Individual ones of the values are provided to an associated operator (e.g., adder or bit replacement). Individual ones of the operators operates on its associated vector index value and a base value to generate a memory address. These memory addresses are then concurrently accessed in one or more memory units. If the data in the memory units are organized as data tables, the apparatus allows for multiple concurrent table lookups. In an alternate embodiment, in addition to the above described operators generating multiple memory addresses, an adder is provided to add the base value to the value represented by the concatenation of the bits in the vector index register to generate a single memory address.

Abstract: In one embodiment, an apparatus includes an input port to receive a request to determine whether data units are stored in the cache, as well as an output port to generate look-ups for the pool of tags. The apparatus also includes a look-up filter coupled to the input and output ports, and operates to filter out superfluous look-ups for the data units, thereby forming filtered look-ups. Advantageously, the look-up filter can filter out superfluous look-ups to at least reduce the quantity of look-up operations associated with the request, thereby reducing stalling associated with multiple look-up operations. In a specific embodiment, the look-up filter can include a data unit grouping detector and a look-up suppressor.

Abstract: A register file for a data processing system comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of memory locations. Each memory location is addressable by an encoded address, wherein the encoded address corresponds to at least one register and processor mode. The input ports receive inputs for addressing at least one memory location using an encoded address. The output ports output data from at least memory location addressable by an encoded address.

Abstract: A method for providing BGP route updates in an MPLS network is disclosed. The route update is performed at a router having a forwarding information table containing BGP routes and an internal label, and an adjacency table containing BGP/VPN labels and said internal label. The internal label corresponds to at least one IGP route and has an adjacency associated therewith. The method includes updating the adjacency associated with the internal label following an IGP route change.

Abstract: A data processing system comprises a processor to process instructions. A plurality of pipeline stages to execute instructions including a register file. The register file includes a memory unit having a plurality of memory locations, each memory location being addressable by an encoded address. The encoded address corresponds to at least one register and processing mode. Input ports receive inputs for addressing at least one of the memory locations using an encoded address. Output ports to output data from at least one of the memory locations using an encoded address.

Abstract: A computer system memory is structured as contiguous memory chunks, each chunk having a header. A chunk header includes a first offset value, a sign bit associated with the first offset value, and a number of bits having values that are added to a second offset value that is determined from the first offset value. In particular, the actual offset value can be determined by adding the values of the bits to the second offset value and by multiplying the result by the binary equivalent of four. The second offset value is then used for determining an actual offset value that is applied to a base address to provide a memory location of the memory chunk.

Abstract: A method of selecting a data item from a memory within a first device, the method comprising the steps of evaluating within the first device a function of an input argument so as to form an output value, using the output value to select a data item from the memory and transmitting the selected data item to a second device.

Abstract: A method for prefetching data from an array, A, the method including: detecting a stride, dB, of a stream of index addresses of an indirect array, B, contents of each index address having information for determining an address of an element of the array A; detecting an access pattern from the indirect array, B, to data in the array, A, wherein the detecting an access pattern includes: using a constant value of an element size, dA; using a domain size k; executing a load instruction to load bi at address, ia, and receiving index data, mbi; multiplying mbi by dA to produce the product mbi*dA; executing another load instruction to load for a column address, j, where 1?j?k, and receiving address aj; recording the difference, aj?mbi*dA; iterating the executing a load instruction, the multiplying, the executing another load instruction, and the recording to produce another difference; incrementing a counter by one if the difference and the another difference are the same; and confirming column address j when the co

Abstract: An apparatus, system, and method are disclosed for redirecting an instruction pointer to recovery software instructions. A load module copies a first and second process to memory locations addressed by a first and second base address. An instruction pointer module addresses a memory location with an address comprising a pointer base address set to the first base address and an offset. A pointer modification module modifies the pointer base address from the first base address to the second base address in response to a read error to redirect the instruction pointer module to a memory location of the second process.

Abstract: A reconfigurable address generation circuit for image processing is configured to an arbitrary state based on configuration data generates a read address for reading out image data of pixel units having a plurality of rows and columns from a memory which stores image data. As the configuration data, there are set a X, Y count end value of the read out pixel unit, a width value of the image in the memory, and edge information for clip processing. The address generation circuit has X counter; Y counter; an X, Y clip processing circuits which convert the count value of the X, Y counter according to the left, right top and bottom edge information; and an address calcuration circuit which generates the reading out address, based on the count values from the X and Y clip processing circuits and the width value.

Abstract: A method and system that aggregates data associated with one or more entities from different data sources are provided. The data sources include documents, web pages, or images that have information about one or more entities. The information is extracted from the data sources based on criteria that define the entities. The extracted information is utilized to generate a hash identifier that corresponds to each entity and one or more storage locations. The one or more storage locations and associated hash identifiers are utilized to store the extracted information corresponding to the entities, and the extracted information for each entity is structured as a virtual page that is stored in an index having references to the data sources.

Abstract: A method and apparatus for high speed addressing of a memory space from a relatively small address space. An N-bit bus interfaces with a memory device having a 2M address memory space, where M is greater than N. The method and apparatus provide for (a) providing at least two registers, (b) receiving one byte of a plurality of N-bit bytes that together define an address in the memory space, (c) incrementing a count as a result of completing step (b), (d) addressing one of the two registers according to the incremented count in step (c), and (e) storing the one byte in the register addressed in step (d).

Abstract: A method for generating a sequence of memory addresses for a multi-dimensional data structure and an address generation unit are disclosed. The address generation unit includes an ADDRESS register, a STRIDE register, and a plurality skip generators, each having SKIP, SPAN and COUNT registers. An address value is initialized to a first address and each COUNT register is initialized. For each address of the sequence an address value is output and a stride value is added to the address value. For each dimension of the data structure the COUNT register associated with the dimension is updated as each address is generated. For all dimensions, when the COUNT register value becomes zero, the skip value associated with the dimension is added to the address value and its COUNT register is reset to a specified value.

Abstract: A computer system stores a dynamically sized array as a base array that contains references to subarrays in which the (composite) array's data elements reside. Each of the base-array elements that thus refers to a respective subarray is associated with a respective subarray size. Each base-array index is thereby at least implicitly associated with a cumulative base value equal to the sum of all preceding base indexes' associated subarray sizes. In response to a request for access to the element associated with a given (composite-array) index, the array-access system identifies the base index associated with the highest cumulative base value not greater than the composite-array index and performs the access to the subarray identified by the element associated with that base index. Composite-array expansion can be performed in a multi-threaded environment without locking, simply by employing a compare-and-swap or similar atomic operation.

Abstract: From an application program described in the form of a flow graph, input and output arcs are extracted. Packet rates on the input and output arcs are extracted, and it is determined whether the packet rates of the input arc and the output arc are lower than an upper-limit value of a pipeline transfer rate of a processor element. Based on the determination result, it is determined whether it is possible to execute the described flow graph program in the processor element. Performance evaluation of a program to be executed by a data driven processor based on an asynchronous pipeline transfer control can be carried out with ease and in a short time.

Abstract: Methods and apparatus are provided for performing circular buffer addressing. Upper boundaries, lower boundaries, circular buffer lengths, addresses, and offsets are set to allow circular buffer access efficiency. An addition/subtraction unit is provided to simplify implementation. Comparators are rearranged and in some instances replaced with combined adder/comparator logic units. The additional logic units and the rearrangement allow efficient implementation of circular buffer addressing, particularly on programmable chips.

Abstract: A system and method for generating and updating a file system on a client computer. An original file system may be compared to an updated file system and the differences between the two file systems may be defined in specific data blocks. The differences may include new data blocks, modified data blocks, and data blocks that have been deleted. The new data blocks or modified data blocks may be sent to the client computer along with reference file updates to update the file system on the client computer. A virtual file system on the client computer may be created using the set of data blocks and the reference files to point to which data blocks contain the data for specific files. As the file system is updated, new data blocks and modified data blocks may replace deleted data blocks in the set of data blocks.

Abstract: A bitwise addressing mode includes including the shaping of symbols of variable length during an operation for reading or writing a symbol in a bank of memories. The addressing is then done with the aid of a word address and of a bit pointer designating the start of the symbol in the word corresponding to the word address. A shift operation is performed during an operation of reading or of writing.

Abstract: Embodiments of the present invention provide method and device for searching fixed length data. The device includes a hash operation means for operating and outputting a hash value of inputted fixed length data, a data table memory consisting of N numbers of memory banks, where N is an integer that is more than and equal to 2, the data table memory for storing a data table holding a large number of fixed length data, a pointer table memory for storing a memory pointer table holding a memory address at which each fixed length datum is stored with the hash value as an index, and a comparison means for simultaneously comparing a plurality of fixed length data stored at the same memory address in the N numbers of memory banks with a single fixed length datum inputted to the hash operation means, the comparison means for outputting results of the comparison.

Abstract: Since no control of accesses made by a computer as accesses to a storage apparatus is executed, the computer can be used illegally to steal and improperly change data stored in the storage apparatus. Thus, an access-control mechanism external to the computer is constructed to solve this problem. That is to say, the control of accesses is executed in the storage apparatus and a network apparatus for each program executed by the computer. In order to enhance the implementability of such control of accesses, the control is executed without extending a variety of protocols of communications among the computer, the network apparatus and the storage apparatus. By implementing the control of accesses in this way, a program other than programs specified in advance is not capable of making an access to data stored in the storage apparatus. Thus, even if the computer is used illegally, data stored in the storage apparatus can be prevented from being stolen and changed improperly.

Abstract: A method for memory controlling is disclosed. It includes an embedded address generator and a controlling scheme of burst terminates burst, which could erase the latency caused by bus interface during the access of non-continuous addresses. Moreover, it includes a controlling scheme of anticipative row activating, which could reduce the latency across different rows of memory by data access. The method could improve the access efficiency and power consumption of memory.

Abstract: The invention relates to a method for accessing matrix elements, wherein accesses to two matrix elements that are adjacent in a row or in a column of a matrix and that are each specified by a respective relative address (ar, ac) are performed for the first of said elements in a first memory block (Bp1) using a first local address (a?1) and for the second of said elements in a different second memory block (Bp2) using a second local address (a?2)

Abstract: A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilizing a 12-bit offset field but with a fixed addressing mode and a second form utilizing a shorter 8-bit offset field but with an addressing mode specified within a manipulation mode control field of the data access instruction.

Abstract: A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is read with a first bit length from a first bit field in the first memory unit starting at a first start point. The bit segment that has been read is stored in the first bit field in the second memory unit starting at a second start point. The first or the second start points is updated by a predetermined value and the updated start point is stored for subsequent method steps.

Abstract: A memory mapped register file is disclosed for a data processing system that comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of registers addressable by an encoded address, wherein the encoded address corresponds to a respective one of the plurality of registers and a corresponding processor mode. The input ports receive inputs for addressing at least one register using an encoded address. The output ports output data from at least register addressable by an encoded address.

Abstract: A memory access method includes: obtaining a, b, and c from a program code for accessing a memory with a triple loop in a program, a being a number of values which an inner-most loop variable of the triple loop may have, b being a number of values which a middle loop variable of the triple loop may have, and c being a number of values which an outer-most loop variable of the triple loop may have; obtaining a starting address of the memory accessed by the triple loop; and obtaining an a×b×c number of addresses of the memory accessed by the triple loop using the starting address and a function.

Abstract: An address generation apparatus and an operation apparatus are shown to generate a complex address and to suppress an increase of a mounted area even if a bit width of a counter is widened. An address generation apparatus has at least one counter setting a count value by an operated value, at least one operation section being arranged corresponding to the counter respectively, operating a supplied step value and a count value of the corresponding counter in response to a control signal and supplying the operated count value to the corresponding counter, a selection section selecting either a set value or the operation result of the operation section in response to a control signal and inputting it to the counter, and an address operation section performing an operation in response to a control signal for the count value of the counter and outputting the operation result as an address.

Abstract: Briefly, a system and a method to efficiently track changes in memory or storage areas, for example, in cache memories of computers and electronic systems. A method in accordance with an exemplary embodiment of the invention includes, for example, updating a tracking list with an address and/or a corresponding address to be updated of a changed entry in an intermediate memory. A system in accordance with an exemplary embodiment of the invention may include, for example, a tracking unit to track the locations of potential data discrepancies between a reference memory and an intermediate memory.

Abstract: A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.

Abstract: Systems and methods are provided for accessing thread private data in a computer. In one embodiment, a method is provided for accessing thread private data in a computer for a program executed by using a plurality of threads, wherein each of the plurality of threads may be associated with a different area of its respective stack for storage of thread private data. Further, the stacks of threads may cover a coherent address space in a memory of the computer, starting at a base address. The method may include determining a thread identifier of the one of the plurality of threads based on the base address and a stack pointer of one of the plurality of threads. In addition, the method may include accessing thread private data of one of the stacks based on the determined thread identifier.

Abstract: A processor includes a memory port for accessing a physical memory under control of an address. A processing unit executing instructions stored in the memory and/or operates on data stored in the memory. An address generation unit (“AGU”) generates address for controlling access to the memory; the AGU being associated with a plurality of N registers enabling the AGU to generate the address under control of an address generation mechanism. A memory unit is operative to save/load k of the N registers, where 2<=k<=N, triggered by one operation. To this end, the memory unit includes a concatenator for concatenating the k registers to one memory word to be written to the memory through the memory port and a splitter for separating a word read from the memory through the memory port into the k registers.

Abstract: A method of managing memory mapped input/output (I/O) for a run-time environment is disclosed, in which opaque references are used for accessing information blocks included in files used in a dynamic run-time environment. The information block is stored in a shared memory space of pages that are each aligned on respective boundaries having addresses that are each some multiple of two raised to an integer power. The opaque reference used for the dynamic run-time environment includes at least an index, or page number reference into a page map of references to the pages of the shared memory space, and an offset value indicating an offset into the referenced page for the beginning of the storage of the information block. Control bits of the opaque reference indicate information such as the mapping mode, e.g., read-only, read-write, or private. Pages which are modified by a process may be written back to a backing store of the file based on control bits which indicate that a page has been modified.

Abstract: A processor is operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the first register-out value and obtaining a second register-out value, and storing the second register-out value into a third register based on the program instruction. The processor is further operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the program instruction and obtaining a second register-out value, and storing the first register-out value into a third register based on the second register-out value.

Abstract: A method and apparatus for improving the operation of a computer processor by utilizing an asymmetric clustered processor architecture are disclosed. The asymmetric clustered processor apparatus includes a narrow cluster, a wide cluster, a steering logic utilizing a cluster predictor for providing a decoded instruction to either the narrow cluster or the wide cluster; address registers which are not part of the ISA, and a translation look-aside buffer for translating the virtual address of a load/store instruction in parallel with an execute stage. The method includes the steps of: predictably steering the instruction to either a W-bit Wide integer cluster or an N-bit Narrow integer cluster, managing the Address register file, and processing any instruction in the Wide integer cluster but processing only N-bit instructions in the Narrow integer cluster.

Abstract: A computerized method for sharing removable storage media in a network, the method comprising associating, in an index entry, a first piece of removable storage media in a first storage device with at least a first storage policy copy and a second storage policy copy; copying, to the first piece of removable storage media, data associated with the first storage policy copy; and copying, to the first piece of removable storage media, data associated with the second storage policy copy.

Abstract: A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logic 0 carry-in and a logic 1 carry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.

Abstract: An integrated device is provided that includes a non-volatile memory having an addressing parallelism and a data parallelism, and a communication interface for interfacing the memory with an external bus. The external bus has a transfer parallelism lower than the addressing parallelism and the data parallelism. The communication interface includes control means for executing multiple reading operations and/or multiple writing operations on the memory according to different modalities in response to corresponding command codes received from the external bus. Also provided is a method of operating such an integrated device.

Abstract: A method and apparatus for determining a stack distance histogram for running software. The method may include receiving a plurality of memory references each including a corresponding address. The method may also include performing a first hash function and a second hash function on each received address. In addition, the method may include selectively storing an indication representative of each corresponding address in a hash table dependent upon results of the first hash function and the second hash function. A stack distance may then be determined based upon contents of the hash table.

Abstract: A method for determining a stack distance including spatial locality for running software. The method may include receiving a plurality of memory references each including a corresponding address. The method may also include performing a merge function on each address corresponding to each received memory reference to generate a modified version of each corresponding address, and then performing a first hash function on the modified version of each corresponding address. In addition, the method may include performing a filter function on each address corresponding to each received memory reference. The method may further include selectively storing an indication representative of the modified version of each corresponding address in a hash table dependent upon results of the first hash function and the filter function. A stack distance may then be determined based upon contents of the hash table.

Abstract: A configuration memory space is scanned to locate an identification register whose value matches a predetermined value. The identification register identifies the location of a structure within the configuration space. The location of the beginning of the structure is used along with a predetermined (known) offset to determine the address of a desired configuration register.

Abstract: A processor is provided with a address calculation unit so as to generate addresses for elements of object oriented data structures in one processor clock cycle.

Abstract: A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data consists of two vectors, which constitute the operands for a permute instruction. Only a limited number of bits are required to index into the table during the execution of this instruction. The remaining bits of each index are used as masks into a series of select instructions. The select instruction chooses between two vector components, based on the mask, and places the selected components into a new vector. The mask is generated by shifting one of the higher order bits of the index to the most significant position, and then propagating that bit throughout a byte, for example by means of an arithmetic shift. This procedure is carried out for all of the index bytes in the vector, to generate a select mask.

Abstract: A semiconductor device comprising a bus master and a bus slave connected by a second bus is provided. A bus control unit (BCU) comprises a first relative address control circuit that performs a process for requesting the access using a relative address to a semiconductor storage medium through the second bus, the process including generation of a relative address corresponding to an absolute address based on the received absolute address and generation of an identification signal indicating the relative address. The memory controller comprises a second relative address control circuit that decides whether the received access address is a relative address or not and, if the received access address is a relative address, calculates an absolute address corresponding to the relative address.

Abstract: N binary signals are transmitted through a bus of m leads, where m<n, at the rhythm of a train of clock pulses by encoding a first signal on a second signal. The encoding provides for the information associated with the first signal to be included in the second signal within a predetermined time interval of the clock period preceding each reading clock pulse. In this way one obtains a reduction of the switching activity on the bus and therefore a reduction of the energy consumption.

Abstract: The invention comprises a hardware constructed address generator for a circular buffer which can be of any size and be in any position in memory. The address generator calculates both an absolute value and a wrapped value and selects one in accordance with whether the wrapped value falls within the boundaries of the buffer.